Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2612121	1			T1	913		T2	1		T3	1696
all_values[1]	2612121	1			T1	913		T2	1		T3	1696
all_values[2]	2612121	1			T1	913		T2	1		T3	1696
all_values[3]	2612121	1			T1	913		T2	1		T3	1696
all_values[4]	2612121	1			T1	913		T2	1		T3	1696
all_values[5]	2612121	1			T1	913		T2	1		T3	1696
all_values[6]	2612121	1			T1	913		T2	1		T3	1696
all_values[7]	2612121	1			T1	913		T2	1		T3	1696

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20675888

1

T1

7304

T2

8

T3

13568

auto[1]

221080

1

T15

24737

T20

69

T22

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20871501

1

T1

7304

T2

8

T3

13568

auto[1]

25467

1

T13

40

T15

159

T42

32

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2594702	1			T1	913		T2	1		T3	1696
all_values[0]	auto[0]	auto[1]	12044	1			T13	35		T15	51		T42	16
all_values[0]	auto[1]	auto[0]	5168	1			T15	4924		T20	6		T22	2
all_values[0]	auto[1]	auto[1]	207	1			T15	22		T20	2		T29	3
all_values[1]	auto[0]	auto[0]	2540162	1			T1	913		T2	1		T3	1696
all_values[1]	auto[0]	auto[1]	7711	1			T13	5		T15	53		T42	16
all_values[1]	auto[1]	auto[0]	63847	1			T15	4938		T20	2		T22	1
all_values[1]	auto[1]	auto[1]	401	1			T15	5		T20	1		T22	3
all_values[2]	auto[0]	auto[0]	2576769	1			T1	913		T2	1		T3	1696
all_values[2]	auto[0]	auto[1]	3065	1			T15	3		T17	82		T53	69
all_values[2]	auto[1]	auto[0]	32040	1			T15	4942		T20	11		T22	2
all_values[2]	auto[1]	auto[1]	247	1			T15	3		T20	5		T22	2
all_values[3]	auto[0]	auto[0]	2585894	1			T1	913		T2	1		T3	1696
all_values[3]	auto[0]	auto[1]	199	1			T15	2		T150	1		T20	5
all_values[3]	auto[1]	auto[0]	25861	1			T15	2		T20	7		T22	1
all_values[3]	auto[1]	auto[1]	167	1			T15	1		T20	5		T22	1
all_values[4]	auto[0]	auto[0]	2576260	1			T1	913		T2	1		T3	1696
all_values[4]	auto[0]	auto[1]	208	1			T15	1		T20	1		T22	1
all_values[4]	auto[1]	auto[0]	35462	1			T15	3		T20	7		T22	5
all_values[4]	auto[1]	auto[1]	191	1			T15	2		T20	1		T22	3
all_values[5]	auto[0]	auto[0]	2601335	1			T1	913		T2	1		T3	1696
all_values[5]	auto[0]	auto[1]	171	1			T15	1		T20	4		T29	5
all_values[5]	auto[1]	auto[0]	10464	1			T15	4942		T20	3		T22	4
all_values[5]	auto[1]	auto[1]	151	1			T15	4		T20	2		T22	1
all_values[6]	auto[0]	auto[0]	2611478	1			T1	913		T2	1		T3	1696
all_values[6]	auto[0]	auto[1]	171	1			T15	2		T20	6		T22	2
all_values[6]	auto[1]	auto[0]	274	1			T15	1		T20	5		T22	5
all_values[6]	auto[1]	auto[1]	198	1			T15	4		T20	8		T22	3
all_values[7]	auto[0]	auto[0]	2565550	1			T1	913		T2	1		T3	1696
all_values[7]	auto[0]	auto[1]	169	1			T15	2		T20	5		T22	3
all_values[7]	auto[1]	auto[0]	46235	1			T15	4941		T20	2		T22	1
all_values[7]	auto[1]	auto[1]	167	1			T15	3		T20	2		T22	4