Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33231	1			T5	24		T12	2		T13	54
auto[SpiFlashAddrCfg]	7402	1			T5	8		T7	14		T13	14
auto[SpiFlashAddr3b]	8832	1			T5	19		T7	8		T11	1
auto[SpiFlashAddr4b]	6984	1			T4	1		T5	9		T13	19

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31651

1

T4

1

T5

34

T7

22

auto[1]

24798

1

T5

26

T13

44

T15

52

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29696

1

T5

25

T7

4

T11

1

auto[1]

26753

1

T4

1

T5

35

T7

18

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37628	1			T5	30		T7	12		T12	2
values[1]	1072	1			T5	2		T13	6		T15	3
values[2]	1415	1			T13	3		T15	5		T42	9
values[3]	1387	1			T5	6		T13	5		T15	4
values[4]	1384	1			T5	2		T7	4		T13	4
values[5]	1423	1			T5	1		T13	5		T15	7
values[6]	1414	1			T13	4		T15	4		T42	15
values[7]	1401	1			T5	1		T11	1		T13	4
values[8]	9325	1			T4	1		T5	18		T7	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27927

1

T5

60

T7

22

T12

2

auto[1]

28522

1

T4

1

T11

1

T13

109

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53313

1

T4

1

T5

51

T7

22

write

3136

1

T5

9

T13

6

T15

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18309

1

T4

1

T5

19

T7

10

valids[0x1]

38140

1

T5

41

T7

12

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1558	1			T5	2		T13	2		T15	2
internal_process_ops[0x5a]	1510	1			T7	2		T13	3		T15	2
internal_process_ops[0x05]	19905	1			T5	2		T13	14		T15	19
internal_process_ops[0x35]	1507	1			T5	4		T13	1		T15	6
internal_process_ops[0x15]	1452	1			T5	2		T13	9		T15	3
internal_process_ops[0x03]	980	1			T5	1		T15	2		T26	2
internal_process_ops[0x0b]	947	1			T5	3		T11	1		T13	1
internal_process_ops[0x3b]	994	1			T13	1		T15	2		T24	2
internal_process_ops[0x6b]	935	1			T5	3		T7	4		T13	2
internal_process_ops[0xbb]	1003	1			T5	2		T13	1		T15	4
internal_process_ops[0xeb]	976	1			T4	1		T5	2		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54893

1

T4

1

T5

58

T7

22

auto[1]

1556

1

T5

2

T13

3

T15

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54152

1

T4

1

T5

54

T7

22

auto[1]

2297

1

T5

6

T13

6

T15

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9386

1

T5

16

T12

2

T15

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5517

1

T5

5

T15

9

T42

69

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1957

1

T5

4

T7

14

T15

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1679

1

T5

2

T15

6

T42

30

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2347

1

T5

4

T7

8

T15

1

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2041

1

T5

11

T15

5

T42

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1910

1

T5

7

T15

1

T16

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1612

1

T5

2

T15

2

T42

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T16

2

T17

5

T49

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

69

1

T5

1

T17

4

T45

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T5

2

T42

2

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T42

7

T47

3

T49

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T5

1

T42

1

T182

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T17

1

T52

1

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

113

1

T5

1

T15

2

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T17

2

T45

4

T48

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T42

3

T17

2

T49

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T5

1

T15

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T5

3

T17

2

T47

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T15

1

T42

1

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T60

2

T183

2

T184

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T17

3

T45

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

70

1

T15

1

T42

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T42

3

T17

2

T46

7

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9764

1

T13

38

T15

12

T17

13

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7845

1

T13

14

T15

14

T17

118

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1567

1

T13

5

T14

1

T15

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1396

1

T13

9

T17

3

T51

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1818

1

T11

1

T13

11

T15

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1824

1

T13

10

T15

7

T17

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1360

1

T4

1

T13

10

T15

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1290

1

T13

6

T15

3

T17

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T17

2

T51

2

T81

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

71

1

T15

1

T17

1

T81

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T13

1

T81

1

T83

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

100

1

T13

1

T17

3

T83

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T15

2

T17

2

T81

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

117

1

T17

1

T51

1

T81

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T15

1

T83

3

T53

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

111

1

T15

1

T81

1

T53

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T13

1

T15

1

T17

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

116

1

T17

1

T51

1

T81

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

127

1

T81

5

T83

2

T53

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T17

1

T81

2

T83

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

126

1

T15

2

T17

5

T51

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

121

1

T83

2

T82

2

T85

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T13

1

T83

3

T82

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

105

1

T13

2

T17

1

T81

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3619	1			T5	5		T7	2		T12	2
auto[0]	values[0]	valids[0x1]	13921	1			T5	25		T7	10		T15	15
auto[0]	values[1]	valids[0x1]	553	1			T5	2		T15	1		T42	5
auto[0]	values[2]	valids[0x0]	481	1			T15	1		T42	4		T17	11
auto[0]	values[2]	valids[0x1]	353	1			T42	5		T17	6		T52	2
auto[0]	values[3]	valids[0x0]	499	1			T15	1		T42	9		T17	10
auto[0]	values[3]	valids[0x1]	315	1			T5	6		T15	3		T42	2
auto[0]	values[4]	valids[0x0]	522	1			T7	4		T42	5		T17	6
auto[0]	values[4]	valids[0x1]	253	1			T5	2		T15	3		T42	4
auto[0]	values[5]	valids[0x0]	504	1			T5	1		T15	2		T42	4
auto[0]	values[5]	valids[0x1]	262	1			T15	5		T120	2		T42	6
auto[0]	values[6]	valids[0x0]	517	1			T15	2		T42	9		T17	6
auto[0]	values[6]	valids[0x1]	259	1			T42	6		T17	6		T185	2
auto[0]	values[7]	valids[0x0]	452	1			T5	1		T26	2		T42	5
auto[0]	values[7]	valids[0x1]	275	1			T15	1		T16	2		T42	2
auto[0]	values[8]	valids[0x0]	3242	1			T5	12		T7	4		T15	2
auto[0]	values[8]	valids[0x1]	1900	1			T5	6		T7	2		T15	2
auto[1]	values[0]	valids[0x0]	3800	1			T13	22		T15	6		T17	15
auto[1]	values[0]	valids[0x1]	16288	1			T13	37		T15	31		T17	144
auto[1]	values[1]	valids[0x1]	519	1			T13	6		T15	2		T17	1
auto[1]	values[2]	valids[0x0]	358	1			T13	2		T15	4		T17	2
auto[1]	values[2]	valids[0x1]	223	1			T13	1		T17	2		T51	1
auto[1]	values[3]	valids[0x0]	319	1			T13	2		T17	1		T51	6
auto[1]	values[3]	valids[0x1]	254	1			T13	3		T17	2		T51	1
auto[1]	values[4]	valids[0x0]	366	1			T13	2		T15	3		T17	5
auto[1]	values[4]	valids[0x1]	243	1			T13	2		T17	3		T51	3
auto[1]	values[5]	valids[0x0]	401	1			T13	4		T17	2		T51	7
auto[1]	values[5]	valids[0x1]	256	1			T13	1		T51	2		T81	2
auto[1]	values[6]	valids[0x0]	373	1			T13	4		T15	2		T17	4
auto[1]	values[6]	valids[0x1]	265	1			T17	1		T51	1		T81	2
auto[1]	values[7]	valids[0x0]	400	1			T13	1		T51	3		T81	4
auto[1]	values[7]	valids[0x1]	274	1			T11	1		T13	3		T14	1
auto[1]	values[8]	valids[0x0]	2456	1			T4	1		T13	11		T17	16
auto[1]	values[8]	valids[0x1]	1727	1			T13	8		T15	2		T17	4