Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3106692

1

T2

1769

T4

6

T5

4759

auto[1]

32847

1

T5

1004

T13

9

T15

17

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

818289

1

T2

1769

T4

6

T5

142

auto[1]

2321250

1

T5

5621

T13

6566

T15

5539

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	591860	1			T2	332		T4	6		T5	3612
auto[524288:1048575]	362141	1			T2	291		T13	2616		T24	22
auto[1048576:1572863]	334354	1			T2	267		T5	137		T13	1
auto[1572864:2097151]	366674	1			T2	53		T11	408		T12	2
auto[2097152:2621439]	415776	1			T2	112		T5	581		T11	12
auto[2621440:3145727]	336128	1			T2	314		T5	1095		T11	7860
auto[3145728:3670015]	384933	1			T2	6		T5	23		T11	37
auto[3670016:4194303]	347673	1			T2	394		T5	315		T13	3399

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2355981

1

T2

76

T4

4

T5

5758

auto[1]

783558

1

T2

1693

T4

2

T5

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2694978

1

T2

1769

T4

6

T5

5745

auto[1]

444561

1

T5

18

T12

2

T13

772

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	169821	1			T2	332		T4	6		T5	29
auto[0]	auto[0]	auto[0:524287]	auto[1]	363227	1			T5	3575		T13	513		T15	4720
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	71806	1			T2	291		T13	7		T24	22
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	225205	1			T13	2606		T42	276		T17	2094
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	89461	1			T2	267		T13	1		T26	113
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	169526	1			T42	4		T17	899		T51	152
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	93533	1			T2	53		T11	408		T12	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	218058	1			T15	769		T42	3202		T17	1043
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	70461	1			T2	112		T5	8		T11	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	283973	1			T5	1		T13	33		T15	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103488	1			T2	314		T5	14		T11	7860
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	189398	1			T5	1079		T13	1		T15	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	91892	1			T2	6		T5	21		T11	37
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	245014	1			T13	19		T42	7		T17	2478
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105030	1			T2	394		T5	19		T13	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	177499	1			T5	2		T13	2623		T15	36
auto[0]	auto[1]	auto[0:524287]	auto[0]	2376	1			T12	2		T13	2		T15	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	50454	1			T17	256		T52	2633		T45	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1805	1			T42	1		T17	3		T45	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59330	1			T42	1		T17	2122		T81	1912
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	4999	1			T5	6		T42	4		T17	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	66163	1			T42	1195		T17	3503		T52	2989
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1052	1			T42	5		T17	7		T51	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51072	1			T42	513		T17	521		T51	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2429	1			T5	5		T42	3		T45	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54377	1			T42	3338		T83	256		T47	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1768	1			T45	1		T83	7		T47	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	37809	1			T17	128		T53	172		T82	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2012	1			T42	3		T17	7		T45	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42527	1			T42	1		T17	5036		T82	1344
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2039	1			T13	2		T42	2		T17	9
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	59088	1			T13	768		T17	912		T47	1479
auto[1]	auto[0]	auto[0:524287]	auto[0]	591	1			T5	8		T13	1		T15	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	4925	1			T13	2		T15	3		T16	69
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	483	1			T13	2		T42	1		T17	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3221	1			T13	1		T42	11		T17	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	388	1			T5	3		T42	4		T17	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2279	1			T5	128		T42	36		T17	18
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	362	1			T15	1		T17	2		T51	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2058	1			T15	1		T17	18		T51	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	484	1			T5	12		T15	2		T42	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3717	1			T5	548		T15	5		T42	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	423	1			T5	2		T13	1		T17	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2487	1			T17	87		T45	159		T82	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	421	1			T5	2		T13	1		T17	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2304	1			T17	10		T46	36		T81	79
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	490	1			T5	6		T13	1		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2953	1			T5	288		T42	12		T17	107
auto[1]	auto[1]	auto[0:524287]	auto[0]	101	1			T45	1		T49	1		T82	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	365	1			T45	10		T49	1		T82	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	68	1			T42	1		T81	1		T47	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	223	1			T42	1		T81	1		T49	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	114	1			T17	3		T45	2		T83	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1424	1			T17	64		T45	59		T85	25
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T42	1		T17	3		T46	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	451	1			T42	4		T17	12		T46	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	64	1			T5	7		T85	1		T232	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	271	1			T85	18		T232	14		T220	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	74	1			T82	1		T84	1		T183	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	681	1			T84	76		T183	21		T22	31
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	94	1			T42	1		T17	1		T82	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	669	1			T42	1		T17	3		T82	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	72	1			T17	2		T47	7		T84	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	502	1			T17	57		T47	64		T84	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1897978	1			T2	76		T4	4		T5	4748
auto[0]	auto[0]	auto[1]	769414	1			T2	1693		T4	2		T11	8325
auto[0]	auto[1]	auto[0]	425847	1			T5	11		T12	1		T13	772
auto[0]	auto[1]	auto[1]	13453	1			T12	1		T17	3		T45	2
auto[1]	auto[0]	auto[0]	27012	1			T5	993		T13	8		T15	17
auto[1]	auto[0]	auto[1]	574	1			T5	4		T13	1		T42	9
auto[1]	auto[1]	auto[0]	5144	1			T5	6		T42	8		T17	145
auto[1]	auto[1]	auto[1]	117	1			T5	1		T42	1		T81	1