Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2612121	1			T1	913		T2	1		T3	1696
all_pins[1]	2612121	1			T1	913		T2	1		T3	1696
all_pins[2]	2612121	1			T1	913		T2	1		T3	1696
all_pins[3]	2612121	1			T1	913		T2	1		T3	1696
all_pins[4]	2612121	1			T1	913		T2	1		T3	1696
all_pins[5]	2612121	1			T1	913		T2	1		T3	1696
all_pins[6]	2612121	1			T1	913		T2	1		T3	1696
all_pins[7]	2612121	1			T1	913		T2	1		T3	1696

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20894080	1			T1	7304		T2	8		T3	13568
values[0x1]	2888	1			T15	575		T20	26		T22	17
transitions[0x0=>0x1]	2529	1			T15	558		T20	20		T22	13
transitions[0x1=>0x0]	2538	1			T15	558		T20	20		T22	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2611909	1			T1	913		T2	1		T3	1696
all_pins[0]	values[0x1]	212	1			T15	27		T20	2		T29	3
all_pins[0]	transitions[0x0=>0x1]	162	1			T15	19		T20	2		T29	1
all_pins[0]	transitions[0x1=>0x0]	374	1			T15	1		T20	1		T22	3
all_pins[1]	values[0x0]	2611697	1			T1	913		T2	1		T3	1696
all_pins[1]	values[0x1]	424	1			T15	9		T20	1		T22	3
all_pins[1]	transitions[0x0=>0x1]	380	1			T15	7		T20	1		T22	3
all_pins[1]	transitions[0x1=>0x0]	208	1			T15	2		T20	5		T22	2
all_pins[2]	values[0x0]	2611869	1			T1	913		T2	1		T3	1696
all_pins[2]	values[0x1]	252	1			T15	4		T20	5		T22	2
all_pins[2]	transitions[0x0=>0x1]	209	1			T15	3		T20	1		T22	2
all_pins[2]	transitions[0x1=>0x0]	124	1			T20	1		T22	1		T29	2
all_pins[3]	values[0x0]	2611954	1			T1	913		T2	1		T3	1696
all_pins[3]	values[0x1]	167	1			T15	1		T20	5		T22	1
all_pins[3]	transitions[0x0=>0x1]	116	1			T20	5		T22	1		T29	4
all_pins[3]	transitions[0x1=>0x0]	140	1			T15	1		T20	1		T22	3
all_pins[4]	values[0x0]	2611930	1			T1	913		T2	1		T3	1696
all_pins[4]	values[0x1]	191	1			T15	2		T20	1		T22	3
all_pins[4]	transitions[0x0=>0x1]	145	1			T15	1		T22	2		T29	3
all_pins[4]	transitions[0x1=>0x0]	1231	1			T15	524		T20	1		T29	1
all_pins[5]	values[0x0]	2610844	1			T1	913		T2	1		T3	1696
all_pins[5]	values[0x1]	1277	1			T15	525		T20	2		T22	1
all_pins[5]	transitions[0x0=>0x1]	1239	1			T15	522		T20	2		T22	1
all_pins[5]	transitions[0x1=>0x0]	160	1			T15	1		T20	8		T22	3
all_pins[6]	values[0x0]	2611923	1			T1	913		T2	1		T3	1696
all_pins[6]	values[0x1]	198	1			T15	4		T20	8		T22	3
all_pins[6]	transitions[0x0=>0x1]	150	1			T15	3		T20	8		T22	1
all_pins[6]	transitions[0x1=>0x0]	119	1			T15	2		T20	2		T22	2
all_pins[7]	values[0x0]	2611954	1			T1	913		T2	1		T3	1696
all_pins[7]	values[0x1]	167	1			T15	3		T20	2		T22	4
all_pins[7]	transitions[0x0=>0x1]	128	1			T15	3		T20	1		T22	3
all_pins[7]	transitions[0x1=>0x0]	182	1			T15	27		T20	1		T29	2