Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16296

1

T5

34

T7

22

T12

2

auto[1]

11631

1

T5

26

T15

26

T42

147

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2978	1			T5	20		T42	32		T17	64
values[1]	3539	1			T7	22		T42	73		T17	192
values[2]	3428	1			T24	4		T26	10		T42	44
values[3]	3239	1			T12	2		T42	40		T17	135
values[4]	3246	1			T16	91		T120	2		T42	20
values[5]	3254	1			T5	20		T15	26		T42	42
values[6]	4274	1			T5	20		T15	20		T42	82
values[7]	3969	1			T42	20		T17	105		T52	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3452	1			T42	95		T17	40		T52	21
values[1]	4139	1			T12	2		T42	40		T17	55
values[2]	2843	1			T7	22		T15	46		T17	169
values[3]	3479	1			T16	91		T42	22		T17	20
values[4]	3448	1			T5	20		T24	4		T42	96
values[5]	3976	1			T26	10		T42	20		T17	96
values[6]	2975	1			T120	2		T42	20		T17	116
values[7]	3615	1			T5	40		T42	60		T157	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	212	1			T49	15		T183	18		T229	11
auto[0]	values[0]	values[1]	247	1			T17	12		T49	12		T171	6
auto[0]	values[0]	values[2]	285	1			T17	17		T196	8		T244	22
auto[0]	values[0]	values[3]	254	1			T46	13		T215	12		T205	15
auto[0]	values[0]	values[4]	129	1			T42	21		T17	10		T211	8
auto[0]	values[0]	values[5]	215	1			T45	14		T56	10		T259	6
auto[0]	values[0]	values[6]	143	1			T49	12		T260	6		T227	15
auto[0]	values[0]	values[7]	154	1			T5	11		T45	7		T209	6
auto[0]	values[1]	values[0]	320	1			T42	25		T45	13		T246	22
auto[0]	values[1]	values[1]	315	1			T55	25		T164	23		T206	7
auto[0]	values[1]	values[2]	157	1			T7	22		T214	8		T207	12
auto[0]	values[1]	values[3]	350	1			T17	14		T185	14		T261	6
auto[0]	values[1]	values[4]	216	1			T45	12		T49	25		T208	28
auto[0]	values[1]	values[5]	167	1			T17	11		T176	2		T209	12
auto[0]	values[1]	values[6]	198	1			T17	9		T215	6		T262	60
auto[0]	values[1]	values[7]	241	1			T42	29		T263	10		T78	18
auto[0]	values[2]	values[0]	294	1			T49	7		T50	17		T214	8
auto[0]	values[2]	values[1]	397	1			T45	82		T47	10		T251	17
auto[0]	values[2]	values[2]	80	1			T264	6		T265	9		T227	14
auto[0]	values[2]	values[3]	223	1			T50	9		T266	10		T196	14
auto[0]	values[2]	values[4]	351	1			T24	4		T42	7		T17	101
auto[0]	values[2]	values[5]	321	1			T26	10		T267	6		T183	14
auto[0]	values[2]	values[6]	314	1			T17	8		T178	10		T268	20
auto[0]	values[2]	values[7]	161	1			T218	16		T269	9		T140	14
auto[0]	values[3]	values[0]	174	1			T42	15		T17	30		T230	10
auto[0]	values[3]	values[1]	327	1			T12	2		T17	12		T49	13
auto[0]	values[3]	values[2]	168	1			T17	30		T47	9		T111	13
auto[0]	values[3]	values[3]	117	1			T209	33		T214	13		T215	10
auto[0]	values[3]	values[4]	295	1			T49	9		T270	18		T260	18
auto[0]	values[3]	values[5]	369	1			T49	11		T210	8		T215	12
auto[0]	values[3]	values[6]	139	1			T17	10		T45	14		T241	22
auto[0]	values[3]	values[7]	307	1			T49	24		T183	57		T208	13
auto[0]	values[4]	values[0]	358	1			T63	24		T96	13		T215	26
auto[0]	values[4]	values[1]	240	1			T52	12		T229	14		T271	20
auto[0]	values[4]	values[2]	188	1			T107	4		T215	10		T196	9
auto[0]	values[4]	values[3]	330	1			T16	91		T272	13		T262	12
auto[0]	values[4]	values[4]	108	1			T111	19		T248	9		T207	11
auto[0]	values[4]	values[5]	264	1			T42	10		T182	16		T215	30
auto[0]	values[4]	values[6]	116	1			T120	2		T45	10		T215	11
auto[0]	values[4]	values[7]	288	1			T49	8		T214	13		T250	13
auto[0]	values[5]	values[0]	156	1			T52	13		T45	25		T76	4
auto[0]	values[5]	values[1]	197	1			T42	12		T50	13		T273	6
auto[0]	values[5]	values[2]	184	1			T15	8		T250	20		T274	31
auto[0]	values[5]	values[3]	350	1			T42	12		T45	72		T96	10
auto[0]	values[5]	values[4]	157	1			T61	2		T111	11		T225	20
auto[0]	values[5]	values[5]	175	1			T214	24		T275	6		T94	10
auto[0]	values[5]	values[6]	288	1			T234	10		T276	4		T208	12
auto[0]	values[5]	values[7]	309	1			T5	12		T17	21		T47	11
auto[0]	values[6]	values[0]	209	1			T42	19		T60	2		T111	8
auto[0]	values[6]	values[1]	345	1			T277	74		T209	13		T278	8
auto[0]	values[6]	values[2]	332	1			T15	12		T46	14		T50	14
auto[0]	values[6]	values[3]	208	1			T250	18		T260	14		T272	11
auto[0]	values[6]	values[4]	479	1			T5	11		T42	12		T17	36
auto[0]	values[6]	values[5]	340	1			T184	16		T243	6		T247	36
auto[0]	values[6]	values[6]	284	1			T42	16		T47	13		T205	15
auto[0]	values[6]	values[7]	241	1			T42	13		T157	2		T35	2
auto[0]	values[7]	values[0]	370	1			T45	130		T46	19		T225	17
auto[0]	values[7]	values[1]	308	1			T42	15		T98	10		T279	2
auto[0]	values[7]	values[2]	257	1			T17	47		T96	14		T230	14
auto[0]	values[7]	values[3]	294	1			T111	16		T208	10		T280	14
auto[0]	values[7]	values[4]	256	1			T45	14		T49	10		T209	40
auto[0]	values[7]	values[5]	449	1			T50	10		T111	12		T209	23
auto[0]	values[7]	values[6]	255	1			T52	14		T46	106		T111	21
auto[0]	values[7]	values[7]	321	1			T209	20		T215	8		T230	7
auto[1]	values[0]	values[0]	164	1			T49	8		T183	41		T229	9
auto[1]	values[0]	values[1]	257	1			T17	8		T48	18		T49	12
auto[1]	values[0]	values[2]	135	1			T17	7		T196	12		T211	12
auto[1]	values[0]	values[3]	137	1			T46	7		T215	12		T205	12
auto[1]	values[0]	values[4]	104	1			T42	11		T17	10		T238	18
auto[1]	values[0]	values[5]	128	1			T45	26		T56	10		T141	6
auto[1]	values[0]	values[6]	211	1			T49	8		T281	12		T260	16
auto[1]	values[0]	values[7]	203	1			T5	9		T45	13		T209	14
auto[1]	values[1]	values[0]	211	1			T42	8		T45	7		T47	5
auto[1]	values[1]	values[1]	332	1			T55	7		T164	10		T206	13
auto[1]	values[1]	values[2]	122	1			T214	13		T207	9		T282	11
auto[1]	values[1]	values[3]	140	1			T17	6		T213	8		T283	5
auto[1]	values[1]	values[4]	265	1			T45	22		T49	17		T208	9
auto[1]	values[1]	values[5]	205	1			T17	85		T209	8		T284	10
auto[1]	values[1]	values[6]	178	1			T17	67		T215	64		T262	9
auto[1]	values[1]	values[7]	122	1			T42	11		T250	10		T285	13
auto[1]	values[2]	values[0]	130	1			T49	13		T50	3		T214	12
auto[1]	values[2]	values[1]	277	1			T45	12		T47	10		T251	8
auto[1]	values[2]	values[2]	72	1			T265	19		T227	6		T286	14
auto[1]	values[2]	values[3]	110	1			T50	11		T196	6		T207	7
auto[1]	values[2]	values[4]	166	1			T42	37		T17	6		T249	8
auto[1]	values[2]	values[5]	333	1			T183	40		T210	7		T282	13
auto[1]	values[2]	values[6]	62	1			T17	12		T250	10		T206	5
auto[1]	values[2]	values[7]	137	1			T269	16		T140	6		T287	17
auto[1]	values[3]	values[0]	200	1			T42	25		T17	10		T288	24
auto[1]	values[3]	values[1]	210	1			T17	23		T49	7		T289	8
auto[1]	values[3]	values[2]	92	1			T17	10		T47	11		T111	8
auto[1]	values[3]	values[3]	126	1			T209	10		T214	7		T215	12
auto[1]	values[3]	values[4]	216	1			T253	8		T49	17		T260	11
auto[1]	values[3]	values[5]	196	1			T49	9		T210	12		T215	8
auto[1]	values[3]	values[6]	115	1			T17	10		T45	6		T225	7
auto[1]	values[3]	values[7]	188	1			T49	16		T183	10		T208	7
auto[1]	values[4]	values[0]	194	1			T96	7		T215	9		T36	12
auto[1]	values[4]	values[1]	161	1			T52	10		T229	6		T290	10
auto[1]	values[4]	values[2]	161	1			T215	10		T196	11		T265	8
auto[1]	values[4]	values[3]	277	1			T272	64		T262	21		T56	40
auto[1]	values[4]	values[4]	131	1			T111	3		T248	83		T207	9
auto[1]	values[4]	values[5]	186	1			T42	10		T215	6		T225	6
auto[1]	values[4]	values[6]	91	1			T45	10		T215	9		T94	12
auto[1]	values[4]	values[7]	153	1			T49	12		T214	7		T250	7
auto[1]	values[5]	values[0]	208	1			T52	8		T45	27		T249	10
auto[1]	values[5]	values[1]	119	1			T42	8		T50	7		T291	10
auto[1]	values[5]	values[2]	165	1			T15	18		T292	6		T250	20
auto[1]	values[5]	values[3]	285	1			T42	10		T45	9		T96	10
auto[1]	values[5]	values[4]	138	1			T111	10		T235	20		T225	20
auto[1]	values[5]	values[5]	106	1			T214	8		T94	10		T293	9
auto[1]	values[5]	values[6]	118	1			T208	8		T250	8		T227	8
auto[1]	values[5]	values[7]	299	1			T5	8		T17	31		T47	9
auto[1]	values[6]	values[0]	93	1			T42	3		T111	12		T96	7
auto[1]	values[6]	values[1]	261	1			T209	22		T249	10		T214	7
auto[1]	values[6]	values[2]	213	1			T15	8		T46	6		T50	6
auto[1]	values[6]	values[3]	153	1			T250	2		T260	9		T272	9
auto[1]	values[6]	values[4]	270	1			T5	9		T42	8		T17	28
auto[1]	values[6]	values[5]	305	1			T248	6		T207	9		T242	6
auto[1]	values[6]	values[6]	360	1			T42	4		T47	7		T205	5
auto[1]	values[6]	values[7]	181	1			T42	7		T45	9		T47	5
auto[1]	values[7]	values[0]	159	1			T45	12		T46	6		T225	3
auto[1]	values[7]	values[1]	146	1			T42	5		T255	10		T209	5
auto[1]	values[7]	values[2]	232	1			T17	58		T96	6		T230	7
auto[1]	values[7]	values[3]	125	1			T111	5		T208	10		T94	21
auto[1]	values[7]	values[4]	167	1			T45	6		T49	12		T209	6
auto[1]	values[7]	values[5]	217	1			T50	10		T111	8		T209	38
auto[1]	values[7]	values[6]	103	1			T52	6		T46	14		T111	8
auto[1]	values[7]	values[7]	310	1			T209	8		T215	12		T230	13