Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	318	1			T5	1		T26	6		T42	1
auto[ReadAddrCrossIntoMailbox]	253	1			T5	1		T42	2		T17	2
auto[ReadAddrCrossOutOfMailbox]	270	1			T5	4		T15	1		T42	1
auto[ReadAddrCrossAllMailbox]	188	1			T5	1		T17	3		T52	2
auto[ReadAddrOutsideMailbox]	3350	1			T5	4		T7	4		T15	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2126

1

T5

6

T7

2

T15

7

auto[1]

2253

1

T5

5

T7

2

T15

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	747	1			T5	1		T15	2		T26	2
read_ops[0x0b]	699	1			T5	3		T15	1		T16	4
read_ops[0x3b]	746	1			T15	2		T24	2		T26	2
read_ops[0x6b]	679	1			T5	3		T7	4		T15	1
read_ops[0xbb]	765	1			T5	2		T15	2		T16	2
read_ops[0xeb]	743	1			T5	2		T15	1		T26	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T5	1		T26	1		T17	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T26	1		T50	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T241	2		T214	1		T250	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T50	3		T249	1		T241	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T45	1		T282	1		T274	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T47	1		T209	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T234	1		T45	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T52	1		T234	1		T241	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T15	2		T42	6		T17	6
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T42	5		T17	2		T185	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T42	1		T17	1		T52	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T17	1		T294	1		T208	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T5	1		T50	1		T241	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T183	1		T241	1		T230	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T17	1		T45	1		T46	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T5	1		T208	1		T214	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T17	1		T234	1		T241	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T234	1		T249	1		T208	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T15	1		T16	2		T17	7
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T5	1		T16	2		T42	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T26	1		T210	2		T230	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T26	1		T45	2		T249	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T47	1		T49	1		T215	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T42	1		T46	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T15	1		T45	1		T107	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T42	1		T45	1		T107	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T17	2		T107	1		T267	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T107	1		T267	3		T215	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T24	1		T42	5		T17	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T15	1		T24	1		T42	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T175	1		T209	1		T225	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T45	1		T46	1		T215	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T208	1		T225	1		T295	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T52	1		T45	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T5	1		T276	2		T225	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T5	1		T52	1		T276	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T5	1		T183	1		T250	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T52	1		T229	1		T285	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T7	2		T42	1		T17	7
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T7	2		T15	1		T42	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T111	1		T209	1		T213	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T213	1		T250	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T209	1		T230	1		T211	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T17	1		T249	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T17	2		T52	2		T234	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T17	1		T234	1		T245	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T234	1		T183	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T234	1		T94	2		T227	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T5	2		T15	2		T16	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T16	1		T42	5		T17	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T26	1		T111	1		T214	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T26	1		T46	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T17	1		T47	1		T209	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T42	1		T96	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T209	2		T249	1		T250	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T5	1		T183	1		T96	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T47	1		T111	2		T196	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T215	1		T205	1		T225	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T15	1		T42	2		T17	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T5	1		T42	2		T17	4