Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3576	1			T42	32		T157	2		T17	24
values[1]	2851	1			T5	20		T15	26		T42	20
values[2]	3562	1			T5	20		T7	22		T15	20
values[3]	3098	1			T42	40		T17	94		T52	20
values[4]	3218	1			T26	10		T120	2		T42	53
values[5]	4031	1			T5	20		T42	104		T17	40
values[6]	3162	1			T17	214		T52	43		T253	8
values[7]	4429	1			T12	2		T16	91		T24	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3459	1			T16	91		T157	2		T17	118
values[1]	3413	1			T24	4		T26	10		T17	40
values[2]	3391	1			T5	20		T12	2		T42	113
values[3]	3104	1			T5	40		T42	22		T17	32
values[4]	4038	1			T15	20		T42	40		T17	115
values[5]	3357	1			T15	26		T42	66		T17	136
values[6]	3523	1			T7	22		T42	52		T17	55
values[7]	3642	1			T120	2		T42	60		T17	96

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27201

1

T5

58

T7

22

T12

2

auto[1]

726

1

T5

2

T15

2

T42

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	266	1			T157	2		T49	20		T111	19
auto[0]	values[0]	values[1]	299	1			T107	4		T267	6		T183	66
auto[0]	values[0]	values[2]	452	1			T45	18		T49	22		T284	19
auto[0]	values[0]	values[3]	360	1			T46	115		T205	19		T296	10
auto[0]	values[0]	values[4]	517	1			T49	22		T210	75		T225	18
auto[0]	values[0]	values[5]	410	1			T111	49		T215	35		T230	20
auto[0]	values[0]	values[6]	650	1			T42	32		T98	10		T209	20
auto[0]	values[0]	values[7]	525	1			T17	24		T45	39		T196	20
auto[0]	values[1]	values[0]	339	1			T49	20		T183	24		T278	8
auto[0]	values[1]	values[1]	329	1			T297	6		T250	20		T36	27
auto[0]	values[1]	values[2]	349	1			T42	19		T79	10		T245	22
auto[0]	values[1]	values[3]	328	1			T5	20		T45	33		T276	4
auto[0]	values[1]	values[4]	642	1			T17	63		T182	16		T78	18
auto[0]	values[1]	values[5]	199	1			T15	25		T246	22		T298	12
auto[0]	values[1]	values[6]	269	1			T285	44		T299	17		T300	23
auto[0]	values[1]	values[7]	309	1			T234	10		T209	24		T196	20
auto[0]	values[2]	values[0]	483	1			T17	76		T301	6		T214	20
auto[0]	values[2]	values[1]	639	1			T47	19		T175	32		T183	54
auto[0]	values[2]	values[2]	355	1			T229	20		T302	6		T303	14
auto[0]	values[2]	values[3]	482	1			T5	18		T50	20		T292	6
auto[0]	values[2]	values[4]	366	1			T15	19		T45	19		T47	18
auto[0]	values[2]	values[5]	505	1			T45	20		T230	21		T250	19
auto[0]	values[2]	values[6]	407	1			T7	22		T215	92		T196	20
auto[0]	values[2]	values[7]	239	1			T42	19		T17	20		T266	10
auto[0]	values[3]	values[0]	450	1			T17	41		T49	20		T229	19
auto[0]	values[3]	values[1]	410	1			T52	20		T277	74		T183	33
auto[0]	values[3]	values[2]	400	1			T42	19		T171	6		T251	20
auto[0]	values[3]	values[3]	369	1			T17	31		T45	81		T63	24
auto[0]	values[3]	values[4]	341	1			T47	15		T96	18		T208	20
auto[0]	values[3]	values[5]	225	1			T47	18		T260	45		T207	18
auto[0]	values[3]	values[6]	374	1			T42	20		T49	20		T50	20
auto[0]	values[3]	values[7]	438	1			T17	20		T96	20		T243	6
auto[0]	values[4]	values[0]	233	1			T47	20		T209	19		T55	20
auto[0]	values[4]	values[1]	425	1			T26	10		T49	20		T176	2
auto[0]	values[4]	values[2]	475	1			T42	31		T209	41		T225	20
auto[0]	values[4]	values[3]	349	1			T49	22		T214	20		T213	20
auto[0]	values[4]	values[4]	458	1			T248	92		T207	20		T242	20
auto[0]	values[4]	values[5]	300	1			T50	19		T215	53		T196	17
auto[0]	values[4]	values[6]	241	1			T304	14		T164	39		T206	20
auto[0]	values[4]	values[7]	651	1			T120	2		T42	20		T17	28
auto[0]	values[5]	values[0]	693	1			T263	10		T209	43		T238	18
auto[0]	values[5]	values[1]	369	1			T17	20		T205	24		T250	19
auto[0]	values[5]	values[2]	364	1			T5	20		T185	14		T183	77
auto[0]	values[5]	values[3]	327	1			T215	21		T231	8		T94	19
auto[0]	values[5]	values[4]	326	1			T42	36		T45	20		T46	20
auto[0]	values[5]	values[5]	600	1			T42	42		T45	52		T46	25
auto[0]	values[5]	values[6]	601	1			T17	20		T45	94		T46	20
auto[0]	values[5]	values[7]	667	1			T42	20		T50	16		T249	28
auto[0]	values[6]	values[0]	186	1			T60	2		T209	20		T216	20
auto[0]	values[6]	values[1]	493	1			T17	20		T52	22		T253	8
auto[0]	values[6]	values[2]	345	1			T17	122		T250	20		T207	20
auto[0]	values[6]	values[3]	435	1			T209	64		T96	20		T218	16
auto[0]	values[6]	values[4]	496	1			T17	32		T216	20		T305	10
auto[0]	values[6]	values[5]	469	1			T49	20		T294	6		T184	16
auto[0]	values[6]	values[6]	381	1			T17	35		T209	33		T214	21
auto[0]	values[6]	values[7]	287	1			T52	20		T251	25		T205	22
auto[0]	values[7]	values[0]	722	1			T16	91		T61	2		T96	17
auto[0]	values[7]	values[1]	384	1			T24	4		T255	10		T111	20
auto[0]	values[7]	values[2]	566	1			T12	2		T42	40		T17	20
auto[0]	values[7]	values[3]	370	1			T42	21		T215	22		T94	18
auto[0]	values[7]	values[4]	795	1			T17	20		T45	20		T49	20
auto[0]	values[7]	values[5]	547	1			T42	22		T17	132		T35	2
auto[0]	values[7]	values[6]	496	1			T45	138		T50	20		T289	4
auto[0]	values[7]	values[7]	424	1			T48	14		T49	18		T252	10
auto[1]	values[0]	values[0]	9	1			T49	2		T111	1		T260	2
auto[1]	values[0]	values[1]	4	1			T183	1		T200	1		T306	2
auto[1]	values[0]	values[2]	10	1			T45	2		T284	1		T207	2
auto[1]	values[0]	values[3]	10	1			T46	5		T205	1		T299	1
auto[1]	values[0]	values[4]	17	1			T49	1		T210	3		T225	2
auto[1]	values[0]	values[5]	18	1			T111	1		T215	1		T230	2
auto[1]	values[0]	values[6]	11	1			T199	1		T293	1		T307	1
auto[1]	values[0]	values[7]	18	1			T45	1		T94	3		T207	2
auto[1]	values[1]	values[0]	10	1			T183	2		T208	4		T226	3
auto[1]	values[1]	values[1]	7	1			T36	2		T227	1		T308	1
auto[1]	values[1]	values[2]	9	1			T42	1		T245	2		T309	2
auto[1]	values[1]	values[3]	9	1			T45	1		T225	1		T309	1
auto[1]	values[1]	values[4]	19	1			T225	3		T310	2		T272	1
auto[1]	values[1]	values[5]	13	1			T15	1		T57	5		T311	2
auto[1]	values[1]	values[6]	17	1			T285	3		T299	3		T300	4
auto[1]	values[1]	values[7]	3	1			T209	1		T262	1		T312	1
auto[1]	values[2]	values[0]	19	1			T281	4		T36	1		T272	1
auto[1]	values[2]	values[1]	14	1			T47	1		T175	1		T215	1
auto[1]	values[2]	values[2]	6	1			T226	1		T313	4		T314	1
auto[1]	values[2]	values[3]	10	1			T5	2		T295	1		T315	2
auto[1]	values[2]	values[4]	6	1			T15	1		T45	1		T47	2
auto[1]	values[2]	values[5]	12	1			T230	1		T250	1		T207	1
auto[1]	values[2]	values[6]	12	1			T215	2		T316	2		T317	1
auto[1]	values[2]	values[7]	7	1			T42	1		T57	1		T318	3
auto[1]	values[3]	values[0]	7	1			T17	1		T229	1		T317	1
auto[1]	values[3]	values[1]	11	1			T210	1		T299	1		T169	1
auto[1]	values[3]	values[2]	12	1			T42	1		T319	3		T320	4
auto[1]	values[3]	values[3]	11	1			T17	1		T248	2		T199	2
auto[1]	values[3]	values[4]	11	1			T47	5		T96	2		T300	3
auto[1]	values[3]	values[5]	8	1			T47	2		T260	2		T207	2
auto[1]	values[3]	values[6]	19	1			T242	1		T226	1		T199	5
auto[1]	values[3]	values[7]	12	1			T215	2		T254	2		T282	4
auto[1]	values[4]	values[0]	2	1			T209	1		T223	1		-	-
auto[1]	values[4]	values[1]	6	1			T141	2		T315	3		T321	1
auto[1]	values[4]	values[2]	13	1			T42	2		T213	3		T57	1
auto[1]	values[4]	values[3]	13	1			T49	2		T315	1		T286	3
auto[1]	values[4]	values[4]	13	1			T269	3		T322	1		T323	1
auto[1]	values[4]	values[5]	9	1			T50	1		T215	2		T196	3
auto[1]	values[4]	values[6]	7	1			T164	1		T324	3		T311	3
auto[1]	values[4]	values[7]	23	1			T17	4		T207	1		T56	3
auto[1]	values[5]	values[0]	11	1			T196	2		T230	1		T265	3
auto[1]	values[5]	values[1]	7	1			T205	3		T250	1		T325	1
auto[1]	values[5]	values[2]	9	1			T183	1		T214	1		T250	2
auto[1]	values[5]	values[3]	6	1			T215	1		T94	1		T326	2
auto[1]	values[5]	values[4]	13	1			T42	4		T211	2		T283	3
auto[1]	values[5]	values[5]	17	1			T42	2		T111	1		T213	1
auto[1]	values[5]	values[6]	8	1			T47	1		T214	2		T213	1
auto[1]	values[5]	values[7]	13	1			T50	4		T249	1		T215	3
auto[1]	values[6]	values[0]	4	1			T250	1		T56	2		T327	1
auto[1]	values[6]	values[1]	7	1			T111	2		T285	1		T223	1
auto[1]	values[6]	values[2]	14	1			T17	5		T262	1		T321	4
auto[1]	values[6]	values[3]	13	1			T209	2		T250	1		T328	2
auto[1]	values[6]	values[4]	6	1			T272	1		T316	1		T141	1
auto[1]	values[6]	values[5]	6	1			T225	1		T206	1		T227	2
auto[1]	values[6]	values[6]	12	1			T209	2		T317	2		T300	2
auto[1]	values[6]	values[7]	8	1			T52	1		T205	1		T250	5
auto[1]	values[7]	values[0]	25	1			T96	3		T283	5		T56	4
auto[1]	values[7]	values[1]	9	1			T260	1		T207	1		T242	1
auto[1]	values[7]	values[2]	12	1			T209	2		T309	1		T300	3
auto[1]	values[7]	values[3]	12	1			T42	1		T215	2		T94	2
auto[1]	values[7]	values[4]	12	1			T111	2		T249	1		T322	4
auto[1]	values[7]	values[5]	19	1			T17	4		T46	3		T214	2
auto[1]	values[7]	values[6]	18	1			T45	4		T289	4		T272	1
auto[1]	values[7]	values[7]	18	1			T48	4		T49	2		T214	1