Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	772	1			T15	10		T20	15		T22	10
all_values[1]	772	1			T15	10		T20	15		T22	10
all_values[2]	772	1			T15	10		T20	15		T22	10
all_values[3]	772	1			T15	10		T20	15		T22	10
all_values[4]	772	1			T15	10		T20	15		T22	10
all_values[5]	772	1			T15	10		T20	15		T22	10
all_values[6]	772	1			T15	10		T20	15		T22	10
all_values[7]	772	1			T15	10		T20	15		T22	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3363

1

T15

35

T20

64

T22

45

auto[1]

2813

1

T15

45

T20

56

T22

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2462

1

T15

35

T20

47

T22

30

auto[1]

3714

1

T15

45

T20

73

T22

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3516

1

T15

48

T20

66

T22

43

auto[1]

2660

1

T15

32

T20

54

T22

37

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	171	1			T15	3		T20	4		T22	3
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T20	1		T22	1		T31	1
all_values[0]	auto[0]	auto[1]	auto[0]	111	1			T15	3		T20	4		T22	3
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T15	1		T29	1		T180	3
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T20	2		T22	3		T29	4
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T15	3		T20	4		T29	2
all_values[1]	auto[0]	auto[0]	auto[0]	151	1			T15	3		T20	4		T22	3
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T15	1		T20	4		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	132	1			T15	2		T20	1		T29	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T15	1		T22	2		T29	1
all_values[1]	auto[1]	auto[0]	auto[1]	200	1			T15	1		T20	4		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	129	1			T15	2		T20	2		T22	3
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T20	1		T22	3		T29	3
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T22	1		T29	1
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T15	3		T20	4		T22	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T20	2		T29	2		T180	2
all_values[2]	auto[1]	auto[0]	auto[1]	163	1			T15	3		T20	3		T22	2
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T15	3		T20	5		T22	3
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T15	3		T20	2		T22	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T20	2		T22	1		T180	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T15	2		T20	1		T31	2
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T15	1		T20	2		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	187	1			T15	4		T20	4		T22	5
all_values[3]	auto[1]	auto[1]	auto[1]	141	1			T20	4		T22	2		T29	5
all_values[4]	auto[0]	auto[0]	auto[0]	130	1			T15	3		T20	6		T22	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T15	1		T29	3		T31	2
all_values[4]	auto[0]	auto[1]	auto[0]	117	1			T15	2		T20	5		T22	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T22	2		T180	1		T181	1
all_values[4]	auto[1]	auto[0]	auto[1]	215	1			T15	1		T20	2		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T15	3		T20	2		T22	2
all_values[5]	auto[0]	auto[0]	auto[0]	236	1			T15	1		T20	5		T22	3
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T15	4		T20	4		T22	6
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T15	1		T20	3		T22	1
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T15	4		T20	3		T31	1
all_values[6]	auto[0]	auto[0]	auto[0]	164	1			T15	1		T29	1		T31	2
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T15	2		T20	1		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	118	1			T15	1		T20	1		T22	2
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T15	3		T20	6		T22	2
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T15	1		T20	5		T22	3
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T15	2		T20	2		T22	2
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T15	2		T20	4		T22	1
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T20	1		T22	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T15	2		T20	1		T29	2
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T15	2		T22	1		T29	2
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T15	3		T20	6		T22	6
all_values[7]	auto[1]	auto[1]	auto[1]	153	1			T15	1		T20	3		T22	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal