Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1645

1

T1

7

T3

1

T10

2

auto[1]

1595

1

T1

10

T3

1

T10

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1851

1

T1

17

T3

2

T10

3

auto[1]

1389

1

T15

3

T25

32

T27

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2550

1

T1

12

T3

2

T10

2

auto[1]

690

1

T1

5

T10

1

T13

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	652	1			T1	5		T13	1		T15	9
valid[1]	657	1			T1	4		T3	1		T10	1
valid[2]	614	1			T1	2		T10	1		T15	9
valid[3]	678	1			T1	2		T3	1		T10	1
valid[4]	639	1			T1	4		T13	2		T15	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	107	1			T1	1		T15	4		T17	2
auto[0]	auto[0]	valid[0]	auto[1]	142	1			T25	1		T34	2		T91	2
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T1	1		T3	1		T10	1
auto[0]	auto[0]	valid[1]	auto[1]	139	1			T15	1		T25	2		T27	1
auto[0]	auto[0]	valid[2]	auto[0]	100	1			T15	3		T27	2		T17	2
auto[0]	auto[0]	valid[2]	auto[1]	166	1			T15	1		T25	2		T34	2
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T1	1		T15	3		T42	1
auto[0]	auto[0]	valid[3]	auto[1]	133	1			T25	2		T34	1		T91	1
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T1	1		T13	1		T15	2
auto[0]	auto[0]	valid[4]	auto[1]	125	1			T15	1		T25	4		T34	3
auto[0]	auto[1]	valid[0]	auto[0]	122	1			T1	1		T13	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	140	1			T25	4		T34	1		T109	1
auto[0]	auto[1]	valid[1]	auto[0]	113	1			T1	3		T15	1		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T25	7		T34	2		T17	1
auto[0]	auto[1]	valid[2]	auto[0]	96	1			T15	3		T27	1		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	127	1			T25	4		T91	1		T93	1
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T1	1		T3	1		T10	1
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T25	4		T34	3		T17	2
auto[0]	auto[1]	valid[4]	auto[0]	120	1			T1	3		T15	5		T17	3
auto[0]	auto[1]	valid[4]	auto[1]	117	1			T25	2		T34	2		T91	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T1	2		T15	2		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T27	1		T51	1		T245	1
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T1	1		T10	1		T15	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T15	3		T17	2		T110	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T13	1		T52	1		T110	2
auto[1]	auto[1]	valid[0]	auto[0]	59	1			T1	1		T15	2		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T13	1		T15	1		T51	1
auto[1]	auto[1]	valid[2]	auto[0]	57	1			T1	1		T15	1		T27	1
auto[1]	auto[1]	valid[3]	auto[0]	60	1			T15	4		T42	1		T52	2
auto[1]	auto[1]	valid[4]	auto[0]	81	1			T15	1		T27	1		T17	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal