Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47491

1

T1

319

T3

73

T8

10

auto[1]

14659

1

T10

19

T13

10

T15

76

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44891

1

T1

220

T3

54

T8

5

auto[1]

17259

1

T1

99

T3

19

T8

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32093	1			T1	157		T3	31		T8	5
others[1]	5263	1			T1	31		T3	7		T8	2
others[2]	5224	1			T1	24		T3	7		T10	11
others[3]	5827	1			T1	31		T3	9		T10	3
interest[1]	3489	1			T1	20		T3	5		T8	1
interest[4]	21047	1			T1	106		T3	15		T8	3
interest[64]	10254	1			T1	56		T3	14		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15560	1			T1	111		T3	24		T8	3
auto[0]	auto[0]	others[1]	2613	1			T1	23		T3	6		T8	1
auto[0]	auto[0]	others[2]	2534	1			T1	14		T3	3		T10	6
auto[0]	auto[0]	others[3]	2846	1			T1	23		T3	7		T10	2
auto[0]	auto[0]	interest[1]	1704	1			T1	13		T3	4		T10	2
auto[0]	auto[0]	interest[4]	10134	1			T1	75		T3	12		T8	2
auto[0]	auto[0]	interest[64]	4975	1			T1	36		T3	10		T8	1
auto[0]	auto[1]	others[0]	7694	1			T10	10		T13	4		T15	43
auto[0]	auto[1]	others[1]	1173	1			T10	2		T15	3		T25	35
auto[0]	auto[1]	others[2]	1178	1			T10	3		T13	2		T15	8
auto[0]	auto[1]	others[3]	1379	1			T10	1		T13	3		T15	5
auto[0]	auto[1]	interest[1]	836	1			T10	1		T15	7		T25	21
auto[0]	auto[1]	interest[4]	5126	1			T10	7		T13	4		T15	26
auto[0]	auto[1]	interest[64]	2399	1			T10	2		T13	1		T15	10
auto[1]	auto[0]	others[0]	8839	1			T1	46		T3	7		T8	2
auto[1]	auto[0]	others[1]	1477	1			T1	8		T3	1		T8	1
auto[1]	auto[0]	others[2]	1512	1			T1	10		T3	4		T10	2
auto[1]	auto[0]	others[3]	1602	1			T1	8		T3	2		T13	4
auto[1]	auto[0]	interest[1]	949	1			T1	7		T3	1		T8	1
auto[1]	auto[0]	interest[4]	5787	1			T1	31		T3	3		T8	1
auto[1]	auto[0]	interest[64]	2880	1			T1	20		T3	4		T8	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal