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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1040 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3040744688 Jul 07 06:13:40 PM PDT 24 Jul 07 06:13:41 PM PDT 24 17344963 ps
T146 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3543286851 Jul 07 06:13:53 PM PDT 24 Jul 07 06:13:55 PM PDT 24 290437353 ps
T147 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.526742630 Jul 07 06:13:34 PM PDT 24 Jul 07 06:13:38 PM PDT 24 360413648 ps
T104 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3766468569 Jul 07 06:13:42 PM PDT 24 Jul 07 06:13:58 PM PDT 24 2592069795 ps
T119 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2187389021 Jul 07 06:13:30 PM PDT 24 Jul 07 06:13:32 PM PDT 24 48959374 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.120913704 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:35 PM PDT 24 52091573 ps
T148 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.859175547 Jul 07 06:13:23 PM PDT 24 Jul 07 06:13:26 PM PDT 24 45563840 ps
T1042 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1736384921 Jul 07 06:13:55 PM PDT 24 Jul 07 06:13:56 PM PDT 24 26984885 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3026055290 Jul 07 06:13:43 PM PDT 24 Jul 07 06:13:44 PM PDT 24 21566829 ps
T114 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4130895636 Jul 07 06:13:26 PM PDT 24 Jul 07 06:13:30 PM PDT 24 48907642 ps
T105 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3581904476 Jul 07 06:13:44 PM PDT 24 Jul 07 06:13:51 PM PDT 24 1405659481 ps
T186 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3017160458 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:48 PM PDT 24 1166989566 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2167527927 Jul 07 06:13:32 PM PDT 24 Jul 07 06:13:34 PM PDT 24 75419790 ps
T1045 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2251793729 Jul 07 06:13:50 PM PDT 24 Jul 07 06:13:51 PM PDT 24 57139449 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.687267142 Jul 07 06:13:27 PM PDT 24 Jul 07 06:13:29 PM PDT 24 83460436 ps
T88 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.60207043 Jul 07 06:13:29 PM PDT 24 Jul 07 06:13:30 PM PDT 24 77065547 ps
T124 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2119221604 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:48 PM PDT 24 416363362 ps
T115 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.527438120 Jul 07 06:13:41 PM PDT 24 Jul 07 06:13:44 PM PDT 24 78194665 ps
T158 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3034539591 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:34 PM PDT 24 190747328 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1188235824 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:49 PM PDT 24 474601087 ps
T125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1411292458 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:48 PM PDT 24 36484555 ps
T126 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2338226764 Jul 07 06:13:47 PM PDT 24 Jul 07 06:13:50 PM PDT 24 38427630 ps
T1046 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2825829879 Jul 07 06:13:55 PM PDT 24 Jul 07 06:13:56 PM PDT 24 35637836 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3819507144 Jul 07 06:13:23 PM PDT 24 Jul 07 06:13:47 PM PDT 24 1820747517 ps
T1048 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2549531860 Jul 07 06:13:55 PM PDT 24 Jul 07 06:13:56 PM PDT 24 19691577 ps
T116 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.402343864 Jul 07 06:13:34 PM PDT 24 Jul 07 06:13:38 PM PDT 24 158383030 ps
T129 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3244594344 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:45 PM PDT 24 1501713213 ps
T1049 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.511199382 Jul 07 06:13:53 PM PDT 24 Jul 07 06:13:55 PM PDT 24 17230919 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3708574961 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:43 PM PDT 24 298306665 ps
T127 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3967941932 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:41 PM PDT 24 107157084 ps
T128 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.89657154 Jul 07 06:13:30 PM PDT 24 Jul 07 06:13:32 PM PDT 24 74003073 ps
T1051 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2955909409 Jul 07 06:13:47 PM PDT 24 Jul 07 06:13:49 PM PDT 24 33195070 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3028518115 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:35 PM PDT 24 43929808 ps
T130 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1642656627 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:40 PM PDT 24 126251076 ps
T1053 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1656493796 Jul 07 06:13:55 PM PDT 24 Jul 07 06:13:57 PM PDT 24 40641210 ps
T192 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3153676240 Jul 07 06:13:51 PM PDT 24 Jul 07 06:14:13 PM PDT 24 5753444128 ps
T191 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.724862005 Jul 07 06:13:45 PM PDT 24 Jul 07 06:14:06 PM PDT 24 821910820 ps
T1054 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.574065230 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:53 PM PDT 24 116090749 ps
T1055 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3682971899 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:53 PM PDT 24 18612698 ps
T187 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2935608611 Jul 07 06:13:27 PM PDT 24 Jul 07 06:13:39 PM PDT 24 197262493 ps
T159 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4151915754 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:34 PM PDT 24 87749350 ps
T131 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3080236552 Jul 07 06:13:36 PM PDT 24 Jul 07 06:13:37 PM PDT 24 43001906 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2377279245 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:36 PM PDT 24 23189860 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2088141915 Jul 07 06:13:21 PM PDT 24 Jul 07 06:13:22 PM PDT 24 12096386 ps
T1058 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3063660908 Jul 07 06:13:50 PM PDT 24 Jul 07 06:13:51 PM PDT 24 45075078 ps
T190 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2256044076 Jul 07 06:13:27 PM PDT 24 Jul 07 06:13:35 PM PDT 24 109664407 ps
T160 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1916256671 Jul 07 06:13:27 PM PDT 24 Jul 07 06:13:53 PM PDT 24 1856048918 ps
T161 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4193867160 Jul 07 06:13:49 PM PDT 24 Jul 07 06:13:52 PM PDT 24 344395858 ps
T132 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2237707621 Jul 07 06:13:30 PM PDT 24 Jul 07 06:14:02 PM PDT 24 526948093 ps
T1059 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3504299038 Jul 07 06:13:54 PM PDT 24 Jul 07 06:13:56 PM PDT 24 43858487 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.746721664 Jul 07 06:13:29 PM PDT 24 Jul 07 06:13:30 PM PDT 24 40521766 ps
T1061 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.921394553 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:32 PM PDT 24 23742938 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3268068765 Jul 07 06:13:25 PM PDT 24 Jul 07 06:13:26 PM PDT 24 12424552 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3914948145 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:32 PM PDT 24 85502845 ps
T1064 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1713224984 Jul 07 06:13:34 PM PDT 24 Jul 07 06:13:35 PM PDT 24 22352218 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2301192287 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:41 PM PDT 24 105485932 ps
T1066 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3317243660 Jul 07 06:13:49 PM PDT 24 Jul 07 06:13:50 PM PDT 24 13079391 ps
T179 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3461367459 Jul 07 06:13:39 PM PDT 24 Jul 07 06:13:42 PM PDT 24 95277754 ps
T162 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.642199285 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:55 PM PDT 24 1049101919 ps
T1067 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1675552636 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:37 PM PDT 24 347692346 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2737231106 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:32 PM PDT 24 158145760 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2395529396 Jul 07 06:13:55 PM PDT 24 Jul 07 06:14:00 PM PDT 24 70211783 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3609338076 Jul 07 06:13:32 PM PDT 24 Jul 07 06:13:48 PM PDT 24 397594481 ps
T1071 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2579091959 Jul 07 06:13:51 PM PDT 24 Jul 07 06:13:53 PM PDT 24 66796389 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.166007397 Jul 07 06:13:29 PM PDT 24 Jul 07 06:13:44 PM PDT 24 5301927508 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2630253976 Jul 07 06:13:55 PM PDT 24 Jul 07 06:13:59 PM PDT 24 419710597 ps
T1074 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3849186214 Jul 07 06:13:49 PM PDT 24 Jul 07 06:13:50 PM PDT 24 36458218 ps
T1075 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3514438715 Jul 07 06:13:54 PM PDT 24 Jul 07 06:13:55 PM PDT 24 20890720 ps
T1076 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3487920103 Jul 07 06:13:48 PM PDT 24 Jul 07 06:13:49 PM PDT 24 103492417 ps
T188 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1454726359 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:50 PM PDT 24 296305214 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4044367899 Jul 07 06:13:42 PM PDT 24 Jul 07 06:13:46 PM PDT 24 44333272 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1608764186 Jul 07 06:13:21 PM PDT 24 Jul 07 06:13:43 PM PDT 24 1037620306 ps
T89 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2818580073 Jul 07 06:13:32 PM PDT 24 Jul 07 06:13:34 PM PDT 24 35168971 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.996933208 Jul 07 06:13:41 PM PDT 24 Jul 07 06:13:44 PM PDT 24 146154769 ps
T1080 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.688560131 Jul 07 06:13:43 PM PDT 24 Jul 07 06:13:48 PM PDT 24 274697208 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4032830990 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:59 PM PDT 24 655982576 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.270112526 Jul 07 06:13:29 PM PDT 24 Jul 07 06:13:31 PM PDT 24 61196960 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4127273381 Jul 07 06:13:40 PM PDT 24 Jul 07 06:13:45 PM PDT 24 1056608266 ps
T1083 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3688558641 Jul 07 06:13:40 PM PDT 24 Jul 07 06:13:47 PM PDT 24 347077841 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2482122294 Jul 07 06:13:36 PM PDT 24 Jul 07 06:13:40 PM PDT 24 345389370 ps
T1085 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2373927423 Jul 07 06:13:41 PM PDT 24 Jul 07 06:13:43 PM PDT 24 46814395 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1674604023 Jul 07 06:13:30 PM PDT 24 Jul 07 06:13:56 PM PDT 24 1255326547 ps
T1087 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1419070583 Jul 07 06:13:51 PM PDT 24 Jul 07 06:13:52 PM PDT 24 18308396 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1333362972 Jul 07 06:13:26 PM PDT 24 Jul 07 06:13:30 PM PDT 24 240044760 ps
T1089 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1848197109 Jul 07 06:13:53 PM PDT 24 Jul 07 06:13:54 PM PDT 24 37269433 ps
T1090 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.79890229 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:53 PM PDT 24 14710132 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3636554099 Jul 07 06:13:26 PM PDT 24 Jul 07 06:13:27 PM PDT 24 73437007 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2767685022 Jul 07 06:13:19 PM PDT 24 Jul 07 06:13:22 PM PDT 24 271419345 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1341937929 Jul 07 06:13:42 PM PDT 24 Jul 07 06:13:45 PM PDT 24 134036418 ps
T1094 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.376882523 Jul 07 06:13:44 PM PDT 24 Jul 07 06:13:47 PM PDT 24 37491704 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.988587601 Jul 07 06:13:20 PM PDT 24 Jul 07 06:13:55 PM PDT 24 4873086453 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3327567909 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:36 PM PDT 24 122968995 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2484719154 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:38 PM PDT 24 739258519 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1700782701 Jul 07 06:13:42 PM PDT 24 Jul 07 06:13:46 PM PDT 24 97331442 ps
T1099 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2892386792 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:40 PM PDT 24 142949695 ps
T1100 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2133850121 Jul 07 06:13:45 PM PDT 24 Jul 07 06:13:48 PM PDT 24 42642001 ps
T1101 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3034835068 Jul 07 06:13:41 PM PDT 24 Jul 07 06:13:46 PM PDT 24 230391796 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1748325475 Jul 07 06:13:23 PM PDT 24 Jul 07 06:13:27 PM PDT 24 229974009 ps
T1103 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1791962303 Jul 07 06:13:50 PM PDT 24 Jul 07 06:13:51 PM PDT 24 36049013 ps
T1104 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1796904296 Jul 07 06:13:51 PM PDT 24 Jul 07 06:13:54 PM PDT 24 210526500 ps
T1105 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.142505716 Jul 07 06:13:51 PM PDT 24 Jul 07 06:13:52 PM PDT 24 11958959 ps
T1106 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3331657143 Jul 07 06:13:42 PM PDT 24 Jul 07 06:13:46 PM PDT 24 148807402 ps
T1107 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.589597487 Jul 07 06:13:34 PM PDT 24 Jul 07 06:13:36 PM PDT 24 61714026 ps
T1108 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3233193035 Jul 07 06:13:37 PM PDT 24 Jul 07 06:13:40 PM PDT 24 195636740 ps
T1109 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1502417914 Jul 07 06:13:50 PM PDT 24 Jul 07 06:13:51 PM PDT 24 31160357 ps
T1110 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3792512284 Jul 07 06:13:43 PM PDT 24 Jul 07 06:13:48 PM PDT 24 125823641 ps
T1111 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2882027969 Jul 07 06:13:57 PM PDT 24 Jul 07 06:13:59 PM PDT 24 13201409 ps
T1112 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1502860281 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:40 PM PDT 24 59192779 ps
T1113 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2649861127 Jul 07 06:13:47 PM PDT 24 Jul 07 06:13:48 PM PDT 24 21393591 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2777411229 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:39 PM PDT 24 627668904 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1323483525 Jul 07 06:13:40 PM PDT 24 Jul 07 06:13:41 PM PDT 24 13807675 ps
T189 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2164518727 Jul 07 06:13:49 PM PDT 24 Jul 07 06:14:02 PM PDT 24 209225753 ps
T1116 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2616420945 Jul 07 06:13:21 PM PDT 24 Jul 07 06:13:26 PM PDT 24 173624440 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.776695341 Jul 07 06:13:34 PM PDT 24 Jul 07 06:13:35 PM PDT 24 74829950 ps
T1117 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.249270142 Jul 07 06:13:50 PM PDT 24 Jul 07 06:13:51 PM PDT 24 11712624 ps
T1118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2666348104 Jul 07 06:13:47 PM PDT 24 Jul 07 06:13:50 PM PDT 24 264734715 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3788359633 Jul 07 06:13:24 PM PDT 24 Jul 07 06:13:25 PM PDT 24 23520869 ps
T1120 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.541777420 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:39 PM PDT 24 63031155 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2216664417 Jul 07 06:13:31 PM PDT 24 Jul 07 06:13:33 PM PDT 24 132626345 ps
T1122 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2923465650 Jul 07 06:13:23 PM PDT 24 Jul 07 06:13:26 PM PDT 24 45843116 ps
T1123 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1587422964 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:37 PM PDT 24 88617929 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2143359787 Jul 07 06:13:21 PM PDT 24 Jul 07 06:13:24 PM PDT 24 228224304 ps
T1125 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1498455884 Jul 07 06:13:27 PM PDT 24 Jul 07 06:13:50 PM PDT 24 5249569895 ps
T1126 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3409362161 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:55 PM PDT 24 101629343 ps
T1127 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3389000196 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:53 PM PDT 24 55881780 ps
T1128 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3386113565 Jul 07 06:13:39 PM PDT 24 Jul 07 06:13:55 PM PDT 24 5187153103 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3869635303 Jul 07 06:13:47 PM PDT 24 Jul 07 06:13:48 PM PDT 24 43228983 ps
T1130 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.213192291 Jul 07 06:13:32 PM PDT 24 Jul 07 06:13:34 PM PDT 24 29158693 ps
T1131 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3582723315 Jul 07 06:13:25 PM PDT 24 Jul 07 06:13:26 PM PDT 24 43187343 ps
T193 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.935429290 Jul 07 06:13:37 PM PDT 24 Jul 07 06:13:54 PM PDT 24 813076674 ps
T1132 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3276240055 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:49 PM PDT 24 261805647 ps
T1133 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.607678745 Jul 07 06:13:28 PM PDT 24 Jul 07 06:13:31 PM PDT 24 37654651 ps
T1134 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1034542286 Jul 07 06:13:38 PM PDT 24 Jul 07 06:13:54 PM PDT 24 1464410869 ps
T1135 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.167625044 Jul 07 06:13:20 PM PDT 24 Jul 07 06:13:22 PM PDT 24 233215992 ps
T1136 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3849823160 Jul 07 06:13:22 PM PDT 24 Jul 07 06:13:31 PM PDT 24 2040122382 ps
T1137 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1385522663 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:47 PM PDT 24 13746130 ps
T1138 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2945505259 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:47 PM PDT 24 12552724 ps
T1139 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4121148306 Jul 07 06:13:56 PM PDT 24 Jul 07 06:13:57 PM PDT 24 42893314 ps
T1140 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.672240580 Jul 07 06:13:52 PM PDT 24 Jul 07 06:13:56 PM PDT 24 137571186 ps
T1141 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4091979374 Jul 07 06:13:36 PM PDT 24 Jul 07 06:13:39 PM PDT 24 168660165 ps
T1142 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4185835141 Jul 07 06:13:57 PM PDT 24 Jul 07 06:13:59 PM PDT 24 14913455 ps
T1143 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2556692713 Jul 07 06:13:39 PM PDT 24 Jul 07 06:13:42 PM PDT 24 449424433 ps
T1144 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4139090940 Jul 07 06:13:21 PM PDT 24 Jul 07 06:13:24 PM PDT 24 275217988 ps
T1145 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1284482404 Jul 07 06:13:33 PM PDT 24 Jul 07 06:13:39 PM PDT 24 1826005022 ps
T1146 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3163855344 Jul 07 06:13:35 PM PDT 24 Jul 07 06:13:41 PM PDT 24 429845836 ps
T1147 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.463101423 Jul 07 06:13:43 PM PDT 24 Jul 07 06:13:48 PM PDT 24 632868067 ps
T1148 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1554791612 Jul 07 06:13:46 PM PDT 24 Jul 07 06:13:47 PM PDT 24 42931229 ps
T194 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.792526298 Jul 07 06:13:22 PM PDT 24 Jul 07 06:13:42 PM PDT 24 588787926 ps
T1149 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2718269744 Jul 07 06:13:51 PM PDT 24 Jul 07 06:13:52 PM PDT 24 40388065 ps
T1150 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.206403214 Jul 07 06:13:32 PM PDT 24 Jul 07 06:13:35 PM PDT 24 201870103 ps
T1151 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1909788398 Jul 07 06:13:43 PM PDT 24 Jul 07 06:13:52 PM PDT 24 485043992 ps

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3249785492
Short name T5
Test name
Test status
Simulation time 885986750 ps
CPU time 23.03 seconds
Started Jul 07 06:32:27 PM PDT 24
Finished Jul 07 06:32:50 PM PDT 24
Peak memory 250172 kb
Host smart-3575add1-ec26-4b3e-833e-097c1e3848bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249785492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3249785492
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.84436515
Short name T15
Test name
Test status
Simulation time 59164327502 ps
CPU time 154.53 seconds
Started Jul 07 06:29:22 PM PDT 24
Finished Jul 07 06:31:57 PM PDT 24
Peak memory 258552 kb
Host smart-911be138-9717-4a88-b93f-1bccc2217c5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84436515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_
all.84436515
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3615131685
Short name T17
Test name
Test status
Simulation time 121243315861 ps
CPU time 279.45 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:37:06 PM PDT 24
Peak memory 288252 kb
Host smart-89a2f027-36ee-47f5-abbb-4fed6917a227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615131685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3615131685
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3766468569
Short name T104
Test name
Test status
Simulation time 2592069795 ps
CPU time 15.2 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:58 PM PDT 24
Peak memory 223780 kb
Host smart-a0c59079-47b8-41cf-82fb-1101b6eab56f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766468569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3766468569
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.490718828
Short name T68
Test name
Test status
Simulation time 15840054 ps
CPU time 0.75 seconds
Started Jul 07 06:28:26 PM PDT 24
Finished Jul 07 06:28:27 PM PDT 24
Peak memory 217056 kb
Host smart-46b755ae-b9a3-4e84-8f84-27ececc96b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490718828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.490718828
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.756028761
Short name T42
Test name
Test status
Simulation time 325737612456 ps
CPU time 668.53 seconds
Started Jul 07 06:33:36 PM PDT 24
Finished Jul 07 06:44:45 PM PDT 24
Peak memory 254152 kb
Host smart-03ef85fd-e4e3-40cf-a532-f6eb1c0edfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756028761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.756028761
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1404301236
Short name T207
Test name
Test status
Simulation time 87509384595 ps
CPU time 852.19 seconds
Started Jul 07 06:30:32 PM PDT 24
Finished Jul 07 06:44:44 PM PDT 24
Peak memory 286280 kb
Host smart-da92e7dd-41ef-4c1e-82ae-158fe7c8923a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404301236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1404301236
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.542489720
Short name T111
Test name
Test status
Simulation time 280839283022 ps
CPU time 277.46 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:38:18 PM PDT 24
Peak memory 258536 kb
Host smart-a0c1f699-42f6-4865-baeb-0398c705a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542489720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.542489720
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3806515821
Short name T214
Test name
Test status
Simulation time 21946842896 ps
CPU time 131.78 seconds
Started Jul 07 06:33:14 PM PDT 24
Finished Jul 07 06:35:26 PM PDT 24
Peak memory 250440 kb
Host smart-718bd334-efa1-4b8a-a9cc-3616034adc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806515821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3806515821
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3404926417
Short name T112
Test name
Test status
Simulation time 227225105 ps
CPU time 2.92 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 215740 kb
Host smart-9ebc8eb1-dc7b-4d7f-acab-31c99ff5e289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404926417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
404926417
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3191406902
Short name T227
Test name
Test status
Simulation time 23817354087 ps
CPU time 162.32 seconds
Started Jul 07 06:28:56 PM PDT 24
Finished Jul 07 06:31:38 PM PDT 24
Peak memory 267492 kb
Host smart-8978f255-bdd3-4c21-92a4-c829b82d47f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191406902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3191406902
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3403492300
Short name T21
Test name
Test status
Simulation time 88312522 ps
CPU time 1.19 seconds
Started Jul 07 06:29:19 PM PDT 24
Finished Jul 07 06:29:20 PM PDT 24
Peak memory 236348 kb
Host smart-6f417a22-8c3e-4f39-bc6a-485c1659cbe4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403492300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3403492300
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2450774410
Short name T215
Test name
Test status
Simulation time 23230317891 ps
CPU time 98.59 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:35:51 PM PDT 24
Peak memory 266344 kb
Host smart-514744ca-5f1c-48c4-8469-e5cba4d754fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450774410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2450774410
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2938397075
Short name T150
Test name
Test status
Simulation time 1399064219 ps
CPU time 21.4 seconds
Started Jul 07 06:30:57 PM PDT 24
Finished Jul 07 06:31:19 PM PDT 24
Peak memory 241996 kb
Host smart-6a06613b-2dfc-4015-b324-2fc1206346be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938397075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2938397075
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1058784915
Short name T53
Test name
Test status
Simulation time 33954800682 ps
CPU time 329.77 seconds
Started Jul 07 06:29:31 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 266740 kb
Host smart-59e584f4-bead-4d6e-88ed-eb3541169658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058784915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1058784915
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.222591691
Short name T199
Test name
Test status
Simulation time 45582378760 ps
CPU time 112.78 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:33:04 PM PDT 24
Peak memory 267912 kb
Host smart-f1a722be-6256-44e3-a321-d628c448e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222591691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.222591691
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3339809402
Short name T121
Test name
Test status
Simulation time 91880294 ps
CPU time 2.32 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:38 PM PDT 24
Peak memory 215560 kb
Host smart-19fd921d-5e39-4463-a77a-62697f15ff63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339809402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
339809402
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1006760526
Short name T213
Test name
Test status
Simulation time 4025032226 ps
CPU time 105.09 seconds
Started Jul 07 06:30:41 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 257984 kb
Host smart-ba2cfe9c-9bcf-4713-9a3a-bc3cd09319d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006760526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1006760526
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1025844997
Short name T205
Test name
Test status
Simulation time 72601371090 ps
CPU time 211.28 seconds
Started Jul 07 06:29:46 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 256364 kb
Host smart-ac0bdcc4-a1cf-48f5-8aff-ec2d0abdabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025844997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1025844997
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3692663002
Short name T423
Test name
Test status
Simulation time 249494660 ps
CPU time 1.05 seconds
Started Jul 07 06:30:23 PM PDT 24
Finished Jul 07 06:30:24 PM PDT 24
Peak memory 217644 kb
Host smart-c543a9a5-dc6c-4dc0-83ee-8b9ee6459332
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692663002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3692663002
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.503048794
Short name T45
Test name
Test status
Simulation time 15084801576 ps
CPU time 85.85 seconds
Started Jul 07 06:29:37 PM PDT 24
Finished Jul 07 06:31:03 PM PDT 24
Peak memory 250312 kb
Host smart-67e331b9-c54e-4966-a7a0-869168e8cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503048794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.503048794
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2356898913
Short name T55
Test name
Test status
Simulation time 12604771099 ps
CPU time 185.29 seconds
Started Jul 07 06:33:35 PM PDT 24
Finished Jul 07 06:36:41 PM PDT 24
Peak memory 266784 kb
Host smart-deb7b896-7d00-41ac-870c-7d24b87e7f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356898913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2356898913
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.904832040
Short name T226
Test name
Test status
Simulation time 18563214603 ps
CPU time 153.79 seconds
Started Jul 07 06:29:08 PM PDT 24
Finished Jul 07 06:31:42 PM PDT 24
Peak memory 255656 kb
Host smart-9fc42370-3e6c-4444-aa40-06575b5c4fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904832040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
904832040
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1159103337
Short name T6
Test name
Test status
Simulation time 37766728 ps
CPU time 0.74 seconds
Started Jul 07 06:31:52 PM PDT 24
Finished Jul 07 06:31:53 PM PDT 24
Peak memory 206372 kb
Host smart-b9f28fec-3f73-4f1f-a9d7-456d560e4321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159103337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1159103337
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3943153860
Short name T209
Test name
Test status
Simulation time 56800362986 ps
CPU time 384.7 seconds
Started Jul 07 06:33:45 PM PDT 24
Finished Jul 07 06:40:11 PM PDT 24
Peak memory 256876 kb
Host smart-d80538bb-36ec-4234-9c04-d52f59a36f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943153860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3943153860
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3910858755
Short name T82
Test name
Test status
Simulation time 53910828038 ps
CPU time 243.85 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:36:59 PM PDT 24
Peak memory 266828 kb
Host smart-f482dc22-ed70-4462-82d0-15ef45bfb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910858755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3910858755
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1976040108
Short name T49
Test name
Test status
Simulation time 123437558238 ps
CPU time 559.99 seconds
Started Jul 07 06:31:27 PM PDT 24
Finished Jul 07 06:40:48 PM PDT 24
Peak memory 266784 kb
Host smart-98b8cbbb-35e9-43d5-8424-9b4605e0779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976040108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1976040108
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.56449727
Short name T164
Test name
Test status
Simulation time 5396066718 ps
CPU time 30.15 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:35:13 PM PDT 24
Peak memory 239616 kb
Host smart-bc7e90f4-7e5a-43c1-ba32-6ec130a76d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56449727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.56449727
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3300464381
Short name T269
Test name
Test status
Simulation time 165000981535 ps
CPU time 368.26 seconds
Started Jul 07 06:29:51 PM PDT 24
Finished Jul 07 06:36:00 PM PDT 24
Peak memory 258220 kb
Host smart-6573de3c-b2bc-46c9-8056-b96172a98f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300464381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3300464381
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2802996763
Short name T96
Test name
Test status
Simulation time 20751821016 ps
CPU time 127.44 seconds
Started Jul 07 06:29:51 PM PDT 24
Finished Jul 07 06:31:59 PM PDT 24
Peak memory 254236 kb
Host smart-aa4563e0-c249-4761-a778-5c8da92cbb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802996763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2802996763
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2357825448
Short name T1
Test name
Test status
Simulation time 2661172594 ps
CPU time 21.33 seconds
Started Jul 07 06:31:23 PM PDT 24
Finished Jul 07 06:31:45 PM PDT 24
Peak memory 217660 kb
Host smart-6d308e3c-af2e-45a2-86f6-56f023fa8d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357825448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2357825448
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.792679011
Short name T285
Test name
Test status
Simulation time 1851318654 ps
CPU time 43.83 seconds
Started Jul 07 06:30:41 PM PDT 24
Finished Jul 07 06:31:25 PM PDT 24
Peak memory 241556 kb
Host smart-36b8e856-e24c-4cfa-bc8e-1d411d1846da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792679011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.792679011
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2162510865
Short name T31
Test name
Test status
Simulation time 20857641708 ps
CPU time 158.54 seconds
Started Jul 07 06:33:28 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 252672 kb
Host smart-b3ce3aad-efea-403a-8426-6eba85cac2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162510865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2162510865
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2528277486
Short name T103
Test name
Test status
Simulation time 833505802 ps
CPU time 4.63 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:14:01 PM PDT 24
Peak memory 215748 kb
Host smart-1b6b1a5f-27f0-471a-8899-b9d2149d5045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528277486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2528277486
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.935429290
Short name T193
Test name
Test status
Simulation time 813076674 ps
CPU time 17.52 seconds
Started Jul 07 06:13:37 PM PDT 24
Finished Jul 07 06:13:54 PM PDT 24
Peak memory 216168 kb
Host smart-418cba19-8cb3-4389-901a-5bc3f22490be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935429290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.935429290
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2154875569
Short name T864
Test name
Test status
Simulation time 922625050 ps
CPU time 9.84 seconds
Started Jul 07 06:30:26 PM PDT 24
Finished Jul 07 06:30:36 PM PDT 24
Peak memory 249992 kb
Host smart-035452e7-69bf-488b-8e73-986ee3f7a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154875569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2154875569
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3013918386
Short name T200
Test name
Test status
Simulation time 31861158385 ps
CPU time 274.57 seconds
Started Jul 07 06:30:50 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 254360 kb
Host smart-1ae957fb-2424-498b-be19-8c0db5a4b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013918386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3013918386
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.838432085
Short name T828
Test name
Test status
Simulation time 12417078596 ps
CPU time 25.38 seconds
Started Jul 07 06:31:16 PM PDT 24
Finished Jul 07 06:31:41 PM PDT 24
Peak memory 225652 kb
Host smart-8d51bca2-7d4e-454c-a4ba-9423cb01a160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838432085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.838432085
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1770064787
Short name T34
Test name
Test status
Simulation time 461019019 ps
CPU time 3.84 seconds
Started Jul 07 06:32:42 PM PDT 24
Finished Jul 07 06:32:46 PM PDT 24
Peak memory 217380 kb
Host smart-fdd5de47-6a3f-4feb-954a-1fb761c7eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770064787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1770064787
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3620006537
Short name T272
Test name
Test status
Simulation time 67271171545 ps
CPU time 300.93 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:38:42 PM PDT 24
Peak memory 264448 kb
Host smart-02e45c3d-4053-4634-8ef0-8b088a82841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620006537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3620006537
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3782522049
Short name T678
Test name
Test status
Simulation time 12017057475 ps
CPU time 167.64 seconds
Started Jul 07 06:33:15 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 266600 kb
Host smart-a9fd9c11-2cad-4a81-870c-f3bf87deea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782522049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3782522049
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.962264139
Short name T35
Test name
Test status
Simulation time 292750219 ps
CPU time 2.14 seconds
Started Jul 07 06:31:54 PM PDT 24
Finished Jul 07 06:31:56 PM PDT 24
Peak memory 225508 kb
Host smart-e339b4e9-d60a-4319-8cf2-500452c7112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962264139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.962264139
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2256044076
Short name T190
Test name
Test status
Simulation time 109664407 ps
CPU time 7.02 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 215552 kb
Host smart-07e5d8e4-1b62-4c30-a7af-87e97d79bf08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256044076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2256044076
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2277227846
Short name T352
Test name
Test status
Simulation time 4083792971 ps
CPU time 20.39 seconds
Started Jul 07 06:28:29 PM PDT 24
Finished Jul 07 06:28:50 PM PDT 24
Peak memory 217396 kb
Host smart-1ad6e9e0-e863-4a83-8d60-1352833178af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277227846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2277227846
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2508510524
Short name T250
Test name
Test status
Simulation time 248559890576 ps
CPU time 400.22 seconds
Started Jul 07 06:30:56 PM PDT 24
Finished Jul 07 06:37:36 PM PDT 24
Peak memory 266396 kb
Host smart-41d0ff85-f712-458d-b723-86c6a412e611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508510524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2508510524
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3800708165
Short name T980
Test name
Test status
Simulation time 155146415894 ps
CPU time 311.1 seconds
Started Jul 07 06:31:25 PM PDT 24
Finished Jul 07 06:36:37 PM PDT 24
Peak memory 257704 kb
Host smart-6278dfe5-85f5-453a-a633-b448356ea455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800708165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3800708165
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.158139205
Short name T154
Test name
Test status
Simulation time 271574202 ps
CPU time 4.72 seconds
Started Jul 07 06:31:36 PM PDT 24
Finished Jul 07 06:31:41 PM PDT 24
Peak memory 225616 kb
Host smart-bc4b8b53-f429-4f8d-8c66-d2b28dfb58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158139205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.158139205
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4222951463
Short name T321
Test name
Test status
Simulation time 22371518042 ps
CPU time 94.41 seconds
Started Jul 07 06:33:54 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 258372 kb
Host smart-5f3a8b8c-a257-407d-8bb7-8de6836b1877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222951463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4222951463
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.94684329
Short name T26
Test name
Test status
Simulation time 795537144 ps
CPU time 3.94 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:30:25 PM PDT 24
Peak memory 233788 kb
Host smart-c08a3af5-ba89-457b-afb9-a49e8f6d64b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94684329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.94684329
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.60207043
Short name T88
Test name
Test status
Simulation time 77065547 ps
CPU time 1.04 seconds
Started Jul 07 06:13:29 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 207056 kb
Host smart-478594dc-8e62-4201-b264-018110a26d41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60207043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
hw_reset.60207043
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2961405418
Short name T36
Test name
Test status
Simulation time 4324744029 ps
CPU time 56.47 seconds
Started Jul 07 06:31:19 PM PDT 24
Finished Jul 07 06:32:16 PM PDT 24
Peak memory 236340 kb
Host smart-4598d7cd-79ef-4c7f-b76c-7d68f20444b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961405418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2961405418
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1608764186
Short name T1078
Test name
Test status
Simulation time 1037620306 ps
CPU time 21.73 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:43 PM PDT 24
Peak memory 215536 kb
Host smart-6ec96bdb-5c15-4068-973d-9eeac0ad44a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608764186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1608764186
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.988587601
Short name T1095
Test name
Test status
Simulation time 4873086453 ps
CPU time 34.7 seconds
Started Jul 07 06:13:20 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 207332 kb
Host smart-250fc12d-08fb-45af-89fe-deec5a709e11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988587601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.988587601
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3028355497
Short name T86
Test name
Test status
Simulation time 28408749 ps
CPU time 0.94 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:22 PM PDT 24
Peak memory 207000 kb
Host smart-ca7a59ee-5725-4b24-935c-2e37990a46dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028355497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3028355497
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2923465650
Short name T1122
Test name
Test status
Simulation time 45843116 ps
CPU time 1.75 seconds
Started Jul 07 06:13:23 PM PDT 24
Finished Jul 07 06:13:26 PM PDT 24
Peak memory 216652 kb
Host smart-f5b2b795-6532-4d2b-9ec2-5c90305694a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923465650 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2923465650
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2143359787
Short name T1124
Test name
Test status
Simulation time 228224304 ps
CPU time 1.97 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:24 PM PDT 24
Peak memory 215460 kb
Host smart-c88d54b9-dc38-400c-95e5-44d976ca5905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143359787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
143359787
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2088141915
Short name T1057
Test name
Test status
Simulation time 12096386 ps
CPU time 0.76 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:22 PM PDT 24
Peak memory 204028 kb
Host smart-e0c79b65-6c16-4c2b-ab68-7f46cc1e1183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088141915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
088141915
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.167625044
Short name T1135
Test name
Test status
Simulation time 233215992 ps
CPU time 2.4 seconds
Started Jul 07 06:13:20 PM PDT 24
Finished Jul 07 06:13:22 PM PDT 24
Peak memory 215576 kb
Host smart-9884f3f3-26f5-46cf-b8a6-3139838ed06d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167625044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.167625044
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.539523828
Short name T1034
Test name
Test status
Simulation time 12927408 ps
CPU time 0.65 seconds
Started Jul 07 06:13:23 PM PDT 24
Finished Jul 07 06:13:24 PM PDT 24
Peak memory 203912 kb
Host smart-5c1dd836-3edc-4442-9576-6ea7d12ec4a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539523828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.539523828
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2767685022
Short name T1092
Test name
Test status
Simulation time 271419345 ps
CPU time 3.08 seconds
Started Jul 07 06:13:19 PM PDT 24
Finished Jul 07 06:13:22 PM PDT 24
Peak memory 215516 kb
Host smart-01682f8b-de03-4f43-82e7-607916e1b5d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767685022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2767685022
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2616420945
Short name T1116
Test name
Test status
Simulation time 173624440 ps
CPU time 4.47 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:26 PM PDT 24
Peak memory 216764 kb
Host smart-75e54092-9355-4cd4-83d7-c5370bdf8785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616420945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
616420945
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3849823160
Short name T1136
Test name
Test status
Simulation time 2040122382 ps
CPU time 8.23 seconds
Started Jul 07 06:13:22 PM PDT 24
Finished Jul 07 06:13:31 PM PDT 24
Peak memory 215576 kb
Host smart-c70c0405-9f7d-433d-a8bc-a1697fc94d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849823160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3849823160
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3819507144
Short name T1047
Test name
Test status
Simulation time 1820747517 ps
CPU time 23.66 seconds
Started Jul 07 06:13:23 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 215472 kb
Host smart-510ab00d-fdf8-4105-b903-f14eeffc7d5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819507144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3819507144
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1916256671
Short name T160
Test name
Test status
Simulation time 1856048918 ps
CPU time 26.47 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 207296 kb
Host smart-39e43da2-6aa0-45a7-8289-3e144b1be9c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916256671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1916256671
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4173008943
Short name T87
Test name
Test status
Simulation time 70902348 ps
CPU time 1.35 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:29 PM PDT 24
Peak memory 207348 kb
Host smart-9a44c4bf-901d-4127-aa20-98a6c9cccfa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173008943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4173008943
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2516348160
Short name T100
Test name
Test status
Simulation time 57002755 ps
CPU time 3.59 seconds
Started Jul 07 06:13:24 PM PDT 24
Finished Jul 07 06:13:28 PM PDT 24
Peak memory 217308 kb
Host smart-25b9a272-671b-4190-8477-dbdd901acabc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516348160 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2516348160
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3636554099
Short name T1091
Test name
Test status
Simulation time 73437007 ps
CPU time 1.25 seconds
Started Jul 07 06:13:26 PM PDT 24
Finished Jul 07 06:13:27 PM PDT 24
Peak memory 207284 kb
Host smart-38c31910-32ec-440a-b149-bbc55e407472
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636554099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
636554099
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3582723315
Short name T1131
Test name
Test status
Simulation time 43187343 ps
CPU time 0.75 seconds
Started Jul 07 06:13:25 PM PDT 24
Finished Jul 07 06:13:26 PM PDT 24
Peak memory 204268 kb
Host smart-73ad1213-e212-4465-a328-27863201b7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582723315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
582723315
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4139090940
Short name T1144
Test name
Test status
Simulation time 275217988 ps
CPU time 2.14 seconds
Started Jul 07 06:13:21 PM PDT 24
Finished Jul 07 06:13:24 PM PDT 24
Peak memory 215540 kb
Host smart-a70b396d-464f-4fd6-af5a-6c77279f652d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139090940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4139090940
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3268068765
Short name T1062
Test name
Test status
Simulation time 12424552 ps
CPU time 0.69 seconds
Started Jul 07 06:13:25 PM PDT 24
Finished Jul 07 06:13:26 PM PDT 24
Peak memory 203928 kb
Host smart-acce2764-4df4-4f03-a164-a6a1c2d1db6f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268068765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3268068765
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.859175547
Short name T148
Test name
Test status
Simulation time 45563840 ps
CPU time 2.78 seconds
Started Jul 07 06:13:23 PM PDT 24
Finished Jul 07 06:13:26 PM PDT 24
Peak memory 215540 kb
Host smart-20508992-5e8d-49fd-9c55-b94c222f090d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859175547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.859175547
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4130895636
Short name T114
Test name
Test status
Simulation time 48907642 ps
CPU time 3.33 seconds
Started Jul 07 06:13:26 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 217044 kb
Host smart-8f93c158-835b-4f6a-8cef-41b2e36790ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130895636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
130895636
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1341937929
Short name T1093
Test name
Test status
Simulation time 134036418 ps
CPU time 2.73 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:45 PM PDT 24
Peak memory 218376 kb
Host smart-a9d1b89e-da4f-46a2-b639-86cc1b18c646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341937929 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1341937929
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.996933208
Short name T1079
Test name
Test status
Simulation time 146154769 ps
CPU time 2.54 seconds
Started Jul 07 06:13:41 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 215516 kb
Host smart-eed9b762-3620-4edf-be32-8edd580c4f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996933208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.996933208
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3040744688
Short name T1040
Test name
Test status
Simulation time 17344963 ps
CPU time 0.77 seconds
Started Jul 07 06:13:40 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 203980 kb
Host smart-3a60367e-b2d7-422f-9892-9745275b7f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040744688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3040744688
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2556692713
Short name T1143
Test name
Test status
Simulation time 449424433 ps
CPU time 3.06 seconds
Started Jul 07 06:13:39 PM PDT 24
Finished Jul 07 06:13:42 PM PDT 24
Peak memory 215500 kb
Host smart-4ba38209-b73c-4672-bb90-83a38c9c0932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556692713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2556692713
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1502860281
Short name T1112
Test name
Test status
Simulation time 59192779 ps
CPU time 2.26 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:40 PM PDT 24
Peak memory 215788 kb
Host smart-9acf5566-2c0e-4b65-83e7-50ddcb5e848d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502860281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1502860281
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3688558641
Short name T1083
Test name
Test status
Simulation time 347077841 ps
CPU time 7.32 seconds
Started Jul 07 06:13:40 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 215472 kb
Host smart-42cd66e0-6102-447b-ac3a-7ec58cf67660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688558641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3688558641
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.527438120
Short name T115
Test name
Test status
Simulation time 78194665 ps
CPU time 2.65 seconds
Started Jul 07 06:13:41 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 216620 kb
Host smart-d9f08a54-630d-4c0e-be7e-a5021a48800b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527438120 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.527438120
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1554791612
Short name T1148
Test name
Test status
Simulation time 42931229 ps
CPU time 1.34 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 207292 kb
Host smart-0ad5c6e0-8ffa-4d13-8d86-aff8aa4c84c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554791612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1554791612
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.541777420
Short name T1120
Test name
Test status
Simulation time 63031155 ps
CPU time 0.71 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:39 PM PDT 24
Peak memory 204056 kb
Host smart-a9a92985-c426-4d30-a4ec-583c0961264f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541777420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.541777420
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.463101423
Short name T1147
Test name
Test status
Simulation time 632868067 ps
CPU time 4.62 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 215452 kb
Host smart-135a72a6-2394-4cfa-b949-56dae71af972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463101423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.463101423
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2301192287
Short name T1065
Test name
Test status
Simulation time 105485932 ps
CPU time 2.03 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 215696 kb
Host smart-8e072eb3-c9c6-4859-9152-7e148f4c2c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301192287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2301192287
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4044367899
Short name T1077
Test name
Test status
Simulation time 44333272 ps
CPU time 2.88 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 217552 kb
Host smart-38d32255-7f23-4fc6-a1e0-cd50ff8f62a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044367899 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4044367899
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3967941932
Short name T127
Test name
Test status
Simulation time 107157084 ps
CPU time 2.6 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 215428 kb
Host smart-47a885fc-0068-436e-a47f-03c53484664d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967941932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3967941932
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3869635303
Short name T1129
Test name
Test status
Simulation time 43228983 ps
CPU time 0.78 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 203952 kb
Host smart-1d8575a9-dc83-49b5-9310-70939ba70d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869635303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3869635303
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3034835068
Short name T1101
Test name
Test status
Simulation time 230391796 ps
CPU time 3.99 seconds
Started Jul 07 06:13:41 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 215536 kb
Host smart-079ef635-e58e-47ca-87eb-6d50044de72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034835068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3034835068
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3461367459
Short name T179
Test name
Test status
Simulation time 95277754 ps
CPU time 2.69 seconds
Started Jul 07 06:13:39 PM PDT 24
Finished Jul 07 06:13:42 PM PDT 24
Peak memory 215752 kb
Host smart-428f1665-00c4-4885-ac0c-95342d88801e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461367459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3461367459
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3386113565
Short name T1128
Test name
Test status
Simulation time 5187153103 ps
CPU time 15.62 seconds
Started Jul 07 06:13:39 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 216436 kb
Host smart-63364036-a80e-40fa-9be5-d4e50a7b6e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386113565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3386113565
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2373927423
Short name T1085
Test name
Test status
Simulation time 46814395 ps
CPU time 1.66 seconds
Started Jul 07 06:13:41 PM PDT 24
Finished Jul 07 06:13:43 PM PDT 24
Peak memory 215584 kb
Host smart-146646d9-5fcb-40e7-80ba-e928e8866682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373927423 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2373927423
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2860458524
Short name T145
Test name
Test status
Simulation time 134017893 ps
CPU time 1.4 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 207268 kb
Host smart-2bdc6bf0-f0a3-4842-956f-18c9140b4de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860458524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2860458524
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3657812687
Short name T1035
Test name
Test status
Simulation time 17990643 ps
CPU time 0.74 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 203952 kb
Host smart-38c653de-93a4-4b40-be24-f03adf42337e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657812687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3657812687
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3331657143
Short name T1106
Test name
Test status
Simulation time 148807402 ps
CPU time 4.21 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 215500 kb
Host smart-bc465ab3-6ffb-4585-8284-4b841dbc4ae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331657143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3331657143
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4127273381
Short name T1082
Test name
Test status
Simulation time 1056608266 ps
CPU time 5.41 seconds
Started Jul 07 06:13:40 PM PDT 24
Finished Jul 07 06:13:45 PM PDT 24
Peak memory 215812 kb
Host smart-6d041c09-17ca-4e30-861c-0340ae26be3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127273381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4127273381
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3581904476
Short name T105
Test name
Test status
Simulation time 1405659481 ps
CPU time 6.5 seconds
Started Jul 07 06:13:44 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 215932 kb
Host smart-bb8b4179-6033-4f00-87ea-d61467f95772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581904476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3581904476
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3792512284
Short name T1110
Test name
Test status
Simulation time 125823641 ps
CPU time 3.53 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 216216 kb
Host smart-26272638-897c-4471-ae03-97640fc43a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792512284 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3792512284
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2666348104
Short name T1118
Test name
Test status
Simulation time 264734715 ps
CPU time 1.84 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 207320 kb
Host smart-c269035a-a80c-49eb-9c1b-08f8d0aa3559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666348104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2666348104
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1281056367
Short name T1039
Test name
Test status
Simulation time 11084106 ps
CPU time 0.7 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 203972 kb
Host smart-5261efcd-4858-4113-aa37-f83017ca8ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281056367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1281056367
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2534150441
Short name T143
Test name
Test status
Simulation time 116219945 ps
CPU time 1.87 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:49 PM PDT 24
Peak memory 207312 kb
Host smart-4d1e1e7f-378d-4798-822c-bf01ec954bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534150441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2534150441
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.376882523
Short name T1094
Test name
Test status
Simulation time 37491704 ps
CPU time 2.5 seconds
Started Jul 07 06:13:44 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 215748 kb
Host smart-1f95d6a2-3829-43cd-a7e3-bcab694f36e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376882523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.376882523
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1700782701
Short name T1098
Test name
Test status
Simulation time 97331442 ps
CPU time 3.65 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 217492 kb
Host smart-8542273e-269b-4425-857b-06749332d2c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700782701 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1700782701
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3646193489
Short name T122
Test name
Test status
Simulation time 44077464 ps
CPU time 1.44 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:45 PM PDT 24
Peak memory 207264 kb
Host smart-95a3b345-e1e4-4fb8-9292-255541ff87db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646193489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3646193489
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3026055290
Short name T1043
Test name
Test status
Simulation time 21566829 ps
CPU time 0.73 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 204324 kb
Host smart-5583c91b-6bb0-49b5-b134-c5b7eca6054c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026055290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3026055290
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2133850121
Short name T1100
Test name
Test status
Simulation time 42642001 ps
CPU time 2.63 seconds
Started Jul 07 06:13:45 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 215536 kb
Host smart-57758329-2b99-4dcf-a934-f4efcdc5527c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133850121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2133850121
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1979206659
Short name T102
Test name
Test status
Simulation time 162967348 ps
CPU time 4.13 seconds
Started Jul 07 06:13:42 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 215844 kb
Host smart-ee88f513-f24d-49b9-860e-4364c3b38cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979206659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1979206659
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.724862005
Short name T191
Test name
Test status
Simulation time 821910820 ps
CPU time 20.32 seconds
Started Jul 07 06:13:45 PM PDT 24
Finished Jul 07 06:14:06 PM PDT 24
Peak memory 215772 kb
Host smart-370df881-313f-42f9-b281-8c0461053e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724862005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.724862005
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2579091959
Short name T1071
Test name
Test status
Simulation time 66796389 ps
CPU time 1.9 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 215676 kb
Host smart-d1170e56-cae3-47f2-9920-d799696ba2fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579091959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2579091959
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2119221604
Short name T124
Test name
Test status
Simulation time 416363362 ps
CPU time 2.03 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 215524 kb
Host smart-92a21902-e2d6-49de-a851-5a11d79a30f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119221604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2119221604
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1385522663
Short name T1137
Test name
Test status
Simulation time 13746130 ps
CPU time 0.73 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 204324 kb
Host smart-35095546-cc8f-4509-a9c3-fe30e0a12663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385522663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1385522663
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2630253976
Short name T1073
Test name
Test status
Simulation time 419710597 ps
CPU time 2.94 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:13:59 PM PDT 24
Peak memory 215472 kb
Host smart-43bd065e-40ec-4101-acbc-4e5c83c96c15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630253976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2630253976
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3276240055
Short name T1132
Test name
Test status
Simulation time 261805647 ps
CPU time 2.33 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:49 PM PDT 24
Peak memory 215784 kb
Host smart-39d3c7c0-f608-4138-853b-af42b81f53fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276240055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3276240055
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1909788398
Short name T1151
Test name
Test status
Simulation time 485043992 ps
CPU time 8.41 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:52 PM PDT 24
Peak memory 214076 kb
Host smart-7ba626b4-326e-4174-a91b-9a3441c7434f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909788398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1909788398
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3814803889
Short name T106
Test name
Test status
Simulation time 103837047 ps
CPU time 3.55 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 218176 kb
Host smart-191a3b11-e0c1-4e77-ba42-7422f7bcba20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814803889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3814803889
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1411292458
Short name T125
Test name
Test status
Simulation time 36484555 ps
CPU time 1.41 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 215572 kb
Host smart-88ceb20d-0575-49cf-96b9-821869f137f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411292458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1411292458
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1797401847
Short name T1038
Test name
Test status
Simulation time 39138292 ps
CPU time 0.7 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 203976 kb
Host smart-6e9ccd6d-04e5-4d35-a44a-21efcb367ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797401847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1797401847
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.672240580
Short name T1140
Test name
Test status
Simulation time 137571186 ps
CPU time 3.78 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 215564 kb
Host smart-32c5a2bb-4749-4bb0-b412-0e4fb54ad608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672240580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.672240580
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3153676240
Short name T192
Test name
Test status
Simulation time 5753444128 ps
CPU time 21.5 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:14:13 PM PDT 24
Peak memory 215544 kb
Host smart-be262990-56ab-4672-bcf3-8db26f399d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153676240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3153676240
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4193867160
Short name T161
Test name
Test status
Simulation time 344395858 ps
CPU time 3.58 seconds
Started Jul 07 06:13:49 PM PDT 24
Finished Jul 07 06:13:52 PM PDT 24
Peak memory 217420 kb
Host smart-1da51267-51c5-4567-bd99-2d04b9fadc5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193867160 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4193867160
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2338226764
Short name T126
Test name
Test status
Simulation time 38427630 ps
CPU time 2.58 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 215444 kb
Host smart-193dd38f-725d-4856-9055-0e017cac65ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338226764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2338226764
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2825829879
Short name T1046
Test name
Test status
Simulation time 35637836 ps
CPU time 0.83 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 203916 kb
Host smart-e5180957-189e-4269-bb53-f77ba5b3688b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825829879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2825829879
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1796904296
Short name T1104
Test name
Test status
Simulation time 210526500 ps
CPU time 3.05 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:13:54 PM PDT 24
Peak memory 215496 kb
Host smart-975b090b-31b3-4bf6-bf2e-fedce8d2b15d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796904296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1796904296
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1188235824
Short name T113
Test name
Test status
Simulation time 474601087 ps
CPU time 2.94 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:49 PM PDT 24
Peak memory 215840 kb
Host smart-b0f3c0b3-aede-4d40-aa82-bb3c900b1700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188235824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1188235824
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2164518727
Short name T189
Test name
Test status
Simulation time 209225753 ps
CPU time 12.86 seconds
Started Jul 07 06:13:49 PM PDT 24
Finished Jul 07 06:14:02 PM PDT 24
Peak memory 215480 kb
Host smart-9738b2a2-334d-474f-9a02-16a97b62f638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164518727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2164518727
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2395529396
Short name T1069
Test name
Test status
Simulation time 70211783 ps
CPU time 3.93 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:14:00 PM PDT 24
Peak memory 217620 kb
Host smart-1015c7e3-5a88-4644-8752-0b3070177248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395529396 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2395529396
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3409362161
Short name T1126
Test name
Test status
Simulation time 101629343 ps
CPU time 2.64 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 215464 kb
Host smart-05fedffb-3700-40d7-a098-8f11f31d101c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409362161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3409362161
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2945505259
Short name T1138
Test name
Test status
Simulation time 12552724 ps
CPU time 0.71 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:47 PM PDT 24
Peak memory 204316 kb
Host smart-1776561d-6a95-454a-9891-157f3e1ceae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945505259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2945505259
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3543286851
Short name T146
Test name
Test status
Simulation time 290437353 ps
CPU time 1.91 seconds
Started Jul 07 06:13:53 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 207256 kb
Host smart-f7624028-ad3f-4927-87e2-62d5cc0efe05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543286851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3543286851
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2864937232
Short name T99
Test name
Test status
Simulation time 1148461281 ps
CPU time 4.59 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 215788 kb
Host smart-53c82f87-a18f-4257-b47d-83aa7893d7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864937232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2864937232
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.642199285
Short name T162
Test name
Test status
Simulation time 1049101919 ps
CPU time 8.76 seconds
Started Jul 07 06:13:46 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 215468 kb
Host smart-32055ad9-b175-4ea0-95f3-e9d1fe40249e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642199285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.642199285
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.166007397
Short name T1072
Test name
Test status
Simulation time 5301927508 ps
CPU time 15.11 seconds
Started Jul 07 06:13:29 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 207416 kb
Host smart-ec3396eb-0b60-4a50-aad4-d19c12e596d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166007397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.166007397
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2237707621
Short name T132
Test name
Test status
Simulation time 526948093 ps
CPU time 31.15 seconds
Started Jul 07 06:13:30 PM PDT 24
Finished Jul 07 06:14:02 PM PDT 24
Peak memory 207268 kb
Host smart-58b8fd24-e401-40f4-8cb8-42499d3aac56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237707621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2237707621
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4151915754
Short name T159
Test name
Test status
Simulation time 87749350 ps
CPU time 2.64 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 217932 kb
Host smart-65275477-1af9-4149-a30f-4835e729943b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151915754 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4151915754
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.89657154
Short name T128
Test name
Test status
Simulation time 74003073 ps
CPU time 1.36 seconds
Started Jul 07 06:13:30 PM PDT 24
Finished Jul 07 06:13:32 PM PDT 24
Peak memory 207348 kb
Host smart-9207b164-b80f-4681-88b1-2dbaed166a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89657154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.89657154
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3788359633
Short name T1119
Test name
Test status
Simulation time 23520869 ps
CPU time 0.74 seconds
Started Jul 07 06:13:24 PM PDT 24
Finished Jul 07 06:13:25 PM PDT 24
Peak memory 204028 kb
Host smart-ae20fd70-3da1-44d0-94ff-4c74b467312f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788359633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
788359633
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2892386792
Short name T1099
Test name
Test status
Simulation time 142949695 ps
CPU time 1.37 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:40 PM PDT 24
Peak memory 215536 kb
Host smart-8a5327c3-d73a-4d00-887e-a2d03b8e38ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892386792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2892386792
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.746721664
Short name T1060
Test name
Test status
Simulation time 40521766 ps
CPU time 0.69 seconds
Started Jul 07 06:13:29 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 203876 kb
Host smart-01f713cf-c96e-4db3-a1bb-29293298a4f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746721664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.746721664
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1333362972
Short name T1088
Test name
Test status
Simulation time 240044760 ps
CPU time 2.94 seconds
Started Jul 07 06:13:26 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 215556 kb
Host smart-5720a81e-4566-4284-80aa-109e72a5d160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333362972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1333362972
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1748325475
Short name T1102
Test name
Test status
Simulation time 229974009 ps
CPU time 3.57 seconds
Started Jul 07 06:13:23 PM PDT 24
Finished Jul 07 06:13:27 PM PDT 24
Peak memory 215744 kb
Host smart-575ad6b7-3e58-4017-a5b9-c144ef6d93c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748325475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
748325475
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.792526298
Short name T194
Test name
Test status
Simulation time 588787926 ps
CPU time 20.17 seconds
Started Jul 07 06:13:22 PM PDT 24
Finished Jul 07 06:13:42 PM PDT 24
Peak memory 215748 kb
Host smart-9a693fb0-dbcb-422c-ab98-4a5144ff892f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792526298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.792526298
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2955909409
Short name T1051
Test name
Test status
Simulation time 33195070 ps
CPU time 0.73 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:49 PM PDT 24
Peak memory 204032 kb
Host smart-a0aff22c-a109-45dd-8b59-db5593f17763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955909409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2955909409
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2649861127
Short name T1113
Test name
Test status
Simulation time 21393591 ps
CPU time 0.75 seconds
Started Jul 07 06:13:47 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 203920 kb
Host smart-f69e2d4c-3fc9-4a2e-9cd0-44d5149de261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649861127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2649861127
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3487920103
Short name T1076
Test name
Test status
Simulation time 103492417 ps
CPU time 0.73 seconds
Started Jul 07 06:13:48 PM PDT 24
Finished Jul 07 06:13:49 PM PDT 24
Peak memory 204012 kb
Host smart-6ae618bd-f3da-4985-81cd-f4ab27a6864e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487920103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3487920103
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2251793729
Short name T1045
Test name
Test status
Simulation time 57139449 ps
CPU time 0.77 seconds
Started Jul 07 06:13:50 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 204316 kb
Host smart-97b3d9b6-1d16-4cb7-bcf5-d8ebe546a9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251793729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2251793729
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3514438715
Short name T1075
Test name
Test status
Simulation time 20890720 ps
CPU time 0.72 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 204324 kb
Host smart-70689c04-f909-499a-b32e-cceb1b1e64f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514438715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3514438715
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.397934900
Short name T1037
Test name
Test status
Simulation time 12736836 ps
CPU time 0.76 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 204040 kb
Host smart-3447debf-4509-4685-8f3e-bd3c8482dd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397934900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.397934900
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4121148306
Short name T1139
Test name
Test status
Simulation time 42893314 ps
CPU time 0.71 seconds
Started Jul 07 06:13:56 PM PDT 24
Finished Jul 07 06:13:57 PM PDT 24
Peak memory 203960 kb
Host smart-f8171112-6aa9-47b4-bc7c-72698ef71896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121148306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4121148306
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1736384921
Short name T1042
Test name
Test status
Simulation time 26984885 ps
CPU time 0.86 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 204192 kb
Host smart-826b15ea-0626-4af5-992b-0d4a9da0d6a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736384921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1736384921
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1502417914
Short name T1109
Test name
Test status
Simulation time 31160357 ps
CPU time 0.7 seconds
Started Jul 07 06:13:50 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 204280 kb
Host smart-ceed2f15-16dc-4ba1-94aa-d0380c7e30cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502417914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1502417914
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.249270142
Short name T1117
Test name
Test status
Simulation time 11712624 ps
CPU time 0.69 seconds
Started Jul 07 06:13:50 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 203984 kb
Host smart-54515686-7965-460b-b3e2-51565783833c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249270142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.249270142
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4032830990
Short name T133
Test name
Test status
Simulation time 655982576 ps
CPU time 20.96 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:59 PM PDT 24
Peak memory 215444 kb
Host smart-40c12291-2a5e-4abc-9db3-ea34ff6fc76c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032830990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4032830990
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3244594344
Short name T129
Test name
Test status
Simulation time 1501713213 ps
CPU time 11.59 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:45 PM PDT 24
Peak memory 215368 kb
Host smart-7b14da2a-7a38-4163-aca0-df1c398ebf87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244594344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3244594344
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.776695341
Short name T90
Test name
Test status
Simulation time 74829950 ps
CPU time 1.26 seconds
Started Jul 07 06:13:34 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 207172 kb
Host smart-4f889838-6170-44e0-9619-cda9eb690b91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776695341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.776695341
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1675552636
Short name T1067
Test name
Test status
Simulation time 347692346 ps
CPU time 2.96 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:37 PM PDT 24
Peak memory 217020 kb
Host smart-e7e51b51-8af2-4193-85c5-d7f142ae288c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675552636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1675552636
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2216664417
Short name T1121
Test name
Test status
Simulation time 132626345 ps
CPU time 1.88 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:33 PM PDT 24
Peak memory 215452 kb
Host smart-a6f7b8f9-be27-49a3-89be-32c7c7eb1252
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216664417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
216664417
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2737231106
Short name T1068
Test name
Test status
Simulation time 158145760 ps
CPU time 0.71 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:32 PM PDT 24
Peak memory 203988 kb
Host smart-17aab029-1dc0-4f34-b2df-2aa83849f0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737231106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
737231106
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.687267142
Short name T123
Test name
Test status
Simulation time 83460436 ps
CPU time 1.72 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:29 PM PDT 24
Peak memory 215544 kb
Host smart-ef13de62-4fc0-4466-a441-184de0c1363c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687267142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.687267142
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.120913704
Short name T1041
Test name
Test status
Simulation time 52091573 ps
CPU time 0.76 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 204128 kb
Host smart-679c6a81-17e9-459d-a89b-7a88c8af286e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120913704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.120913704
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.270112526
Short name T1081
Test name
Test status
Simulation time 61196960 ps
CPU time 1.87 seconds
Started Jul 07 06:13:29 PM PDT 24
Finished Jul 07 06:13:31 PM PDT 24
Peak memory 207252 kb
Host smart-18125b9c-5872-40ff-aca7-52c279c3d755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270112526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.270112526
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.607678745
Short name T1133
Test name
Test status
Simulation time 37654651 ps
CPU time 2.24 seconds
Started Jul 07 06:13:28 PM PDT 24
Finished Jul 07 06:13:31 PM PDT 24
Peak memory 215672 kb
Host smart-e3590100-fa17-4a9d-bba4-f497d50d5c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607678745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.607678745
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2935608611
Short name T187
Test name
Test status
Simulation time 197262493 ps
CPU time 12.36 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:39 PM PDT 24
Peak memory 215496 kb
Host smart-4888af0b-b26f-48e3-9edd-286d55d57dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935608611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2935608611
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1848197109
Short name T1089
Test name
Test status
Simulation time 37269433 ps
CPU time 0.75 seconds
Started Jul 07 06:13:53 PM PDT 24
Finished Jul 07 06:13:54 PM PDT 24
Peak memory 204004 kb
Host smart-d0256eb1-083a-49da-9b93-53130b64f391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848197109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1848197109
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3504299038
Short name T1059
Test name
Test status
Simulation time 43858487 ps
CPU time 0.77 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 204340 kb
Host smart-1df84698-986a-4827-8e66-ca3e1d85dcce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504299038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3504299038
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3317243660
Short name T1066
Test name
Test status
Simulation time 13079391 ps
CPU time 0.7 seconds
Started Jul 07 06:13:49 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 203932 kb
Host smart-96019e60-a57e-4011-94bb-164a8c3b7dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317243660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3317243660
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.574065230
Short name T1054
Test name
Test status
Simulation time 116090749 ps
CPU time 0.74 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 203968 kb
Host smart-2600db1c-6b67-4c12-bc12-b3fdcd06d5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574065230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.574065230
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.511199382
Short name T1049
Test name
Test status
Simulation time 17230919 ps
CPU time 0.76 seconds
Started Jul 07 06:13:53 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 204040 kb
Host smart-4f56cb21-df42-48e9-aa0d-b76208b03ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511199382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.511199382
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2549531860
Short name T1048
Test name
Test status
Simulation time 19691577 ps
CPU time 0.83 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 203916 kb
Host smart-36649cc7-492a-4052-993f-d8cea0362e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549531860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2549531860
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3682971899
Short name T1055
Test name
Test status
Simulation time 18612698 ps
CPU time 0.72 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 203952 kb
Host smart-123438a5-ae12-4c08-9f0f-ac2e8f142df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682971899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3682971899
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1791962303
Short name T1103
Test name
Test status
Simulation time 36049013 ps
CPU time 0.69 seconds
Started Jul 07 06:13:50 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 203964 kb
Host smart-33820501-d952-4d06-9050-bbaad96ac777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791962303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1791962303
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3063660908
Short name T1058
Test name
Test status
Simulation time 45075078 ps
CPU time 0.72 seconds
Started Jul 07 06:13:50 PM PDT 24
Finished Jul 07 06:13:51 PM PDT 24
Peak memory 204356 kb
Host smart-9609ba2f-2eca-4d3b-a2ab-b42835fd6c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063660908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3063660908
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1419070583
Short name T1087
Test name
Test status
Simulation time 18308396 ps
CPU time 0.8 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:13:52 PM PDT 24
Peak memory 204028 kb
Host smart-fc77a0aa-c997-4fb6-b273-e5d80ee8d68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419070583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1419070583
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3609338076
Short name T1070
Test name
Test status
Simulation time 397594481 ps
CPU time 14.7 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 207292 kb
Host smart-4ba43b96-75e2-4877-9f86-16f72b4fe437
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609338076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3609338076
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1674604023
Short name T1086
Test name
Test status
Simulation time 1255326547 ps
CPU time 25.65 seconds
Started Jul 07 06:13:30 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 207472 kb
Host smart-6c4a9d82-4648-4673-8f10-6f0922ec92b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674604023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1674604023
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2818580073
Short name T89
Test name
Test status
Simulation time 35168971 ps
CPU time 1.27 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 207324 kb
Host smart-6af41e5b-3d1d-4e56-acb6-fb898542d4bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818580073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2818580073
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3034539591
Short name T158
Test name
Test status
Simulation time 190747328 ps
CPU time 2.57 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 216996 kb
Host smart-c5e0bba5-773f-46ac-b067-fdc7f7ccf833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034539591 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3034539591
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3914948145
Short name T1063
Test name
Test status
Simulation time 85502845 ps
CPU time 0.68 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:32 PM PDT 24
Peak memory 204320 kb
Host smart-e7721b8e-ff5e-43f5-b639-571c58dd5fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914948145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
914948145
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1642656627
Short name T130
Test name
Test status
Simulation time 126251076 ps
CPU time 1.72 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:40 PM PDT 24
Peak memory 215536 kb
Host smart-99bc8bd4-7789-41ab-a0a7-79f078bd92ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642656627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1642656627
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1323483525
Short name T1115
Test name
Test status
Simulation time 13807675 ps
CPU time 0.69 seconds
Started Jul 07 06:13:40 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 203900 kb
Host smart-d7e7fdb8-4128-453c-8bb4-f7b08708dfc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323483525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1323483525
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2482122294
Short name T1084
Test name
Test status
Simulation time 345389370 ps
CPU time 3.93 seconds
Started Jul 07 06:13:36 PM PDT 24
Finished Jul 07 06:13:40 PM PDT 24
Peak memory 215552 kb
Host smart-a26795a2-7f53-42bb-b2fc-0b03d1fb6be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482122294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2482122294
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1498455884
Short name T1125
Test name
Test status
Simulation time 5249569895 ps
CPU time 22.02 seconds
Started Jul 07 06:13:27 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 215632 kb
Host smart-5a651578-d829-43d4-a75e-e119ac010377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498455884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1498455884
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2718269744
Short name T1149
Test name
Test status
Simulation time 40388065 ps
CPU time 0.69 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:13:52 PM PDT 24
Peak memory 203956 kb
Host smart-3293d4fd-c9be-4780-8571-804106c4b4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718269744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2718269744
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.233129879
Short name T1033
Test name
Test status
Simulation time 43499917 ps
CPU time 0.7 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:55 PM PDT 24
Peak memory 204344 kb
Host smart-203dbad6-479d-46ea-86d1-91867fda3e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233129879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.233129879
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.142505716
Short name T1105
Test name
Test status
Simulation time 11958959 ps
CPU time 0.75 seconds
Started Jul 07 06:13:51 PM PDT 24
Finished Jul 07 06:13:52 PM PDT 24
Peak memory 203952 kb
Host smart-e60aed8f-721f-4114-a6c1-9d5b12e1787f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142505716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.142505716
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.79890229
Short name T1090
Test name
Test status
Simulation time 14710132 ps
CPU time 0.69 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 204316 kb
Host smart-8707e4cb-b17c-44c7-b89b-d8fb7efd375c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79890229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.79890229
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3389000196
Short name T1127
Test name
Test status
Simulation time 55881780 ps
CPU time 0.78 seconds
Started Jul 07 06:13:52 PM PDT 24
Finished Jul 07 06:13:53 PM PDT 24
Peak memory 204052 kb
Host smart-da2d472d-efa3-4aad-9306-772441496db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389000196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3389000196
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3849186214
Short name T1074
Test name
Test status
Simulation time 36458218 ps
CPU time 0.77 seconds
Started Jul 07 06:13:49 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 204076 kb
Host smart-742a21fe-7ebe-4802-ae17-8b5dabadb675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849186214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3849186214
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1656493796
Short name T1053
Test name
Test status
Simulation time 40641210 ps
CPU time 0.79 seconds
Started Jul 07 06:13:55 PM PDT 24
Finished Jul 07 06:13:57 PM PDT 24
Peak memory 204052 kb
Host smart-b449ff7a-e8a9-4b89-bfa8-2d924aeb35a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656493796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1656493796
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2882027969
Short name T1111
Test name
Test status
Simulation time 13201409 ps
CPU time 0.69 seconds
Started Jul 07 06:13:57 PM PDT 24
Finished Jul 07 06:13:59 PM PDT 24
Peak memory 204320 kb
Host smart-dd7bd5ac-53f8-45ba-a7d9-7165a1a210e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882027969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2882027969
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4185835141
Short name T1142
Test name
Test status
Simulation time 14913455 ps
CPU time 0.82 seconds
Started Jul 07 06:13:57 PM PDT 24
Finished Jul 07 06:13:59 PM PDT 24
Peak memory 204316 kb
Host smart-53c3b187-00e8-48f8-a721-47be03cac017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185835141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4185835141
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3232042483
Short name T1032
Test name
Test status
Simulation time 30274491 ps
CPU time 0.76 seconds
Started Jul 07 06:13:54 PM PDT 24
Finished Jul 07 06:13:56 PM PDT 24
Peak memory 204056 kb
Host smart-53828b18-7d13-4717-8b33-a63298be00fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232042483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3232042483
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3327567909
Short name T1096
Test name
Test status
Simulation time 122968995 ps
CPU time 1.88 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:36 PM PDT 24
Peak memory 215588 kb
Host smart-4b4d05fd-4d31-41a0-a8fc-346d21c56b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327567909 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3327567909
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2167527927
Short name T1044
Test name
Test status
Simulation time 75419790 ps
CPU time 1.17 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 218984 kb
Host smart-5857caa3-3fb5-40e4-ac3f-870091ef5dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167527927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
167527927
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.921394553
Short name T1061
Test name
Test status
Simulation time 23742938 ps
CPU time 0.71 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:32 PM PDT 24
Peak memory 204332 kb
Host smart-725818de-65cd-44a5-abb1-1ed61cc29cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921394553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.921394553
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.589597487
Short name T1107
Test name
Test status
Simulation time 61714026 ps
CPU time 1.68 seconds
Started Jul 07 06:13:34 PM PDT 24
Finished Jul 07 06:13:36 PM PDT 24
Peak memory 215508 kb
Host smart-0d62179d-c32f-4955-ad72-a93703cec68d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589597487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.589597487
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1284482404
Short name T1145
Test name
Test status
Simulation time 1826005022 ps
CPU time 4.99 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:39 PM PDT 24
Peak memory 216868 kb
Host smart-20882f10-9585-4424-9df1-f559d104f492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284482404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
284482404
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2345115336
Short name T101
Test name
Test status
Simulation time 212017852 ps
CPU time 7.35 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 215552 kb
Host smart-8893223c-3619-4104-a312-6c50d8abafaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345115336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2345115336
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2187389021
Short name T119
Test name
Test status
Simulation time 48959374 ps
CPU time 1.66 seconds
Started Jul 07 06:13:30 PM PDT 24
Finished Jul 07 06:13:32 PM PDT 24
Peak memory 215476 kb
Host smart-f10a62d9-8f6c-4771-988c-f8363967f34b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187389021 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2187389021
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.206403214
Short name T1150
Test name
Test status
Simulation time 201870103 ps
CPU time 2.33 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 215480 kb
Host smart-40269653-f9c4-4807-9524-c0f1a0ca8622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206403214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.206403214
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3150083243
Short name T1036
Test name
Test status
Simulation time 41006020 ps
CPU time 0.68 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 203964 kb
Host smart-519f33a7-26d7-4fa1-a8ad-d8127fc231cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150083243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
150083243
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.213192291
Short name T1130
Test name
Test status
Simulation time 29158693 ps
CPU time 1.79 seconds
Started Jul 07 06:13:32 PM PDT 24
Finished Jul 07 06:13:34 PM PDT 24
Peak memory 215772 kb
Host smart-b4822669-940b-4e59-b052-f8fad1161e64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213192291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.213192291
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1587422964
Short name T1123
Test name
Test status
Simulation time 88617929 ps
CPU time 2.87 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:37 PM PDT 24
Peak memory 216004 kb
Host smart-229b0fdd-caf6-4b90-9c2a-a68842f8c5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587422964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
587422964
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1454726359
Short name T188
Test name
Test status
Simulation time 296305214 ps
CPU time 18.11 seconds
Started Jul 07 06:13:31 PM PDT 24
Finished Jul 07 06:13:50 PM PDT 24
Peak memory 215532 kb
Host smart-1e9d5a56-1d57-4a13-a25d-c0b44c1a5ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454726359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1454726359
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.688560131
Short name T1080
Test name
Test status
Simulation time 274697208 ps
CPU time 3.71 seconds
Started Jul 07 06:13:43 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 218748 kb
Host smart-32741148-2ce3-4c5c-beee-2a399bbe36e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688560131 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.688560131
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2484719154
Short name T1097
Test name
Test status
Simulation time 739258519 ps
CPU time 2.05 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:38 PM PDT 24
Peak memory 215576 kb
Host smart-ccb56773-7e87-449f-b8d6-fd8508470d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484719154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
484719154
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1713224984
Short name T1064
Test name
Test status
Simulation time 22352218 ps
CPU time 0.74 seconds
Started Jul 07 06:13:34 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 203960 kb
Host smart-fdfc9f15-6a47-4e78-b9fd-7c447cf45418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713224984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
713224984
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3233193035
Short name T1108
Test name
Test status
Simulation time 195636740 ps
CPU time 2.79 seconds
Started Jul 07 06:13:37 PM PDT 24
Finished Jul 07 06:13:40 PM PDT 24
Peak memory 215500 kb
Host smart-a705343e-63c5-474c-a8c1-1d269ed16a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233193035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3233193035
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3163855344
Short name T1146
Test name
Test status
Simulation time 429845836 ps
CPU time 4.83 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:41 PM PDT 24
Peak memory 215820 kb
Host smart-f55eff8e-a66f-45ec-956a-f4d148cded99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163855344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
163855344
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3017160458
Short name T186
Test name
Test status
Simulation time 1166989566 ps
CPU time 12.32 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:48 PM PDT 24
Peak memory 215552 kb
Host smart-35ab1842-f035-4710-b611-71feffb751c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017160458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3017160458
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2337829585
Short name T118
Test name
Test status
Simulation time 222363720 ps
CPU time 3.86 seconds
Started Jul 07 06:13:39 PM PDT 24
Finished Jul 07 06:13:44 PM PDT 24
Peak memory 218536 kb
Host smart-66ef81d1-0d53-4768-aac0-bab44bf7d2c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337829585 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2337829585
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3080236552
Short name T131
Test name
Test status
Simulation time 43001906 ps
CPU time 1.29 seconds
Started Jul 07 06:13:36 PM PDT 24
Finished Jul 07 06:13:37 PM PDT 24
Peak memory 207276 kb
Host smart-042b53fd-10f0-41d5-bdc2-994b7bb85280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080236552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
080236552
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2377279245
Short name T1056
Test name
Test status
Simulation time 23189860 ps
CPU time 0.73 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:36 PM PDT 24
Peak memory 203980 kb
Host smart-47ce8210-a2c1-4712-8d3e-8cdd98b56673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377279245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
377279245
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2777411229
Short name T1114
Test name
Test status
Simulation time 627668904 ps
CPU time 3.97 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:39 PM PDT 24
Peak memory 215516 kb
Host smart-a599d608-9de7-4614-83e7-7686d4325092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777411229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2777411229
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.402343864
Short name T116
Test name
Test status
Simulation time 158383030 ps
CPU time 2.97 seconds
Started Jul 07 06:13:34 PM PDT 24
Finished Jul 07 06:13:38 PM PDT 24
Peak memory 216132 kb
Host smart-1806b699-49ca-469a-82ec-6ed73f714dab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402343864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.402343864
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1034542286
Short name T1134
Test name
Test status
Simulation time 1464410869 ps
CPU time 15.59 seconds
Started Jul 07 06:13:38 PM PDT 24
Finished Jul 07 06:13:54 PM PDT 24
Peak memory 215988 kb
Host smart-3b119627-9201-4f52-b7ea-62b176c6d371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034542286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1034542286
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3986871933
Short name T117
Test name
Test status
Simulation time 366692102 ps
CPU time 2.47 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:38 PM PDT 24
Peak memory 217440 kb
Host smart-fc2c091b-00c2-4bbf-806f-13e399167fd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986871933 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3986871933
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.526742630
Short name T147
Test name
Test status
Simulation time 360413648 ps
CPU time 2.86 seconds
Started Jul 07 06:13:34 PM PDT 24
Finished Jul 07 06:13:38 PM PDT 24
Peak memory 215824 kb
Host smart-36edffcd-9b57-469a-a8a3-7c569a824e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526742630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.526742630
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3028518115
Short name T1052
Test name
Test status
Simulation time 43929808 ps
CPU time 0.71 seconds
Started Jul 07 06:13:33 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 204052 kb
Host smart-d1bdd3dd-71a3-4447-adfd-a7d36a130146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028518115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
028518115
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.882972484
Short name T144
Test name
Test status
Simulation time 58726229 ps
CPU time 3.59 seconds
Started Jul 07 06:13:39 PM PDT 24
Finished Jul 07 06:13:43 PM PDT 24
Peak memory 215464 kb
Host smart-f6a58c4e-bdb3-43fe-aeb4-8d993be75bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882972484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.882972484
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4091979374
Short name T1141
Test name
Test status
Simulation time 168660165 ps
CPU time 2.64 seconds
Started Jul 07 06:13:36 PM PDT 24
Finished Jul 07 06:13:39 PM PDT 24
Peak memory 215684 kb
Host smart-dc5aa291-7446-444d-95c0-48c6761d593e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091979374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
091979374
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3708574961
Short name T1050
Test name
Test status
Simulation time 298306665 ps
CPU time 8.35 seconds
Started Jul 07 06:13:35 PM PDT 24
Finished Jul 07 06:13:43 PM PDT 24
Peak memory 215532 kb
Host smart-47e8b23d-83dc-47b7-9a02-1202c166aa58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708574961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3708574961
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1911799918
Short name T626
Test name
Test status
Simulation time 19787776 ps
CPU time 0.77 seconds
Started Jul 07 06:28:39 PM PDT 24
Finished Jul 07 06:28:40 PM PDT 24
Peak memory 206388 kb
Host smart-cf75a0dd-e690-41dd-808e-bd85681d7dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911799918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
911799918
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2679957195
Short name T366
Test name
Test status
Simulation time 10405309076 ps
CPU time 18.69 seconds
Started Jul 07 06:28:31 PM PDT 24
Finished Jul 07 06:28:51 PM PDT 24
Peak memory 225644 kb
Host smart-50ca29b0-6aae-4a56-a0ee-bbe0dd4885ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679957195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2679957195
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.480044438
Short name T77
Test name
Test status
Simulation time 197243714 ps
CPU time 0.81 seconds
Started Jul 07 06:28:26 PM PDT 24
Finished Jul 07 06:28:27 PM PDT 24
Peak memory 207516 kb
Host smart-9c7c5853-82c3-401a-88ed-f664bfafb0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480044438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.480044438
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3222477153
Short name T534
Test name
Test status
Simulation time 6404377190 ps
CPU time 17.64 seconds
Started Jul 07 06:28:38 PM PDT 24
Finished Jul 07 06:28:56 PM PDT 24
Peak memory 238328 kb
Host smart-e99c0333-c8be-433b-9fb3-a7432dbfdec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222477153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3222477153
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2068257928
Short name T867
Test name
Test status
Simulation time 10577441757 ps
CPU time 70.73 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:29:46 PM PDT 24
Peak memory 257848 kb
Host smart-53947649-f753-4259-914c-436db7179f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068257928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2068257928
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.963983291
Short name T983
Test name
Test status
Simulation time 29144516996 ps
CPU time 270.93 seconds
Started Jul 07 06:28:37 PM PDT 24
Finished Jul 07 06:33:08 PM PDT 24
Peak memory 254852 kb
Host smart-47a6ec8a-bd00-47b8-a6fc-81c136eb43ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963983291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
963983291
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1046468436
Short name T470
Test name
Test status
Simulation time 1130692932 ps
CPU time 7.74 seconds
Started Jul 07 06:28:39 PM PDT 24
Finished Jul 07 06:28:47 PM PDT 24
Peak memory 241996 kb
Host smart-ac20399a-d400-4fb9-94f2-d69b9df32e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046468436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1046468436
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2534004257
Short name T206
Test name
Test status
Simulation time 11567682281 ps
CPU time 61.36 seconds
Started Jul 07 06:28:36 PM PDT 24
Finished Jul 07 06:29:38 PM PDT 24
Peak memory 241984 kb
Host smart-a336f75a-e0e1-4572-8caa-3417ae9579a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534004257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2534004257
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2747756183
Short name T1006
Test name
Test status
Simulation time 176731313 ps
CPU time 3.36 seconds
Started Jul 07 06:28:36 PM PDT 24
Finished Jul 07 06:28:40 PM PDT 24
Peak memory 233736 kb
Host smart-720c339a-da8e-46cb-b798-0ef473958cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747756183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2747756183
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2282048679
Short name T701
Test name
Test status
Simulation time 114508792 ps
CPU time 4.79 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:28:40 PM PDT 24
Peak memory 224324 kb
Host smart-a23170af-f70e-465e-a8f5-9fa6a23d0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282048679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2282048679
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.524017719
Short name T823
Test name
Test status
Simulation time 111789557 ps
CPU time 1.11 seconds
Started Jul 07 06:28:26 PM PDT 24
Finished Jul 07 06:28:27 PM PDT 24
Peak memory 217676 kb
Host smart-0f5cfc6c-080e-4b15-b074-779f2a99f9ee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524017719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.524017719
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.338381445
Short name T659
Test name
Test status
Simulation time 847762544 ps
CPU time 4.85 seconds
Started Jul 07 06:28:33 PM PDT 24
Finished Jul 07 06:28:38 PM PDT 24
Peak memory 225536 kb
Host smart-c07894e2-cdf2-441a-a780-3a1d796d2444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338381445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
338381445
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2132600003
Short name T581
Test name
Test status
Simulation time 15699844837 ps
CPU time 12.39 seconds
Started Jul 07 06:28:34 PM PDT 24
Finished Jul 07 06:28:46 PM PDT 24
Peak memory 240596 kb
Host smart-0d9796dd-60a5-4024-a1ae-c48907ac1a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132600003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2132600003
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3762660843
Short name T44
Test name
Test status
Simulation time 279056374 ps
CPU time 5.94 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:28:41 PM PDT 24
Peak memory 222972 kb
Host smart-7801a9eb-9fc3-4c6c-84c9-43bbde48e60d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3762660843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3762660843
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2369152255
Short name T69
Test name
Test status
Simulation time 229117944 ps
CPU time 0.97 seconds
Started Jul 07 06:28:37 PM PDT 24
Finished Jul 07 06:28:39 PM PDT 24
Peak memory 236720 kb
Host smart-4f30d620-da85-420e-b4b3-8994b2a05caf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369152255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2369152255
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.137845569
Short name T136
Test name
Test status
Simulation time 9535386566 ps
CPU time 48.41 seconds
Started Jul 07 06:28:36 PM PDT 24
Finished Jul 07 06:29:25 PM PDT 24
Peak memory 252404 kb
Host smart-9b5a868f-6186-4d5c-a0d1-8443ccd7dc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137845569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.137845569
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1127037423
Short name T368
Test name
Test status
Simulation time 5199785576 ps
CPU time 7.7 seconds
Started Jul 07 06:28:31 PM PDT 24
Finished Jul 07 06:28:39 PM PDT 24
Peak memory 217500 kb
Host smart-defa001c-996e-454b-92f6-9c71627f2901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127037423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1127037423
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4174296891
Short name T381
Test name
Test status
Simulation time 139308537 ps
CPU time 1.04 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:28:37 PM PDT 24
Peak memory 208444 kb
Host smart-40fa258e-e4e0-4206-b892-3ba1b106014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174296891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4174296891
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2771055040
Short name T92
Test name
Test status
Simulation time 14247127 ps
CPU time 0.74 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:28:36 PM PDT 24
Peak memory 206960 kb
Host smart-7570d2ad-7b2b-4470-ade6-3bd2e1b1bc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771055040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2771055040
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2650761747
Short name T813
Test name
Test status
Simulation time 1016077872 ps
CPU time 4.97 seconds
Started Jul 07 06:28:35 PM PDT 24
Finished Jul 07 06:28:41 PM PDT 24
Peak memory 235836 kb
Host smart-dfbb2eb2-3e21-45f3-a529-e6129ab20247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650761747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2650761747
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4099229519
Short name T365
Test name
Test status
Simulation time 11916607 ps
CPU time 0.75 seconds
Started Jul 07 06:28:53 PM PDT 24
Finished Jul 07 06:28:54 PM PDT 24
Peak memory 206372 kb
Host smart-5d7c87f9-f79e-427d-a8e0-ef3d22ae0b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099229519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
099229519
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2687226308
Short name T279
Test name
Test status
Simulation time 793316662 ps
CPU time 9.45 seconds
Started Jul 07 06:28:50 PM PDT 24
Finished Jul 07 06:29:00 PM PDT 24
Peak memory 225496 kb
Host smart-8d6d1b9b-db8f-49be-ab4e-3a27cdbf1b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687226308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2687226308
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.182267256
Short name T738
Test name
Test status
Simulation time 19729408 ps
CPU time 0.81 seconds
Started Jul 07 06:28:40 PM PDT 24
Finished Jul 07 06:28:41 PM PDT 24
Peak memory 207516 kb
Host smart-84898e3d-28e3-4ff9-b5df-30396ee26a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182267256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.182267256
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.479794302
Short name T283
Test name
Test status
Simulation time 2041439301 ps
CPU time 23.52 seconds
Started Jul 07 06:28:56 PM PDT 24
Finished Jul 07 06:29:20 PM PDT 24
Peak memory 225580 kb
Host smart-1cc38e94-0bee-4bd6-8b4b-e2659e757493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479794302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.479794302
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1221060571
Short name T245
Test name
Test status
Simulation time 25604301612 ps
CPU time 47.51 seconds
Started Jul 07 06:28:54 PM PDT 24
Finished Jul 07 06:29:41 PM PDT 24
Peak memory 236772 kb
Host smart-723c2e4f-2287-46dd-b7c2-4e42dbd79b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221060571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1221060571
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.263116858
Short name T140
Test name
Test status
Simulation time 15519938625 ps
CPU time 64.22 seconds
Started Jul 07 06:28:54 PM PDT 24
Finished Jul 07 06:29:59 PM PDT 24
Peak memory 225472 kb
Host smart-85a46e4b-0435-4473-8758-88c125b970a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263116858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
263116858
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4228979493
Short name T955
Test name
Test status
Simulation time 889756633 ps
CPU time 5.84 seconds
Started Jul 07 06:28:51 PM PDT 24
Finished Jul 07 06:28:57 PM PDT 24
Peak memory 225532 kb
Host smart-54a4e8ac-6ca5-40ed-866c-2efdd1fa0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228979493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4228979493
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.97597671
Short name T369
Test name
Test status
Simulation time 56528254 ps
CPU time 0.78 seconds
Started Jul 07 06:28:52 PM PDT 24
Finished Jul 07 06:28:53 PM PDT 24
Peak memory 216916 kb
Host smart-0a927f22-33f9-4311-905d-50060d6a7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97597671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.97597671
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2530670869
Short name T95
Test name
Test status
Simulation time 6378816630 ps
CPU time 16.67 seconds
Started Jul 07 06:28:43 PM PDT 24
Finished Jul 07 06:29:00 PM PDT 24
Peak memory 233860 kb
Host smart-97e0f5dd-8fea-42d2-8c09-3104e4f1b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530670869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2530670869
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3500009845
Short name T933
Test name
Test status
Simulation time 437996176 ps
CPU time 9.08 seconds
Started Jul 07 06:28:49 PM PDT 24
Finished Jul 07 06:28:58 PM PDT 24
Peak memory 233764 kb
Host smart-79320a30-0f96-4896-9179-5e16f4e88333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500009845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3500009845
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2125309265
Short name T728
Test name
Test status
Simulation time 26612746 ps
CPU time 1.08 seconds
Started Jul 07 06:28:41 PM PDT 24
Finished Jul 07 06:28:42 PM PDT 24
Peak memory 217664 kb
Host smart-c30bc58a-5572-4111-b677-30fa443efaef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125309265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2125309265
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3067335310
Short name T632
Test name
Test status
Simulation time 568875514 ps
CPU time 3.91 seconds
Started Jul 07 06:28:42 PM PDT 24
Finished Jul 07 06:28:46 PM PDT 24
Peak memory 233724 kb
Host smart-a9b5bb92-d90c-4173-9f64-7f41e9fe89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067335310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3067335310
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4046913470
Short name T263
Test name
Test status
Simulation time 900988859 ps
CPU time 9.01 seconds
Started Jul 07 06:28:40 PM PDT 24
Finished Jul 07 06:28:49 PM PDT 24
Peak memory 233764 kb
Host smart-46be42ca-425e-455c-8fd4-6d5271c1eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046913470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4046913470
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1843220208
Short name T451
Test name
Test status
Simulation time 1372558688 ps
CPU time 11.26 seconds
Started Jul 07 06:28:55 PM PDT 24
Finished Jul 07 06:29:06 PM PDT 24
Peak memory 223744 kb
Host smart-0ab6205f-bb93-4e91-a5d3-8b509f8f1498
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1843220208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1843220208
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3153867545
Short name T70
Test name
Test status
Simulation time 169347857 ps
CPU time 1.25 seconds
Started Jul 07 06:28:55 PM PDT 24
Finished Jul 07 06:28:56 PM PDT 24
Peak memory 237776 kb
Host smart-7b5deac9-a8bb-4662-a848-d4143d39fe9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153867545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3153867545
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.549622619
Short name T500
Test name
Test status
Simulation time 2853448066 ps
CPU time 8.29 seconds
Started Jul 07 06:28:38 PM PDT 24
Finished Jul 07 06:28:47 PM PDT 24
Peak memory 217540 kb
Host smart-caf3c253-042a-4659-b853-a911d83d2e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549622619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.549622619
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2893036751
Short name T940
Test name
Test status
Simulation time 4813518402 ps
CPU time 13.15 seconds
Started Jul 07 06:28:37 PM PDT 24
Finished Jul 07 06:28:50 PM PDT 24
Peak memory 217444 kb
Host smart-b99c74de-caf0-42a1-b230-bcff4a275063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893036751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2893036751
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.954138410
Short name T461
Test name
Test status
Simulation time 231418899 ps
CPU time 1.91 seconds
Started Jul 07 06:28:39 PM PDT 24
Finished Jul 07 06:28:41 PM PDT 24
Peak memory 217344 kb
Host smart-1a46faff-5944-4057-9270-227f18e9f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954138410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.954138410
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4191604845
Short name T448
Test name
Test status
Simulation time 85566506 ps
CPU time 0.83 seconds
Started Jul 07 06:28:41 PM PDT 24
Finished Jul 07 06:28:42 PM PDT 24
Peak memory 206972 kb
Host smart-0c0e9c03-8cf7-4fa0-9733-7a7d89897670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191604845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4191604845
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3393369734
Short name T753
Test name
Test status
Simulation time 1617334988 ps
CPU time 7.48 seconds
Started Jul 07 06:28:47 PM PDT 24
Finished Jul 07 06:28:55 PM PDT 24
Peak memory 225564 kb
Host smart-4a5c0aef-a269-420a-9a4e-98465c5e4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393369734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3393369734
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.159347841
Short name T517
Test name
Test status
Simulation time 11710586 ps
CPU time 0.71 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:30:22 PM PDT 24
Peak memory 205796 kb
Host smart-22a63d99-cba4-4480-9f10-2421a4f7a3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159347841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.159347841
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4238991712
Short name T866
Test name
Test status
Simulation time 72211961 ps
CPU time 2.2 seconds
Started Jul 07 06:30:18 PM PDT 24
Finished Jul 07 06:30:20 PM PDT 24
Peak memory 225212 kb
Host smart-c585e260-d613-446d-b468-3641ac31f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238991712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4238991712
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3863630006
Short name T794
Test name
Test status
Simulation time 19278908 ps
CPU time 0.79 seconds
Started Jul 07 06:30:14 PM PDT 24
Finished Jul 07 06:30:15 PM PDT 24
Peak memory 207508 kb
Host smart-7e6b1015-0c53-4b78-a0eb-8512bd531680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863630006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3863630006
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3976354621
Short name T322
Test name
Test status
Simulation time 24998666871 ps
CPU time 89.06 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:31:50 PM PDT 24
Peak memory 257180 kb
Host smart-756c8b1d-105e-4a58-a418-08ff0cf3337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976354621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3976354621
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1923949798
Short name T571
Test name
Test status
Simulation time 25897857322 ps
CPU time 108.46 seconds
Started Jul 07 06:30:25 PM PDT 24
Finished Jul 07 06:32:14 PM PDT 24
Peak memory 258620 kb
Host smart-80ab57d8-7b7a-43fb-aaf4-6191b9c8c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923949798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1923949798
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1870479533
Short name T962
Test name
Test status
Simulation time 30599289255 ps
CPU time 114.5 seconds
Started Jul 07 06:30:25 PM PDT 24
Finished Jul 07 06:32:20 PM PDT 24
Peak memory 239480 kb
Host smart-e06e2452-ad18-488f-89f5-ab2b6a878da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870479533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1870479533
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.262992917
Short name T332
Test name
Test status
Simulation time 3224861739 ps
CPU time 57.7 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:31:19 PM PDT 24
Peak memory 233872 kb
Host smart-24aa5caa-b48a-427e-b054-c50f32621ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262992917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.262992917
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.519015113
Short name T274
Test name
Test status
Simulation time 4716975107 ps
CPU time 80.48 seconds
Started Jul 07 06:30:18 PM PDT 24
Finished Jul 07 06:31:38 PM PDT 24
Peak memory 253040 kb
Host smart-1df0281f-1dec-483f-874e-292e29aae664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519015113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.519015113
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3116002304
Short name T523
Test name
Test status
Simulation time 75965265 ps
CPU time 2.47 seconds
Started Jul 07 06:30:14 PM PDT 24
Finished Jul 07 06:30:17 PM PDT 24
Peak memory 233788 kb
Host smart-1d0e2a64-2677-4ca6-9ac8-d448dfc4d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116002304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3116002304
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.864627413
Short name T751
Test name
Test status
Simulation time 21683056618 ps
CPU time 86.46 seconds
Started Jul 07 06:30:16 PM PDT 24
Finished Jul 07 06:31:43 PM PDT 24
Peak memory 240812 kb
Host smart-ca2b7097-c53a-474c-a08b-56aa16c17cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864627413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.864627413
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1067464661
Short name T920
Test name
Test status
Simulation time 94938911 ps
CPU time 1.08 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:16 PM PDT 24
Peak memory 217640 kb
Host smart-bf71954c-2994-4de1-92af-248d9facafa5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067464661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1067464661
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2605702356
Short name T289
Test name
Test status
Simulation time 2944555180 ps
CPU time 10.43 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:25 PM PDT 24
Peak memory 249704 kb
Host smart-35f0bddc-98d5-441d-8635-967b758ceb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605702356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2605702356
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1691966679
Short name T719
Test name
Test status
Simulation time 85318200456 ps
CPU time 19.15 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:35 PM PDT 24
Peak memory 233852 kb
Host smart-ae5d4f1f-b7ba-471e-9ed4-6a70b0a8d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691966679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1691966679
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.577336454
Short name T149
Test name
Test status
Simulation time 5739928718 ps
CPU time 13.27 seconds
Started Jul 07 06:30:17 PM PDT 24
Finished Jul 07 06:30:30 PM PDT 24
Peak memory 224324 kb
Host smart-831b0d55-c3c0-4ad6-bbf6-1a3bea7e0d36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577336454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.577336454
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3128912262
Short name T573
Test name
Test status
Simulation time 57365097 ps
CPU time 1.13 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:30:22 PM PDT 24
Peak memory 208692 kb
Host smart-dedec92e-12e5-45ad-a139-ef8b911cbab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128912262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3128912262
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3738898455
Short name T342
Test name
Test status
Simulation time 8625952802 ps
CPU time 18.39 seconds
Started Jul 07 06:30:13 PM PDT 24
Finished Jul 07 06:30:31 PM PDT 24
Peak memory 217664 kb
Host smart-0af3f18f-5a3a-4e30-90dd-cd1b511077d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738898455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3738898455
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3495797406
Short name T702
Test name
Test status
Simulation time 14738192091 ps
CPU time 11.38 seconds
Started Jul 07 06:30:14 PM PDT 24
Finished Jul 07 06:30:26 PM PDT 24
Peak memory 217548 kb
Host smart-d150dfa4-5ed8-4e83-adbd-51938b02de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495797406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3495797406
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1868432647
Short name T636
Test name
Test status
Simulation time 41495252 ps
CPU time 1.28 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:16 PM PDT 24
Peak memory 208936 kb
Host smart-b77dc3b4-9f11-46b5-85f8-c90345f72a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868432647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1868432647
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1520453887
Short name T924
Test name
Test status
Simulation time 248284201 ps
CPU time 0.88 seconds
Started Jul 07 06:30:14 PM PDT 24
Finished Jul 07 06:30:15 PM PDT 24
Peak memory 206968 kb
Host smart-086dfc25-cad7-405a-9658-58e170f84f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520453887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1520453887
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3425410972
Short name T970
Test name
Test status
Simulation time 5651054632 ps
CPU time 10.74 seconds
Started Jul 07 06:30:19 PM PDT 24
Finished Jul 07 06:30:30 PM PDT 24
Peak memory 225696 kb
Host smart-d8daf560-1393-490e-8c8e-04aa1d59640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425410972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3425410972
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2314403366
Short name T624
Test name
Test status
Simulation time 12978925 ps
CPU time 0.78 seconds
Started Jul 07 06:30:30 PM PDT 24
Finished Jul 07 06:30:31 PM PDT 24
Peak memory 206412 kb
Host smart-663a596b-f998-42d2-8e39-c7668d938bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314403366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2314403366
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4009936822
Short name T453
Test name
Test status
Simulation time 34075885 ps
CPU time 2.4 seconds
Started Jul 07 06:30:27 PM PDT 24
Finished Jul 07 06:30:30 PM PDT 24
Peak memory 233464 kb
Host smart-a2fda5ac-4e23-414f-b6f0-85d1f56400b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009936822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4009936822
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.160584025
Short name T444
Test name
Test status
Simulation time 49419379 ps
CPU time 0.73 seconds
Started Jul 07 06:30:24 PM PDT 24
Finished Jul 07 06:30:25 PM PDT 24
Peak memory 206492 kb
Host smart-e3f50dbf-14bf-4cd9-9b81-fe1be2f7b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160584025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.160584025
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1844434122
Short name T811
Test name
Test status
Simulation time 28754256873 ps
CPU time 129.56 seconds
Started Jul 07 06:30:26 PM PDT 24
Finished Jul 07 06:32:36 PM PDT 24
Peak memory 255256 kb
Host smart-7d750084-65b4-4375-84d4-54f5d49dacea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844434122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1844434122
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3370124842
Short name T198
Test name
Test status
Simulation time 3513417079 ps
CPU time 40.86 seconds
Started Jul 07 06:30:30 PM PDT 24
Finished Jul 07 06:31:11 PM PDT 24
Peak memory 257808 kb
Host smart-273da31f-90fd-478d-9d8c-0f07a198f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370124842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3370124842
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2367766604
Short name T57
Test name
Test status
Simulation time 182104710651 ps
CPU time 550.75 seconds
Started Jul 07 06:30:30 PM PDT 24
Finished Jul 07 06:39:41 PM PDT 24
Peak memory 262688 kb
Host smart-2e3c61ba-d613-46f6-a3bf-7ef94076c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367766604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2367766604
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.312100085
Short name T835
Test name
Test status
Simulation time 18667968217 ps
CPU time 134.37 seconds
Started Jul 07 06:30:31 PM PDT 24
Finished Jul 07 06:32:45 PM PDT 24
Peak memory 258108 kb
Host smart-409ca98b-8afe-4aed-a738-3e25ef3550ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312100085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.312100085
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1775125027
Short name T810
Test name
Test status
Simulation time 19306172283 ps
CPU time 56.51 seconds
Started Jul 07 06:30:26 PM PDT 24
Finished Jul 07 06:31:22 PM PDT 24
Peak memory 237852 kb
Host smart-878b8832-611c-4e8e-9fc2-f03b3a9911b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775125027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1775125027
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.749475897
Short name T945
Test name
Test status
Simulation time 11551105968 ps
CPU time 33.5 seconds
Started Jul 07 06:30:23 PM PDT 24
Finished Jul 07 06:30:57 PM PDT 24
Peak memory 234932 kb
Host smart-b4614c2e-e751-4769-9e64-0e0212ec55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749475897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.749475897
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3082571813
Short name T7
Test name
Test status
Simulation time 1932907901 ps
CPU time 7.53 seconds
Started Jul 07 06:30:20 PM PDT 24
Finished Jul 07 06:30:27 PM PDT 24
Peak memory 233716 kb
Host smart-71f20e40-4bde-4621-a560-eb1b9f5db367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082571813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3082571813
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2082040921
Short name T409
Test name
Test status
Simulation time 1647543021 ps
CPU time 6.35 seconds
Started Jul 07 06:30:30 PM PDT 24
Finished Jul 07 06:30:37 PM PDT 24
Peak memory 222856 kb
Host smart-6419953b-a19e-4efa-9bc1-fd493f2ad721
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082040921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2082040921
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1707719928
Short name T1003
Test name
Test status
Simulation time 23387313399 ps
CPU time 38.17 seconds
Started Jul 07 06:30:23 PM PDT 24
Finished Jul 07 06:31:01 PM PDT 24
Peak memory 217516 kb
Host smart-1c625ab9-c489-42e8-9d0b-3f9e9cc94c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707719928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1707719928
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.617727821
Short name T80
Test name
Test status
Simulation time 8825305001 ps
CPU time 5.36 seconds
Started Jul 07 06:30:25 PM PDT 24
Finished Jul 07 06:30:31 PM PDT 24
Peak memory 217476 kb
Host smart-e77b4e30-42ba-47bb-b2c3-ddd8faf8d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617727821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.617727821
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1529025459
Short name T507
Test name
Test status
Simulation time 202185617 ps
CPU time 2.4 seconds
Started Jul 07 06:30:21 PM PDT 24
Finished Jul 07 06:30:24 PM PDT 24
Peak memory 217324 kb
Host smart-9c94c02b-df4f-4aeb-b8d4-53c7f9cb79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529025459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1529025459
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3782309576
Short name T586
Test name
Test status
Simulation time 21578729 ps
CPU time 0.77 seconds
Started Jul 07 06:30:24 PM PDT 24
Finished Jul 07 06:30:25 PM PDT 24
Peak memory 206968 kb
Host smart-caef73f3-aa98-4c52-9237-b15e8ab16f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782309576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3782309576
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2506211097
Short name T1022
Test name
Test status
Simulation time 144770557 ps
CPU time 2.44 seconds
Started Jul 07 06:30:25 PM PDT 24
Finished Jul 07 06:30:28 PM PDT 24
Peak memory 233536 kb
Host smart-20fb5bf6-f078-47b7-a7e8-ff2a915dbc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506211097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2506211097
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2548129874
Short name T1008
Test name
Test status
Simulation time 12057436 ps
CPU time 0.72 seconds
Started Jul 07 06:30:37 PM PDT 24
Finished Jul 07 06:30:38 PM PDT 24
Peak memory 205812 kb
Host smart-2c86bfbb-205d-45ce-9214-a359c4fe7237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548129874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2548129874
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3350586111
Short name T1028
Test name
Test status
Simulation time 357066402 ps
CPU time 2.49 seconds
Started Jul 07 06:30:35 PM PDT 24
Finished Jul 07 06:30:37 PM PDT 24
Peak memory 225612 kb
Host smart-d0ff3aa7-1af0-477c-b852-eaae788201e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350586111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3350586111
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1180127400
Short name T938
Test name
Test status
Simulation time 51208524 ps
CPU time 0.75 seconds
Started Jul 07 06:30:29 PM PDT 24
Finished Jul 07 06:30:30 PM PDT 24
Peak memory 207692 kb
Host smart-e96c422c-af45-4031-8d9f-cecb8c8e1022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180127400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1180127400
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2305688540
Short name T641
Test name
Test status
Simulation time 3118558213 ps
CPU time 57.99 seconds
Started Jul 07 06:30:39 PM PDT 24
Finished Jul 07 06:31:38 PM PDT 24
Peak memory 254176 kb
Host smart-67b6adce-e294-444d-b0f4-dd0adefa2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305688540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2305688540
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1867576341
Short name T667
Test name
Test status
Simulation time 20205059966 ps
CPU time 112 seconds
Started Jul 07 06:30:37 PM PDT 24
Finished Jul 07 06:32:30 PM PDT 24
Peak memory 255340 kb
Host smart-e9f93c8c-c512-480e-8b43-5eca2fe0e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867576341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1867576341
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3879098500
Short name T818
Test name
Test status
Simulation time 21257232819 ps
CPU time 66.21 seconds
Started Jul 07 06:30:36 PM PDT 24
Finished Jul 07 06:31:42 PM PDT 24
Peak memory 233896 kb
Host smart-83dabac6-cfe4-452f-81e4-38e1fda8aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879098500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3879098500
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2026318280
Short name T83
Test name
Test status
Simulation time 49058295972 ps
CPU time 110.69 seconds
Started Jul 07 06:30:35 PM PDT 24
Finished Jul 07 06:32:26 PM PDT 24
Peak memory 253556 kb
Host smart-86610b2f-4ecf-4ca8-8934-63a31806b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026318280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2026318280
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1785606808
Short name T891
Test name
Test status
Simulation time 202657994 ps
CPU time 3.55 seconds
Started Jul 07 06:30:34 PM PDT 24
Finished Jul 07 06:30:38 PM PDT 24
Peak memory 233776 kb
Host smart-b407c42a-bf4b-4888-a584-62252ca7a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785606808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1785606808
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4041049805
Short name T793
Test name
Test status
Simulation time 390654776 ps
CPU time 11.94 seconds
Started Jul 07 06:30:35 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 233732 kb
Host smart-24d1607d-f72a-442a-af25-87982694f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041049805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4041049805
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1533897516
Short name T658
Test name
Test status
Simulation time 94138808 ps
CPU time 1.02 seconds
Started Jul 07 06:30:28 PM PDT 24
Finished Jul 07 06:30:30 PM PDT 24
Peak memory 218888 kb
Host smart-e4eac63f-5b32-4698-8ae6-afd2e81f8793
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533897516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1533897516
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3977585228
Short name T320
Test name
Test status
Simulation time 10248589521 ps
CPU time 11.21 seconds
Started Jul 07 06:30:33 PM PDT 24
Finished Jul 07 06:30:44 PM PDT 24
Peak memory 235720 kb
Host smart-d56de1c2-7b60-493d-91ae-ba561b8edf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977585228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3977585228
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.25429360
Short name T156
Test name
Test status
Simulation time 30730467 ps
CPU time 2.2 seconds
Started Jul 07 06:30:35 PM PDT 24
Finished Jul 07 06:30:37 PM PDT 24
Peak memory 224960 kb
Host smart-8d32bf6a-a423-4a2e-8f70-2a2523916593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25429360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.25429360
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2454740812
Short name T862
Test name
Test status
Simulation time 867142268 ps
CPU time 5.15 seconds
Started Jul 07 06:30:42 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 224168 kb
Host smart-569b3c9b-b218-472c-bf88-f00a796e7d98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454740812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2454740812
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2804178207
Short name T3
Test name
Test status
Simulation time 10565664603 ps
CPU time 9.88 seconds
Started Jul 07 06:30:35 PM PDT 24
Finished Jul 07 06:30:45 PM PDT 24
Peak memory 217476 kb
Host smart-f4855852-0ca2-440a-9834-4f16ce2b3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804178207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2804178207
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3512966225
Short name T804
Test name
Test status
Simulation time 274910445 ps
CPU time 1.48 seconds
Started Jul 07 06:30:34 PM PDT 24
Finished Jul 07 06:30:35 PM PDT 24
Peak memory 208924 kb
Host smart-fc829b04-4c0f-4e1c-ad7a-34b646279ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512966225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3512966225
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3777296458
Short name T985
Test name
Test status
Simulation time 58679056 ps
CPU time 1.61 seconds
Started Jul 07 06:30:34 PM PDT 24
Finished Jul 07 06:30:36 PM PDT 24
Peak memory 217300 kb
Host smart-2f614094-afd8-45b9-bf0b-f1d46d5d65cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777296458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3777296458
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4258897564
Short name T378
Test name
Test status
Simulation time 86163254 ps
CPU time 0.87 seconds
Started Jul 07 06:30:37 PM PDT 24
Finished Jul 07 06:30:38 PM PDT 24
Peak memory 206968 kb
Host smart-f57e42f7-e7d2-4429-8a1f-60574844b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258897564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4258897564
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1755130909
Short name T690
Test name
Test status
Simulation time 37444866573 ps
CPU time 11.3 seconds
Started Jul 07 06:30:37 PM PDT 24
Finished Jul 07 06:30:49 PM PDT 24
Peak memory 233900 kb
Host smart-8bb5ee2d-d15e-424f-bb79-4cebefde54fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755130909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1755130909
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2121917454
Short name T911
Test name
Test status
Simulation time 47732186 ps
CPU time 0.75 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:30:46 PM PDT 24
Peak memory 205820 kb
Host smart-8a21d9d2-1e22-49fd-920c-b11eef823fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121917454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2121917454
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.304108045
Short name T939
Test name
Test status
Simulation time 347094095 ps
CPU time 4.85 seconds
Started Jul 07 06:30:43 PM PDT 24
Finished Jul 07 06:30:48 PM PDT 24
Peak memory 233776 kb
Host smart-35afa4ce-ee2f-405a-bb0e-f2420a8f1aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304108045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.304108045
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3592238247
Short name T536
Test name
Test status
Simulation time 37773368 ps
CPU time 0.74 seconds
Started Jul 07 06:30:39 PM PDT 24
Finished Jul 07 06:30:40 PM PDT 24
Peak memory 206820 kb
Host smart-a5e4d9ad-d10e-4c72-af0b-03e2a8eb8511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592238247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3592238247
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1419451249
Short name T175
Test name
Test status
Simulation time 630692768 ps
CPU time 9.5 seconds
Started Jul 07 06:30:44 PM PDT 24
Finished Jul 07 06:30:54 PM PDT 24
Peak memory 241972 kb
Host smart-78ddd950-f533-46fe-a7d1-ede210b1bd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419451249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1419451249
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3427527289
Short name T319
Test name
Test status
Simulation time 7578807069 ps
CPU time 37.49 seconds
Started Jul 07 06:30:54 PM PDT 24
Finished Jul 07 06:31:32 PM PDT 24
Peak memory 254940 kb
Host smart-83ac49c9-1315-4bf9-94af-2e0fd00a3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427527289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3427527289
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2358121627
Short name T609
Test name
Test status
Simulation time 2318057017 ps
CPU time 34.36 seconds
Started Jul 07 06:30:48 PM PDT 24
Finished Jul 07 06:31:23 PM PDT 24
Peak memory 250444 kb
Host smart-fd180a6c-fe2c-4da9-b148-36141c03ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358121627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2358121627
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.640317511
Short name T574
Test name
Test status
Simulation time 231748283 ps
CPU time 3.03 seconds
Started Jul 07 06:30:43 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 225616 kb
Host smart-f1009ec5-4993-41c1-8d14-4bdff1272e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640317511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.640317511
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.457567783
Short name T578
Test name
Test status
Simulation time 34288259377 ps
CPU time 65.71 seconds
Started Jul 07 06:30:43 PM PDT 24
Finished Jul 07 06:31:49 PM PDT 24
Peak memory 254328 kb
Host smart-ba4874cc-a1b0-456e-8738-5fd04fc8686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457567783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.457567783
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.783180412
Short name T689
Test name
Test status
Simulation time 8609815426 ps
CPU time 14.86 seconds
Started Jul 07 06:30:42 PM PDT 24
Finished Jul 07 06:30:57 PM PDT 24
Peak memory 233912 kb
Host smart-47f20bce-125a-4164-b8aa-8f4e01ccdf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783180412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.783180412
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.962510469
Short name T467
Test name
Test status
Simulation time 680525215 ps
CPU time 19.48 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:31:05 PM PDT 24
Peak memory 237208 kb
Host smart-64f2c21a-31b9-43b7-964c-9587ca24334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962510469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.962510469
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1548217502
Short name T39
Test name
Test status
Simulation time 57711750 ps
CPU time 1.01 seconds
Started Jul 07 06:30:39 PM PDT 24
Finished Jul 07 06:30:41 PM PDT 24
Peak memory 217652 kb
Host smart-8a19cb78-2c86-4230-b2d6-6217eac06765
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548217502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1548217502
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4145126766
Short name T362
Test name
Test status
Simulation time 30349499 ps
CPU time 2.12 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 224064 kb
Host smart-1940e511-9eaa-4626-b4a9-7ae9a6e71d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145126766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4145126766
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.190839335
Short name T244
Test name
Test status
Simulation time 18404651555 ps
CPU time 14.78 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:31:00 PM PDT 24
Peak memory 225712 kb
Host smart-bec9c14a-3c63-4c3b-9623-339af7233360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190839335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.190839335
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.608782524
Short name T617
Test name
Test status
Simulation time 9377022873 ps
CPU time 6.89 seconds
Started Jul 07 06:30:44 PM PDT 24
Finished Jul 07 06:30:51 PM PDT 24
Peak memory 223304 kb
Host smart-db0729b2-04ba-4223-9676-d00643c6ca2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=608782524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.608782524
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1588906949
Short name T318
Test name
Test status
Simulation time 130160386144 ps
CPU time 255.4 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 255772 kb
Host smart-bd615cd2-5098-4278-b3fc-1e3c5a47bbc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588906949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1588906949
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.918808079
Short name T814
Test name
Test status
Simulation time 1917976763 ps
CPU time 3.11 seconds
Started Jul 07 06:30:40 PM PDT 24
Finished Jul 07 06:30:43 PM PDT 24
Peak memory 217400 kb
Host smart-ad786688-2184-4260-ad22-a3129b3021f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918808079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.918808079
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2118595250
Short name T815
Test name
Test status
Simulation time 413466073 ps
CPU time 2.25 seconds
Started Jul 07 06:30:37 PM PDT 24
Finished Jul 07 06:30:40 PM PDT 24
Peak memory 217116 kb
Host smart-654c643a-03e8-457a-ab05-9b72ea725f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118595250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2118595250
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.290516726
Short name T603
Test name
Test status
Simulation time 382470062 ps
CPU time 1.25 seconds
Started Jul 07 06:30:43 PM PDT 24
Finished Jul 07 06:30:45 PM PDT 24
Peak memory 208908 kb
Host smart-b9bd1181-4a07-4964-82dd-d24481b35e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290516726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.290516726
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.426206577
Short name T524
Test name
Test status
Simulation time 351215416 ps
CPU time 0.79 seconds
Started Jul 07 06:30:45 PM PDT 24
Finished Jul 07 06:30:46 PM PDT 24
Peak memory 206960 kb
Host smart-ba06e91b-9023-45d8-9be8-8fb9ac43076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426206577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.426206577
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2136837037
Short name T247
Test name
Test status
Simulation time 23167294824 ps
CPU time 23.06 seconds
Started Jul 07 06:30:57 PM PDT 24
Finished Jul 07 06:31:20 PM PDT 24
Peak memory 233952 kb
Host smart-b9da5e8d-14f6-486a-b826-f085373877f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136837037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2136837037
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.164139627
Short name T615
Test name
Test status
Simulation time 54503644 ps
CPU time 0.78 seconds
Started Jul 07 06:31:01 PM PDT 24
Finished Jul 07 06:31:02 PM PDT 24
Peak memory 205864 kb
Host smart-06155e7e-a65b-4c2c-9c2c-cd10c9427095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164139627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.164139627
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2662534808
Short name T296
Test name
Test status
Simulation time 657015938 ps
CPU time 8.76 seconds
Started Jul 07 06:30:52 PM PDT 24
Finished Jul 07 06:31:01 PM PDT 24
Peak memory 233788 kb
Host smart-7b875a63-6d55-4c39-b52b-27a63c3f7d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662534808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2662534808
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1168316783
Short name T1020
Test name
Test status
Simulation time 13671654 ps
CPU time 0.77 seconds
Started Jul 07 06:30:46 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 206832 kb
Host smart-c20d2b01-6435-4d19-a49b-b44602e337be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168316783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1168316783
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.436377259
Short name T878
Test name
Test status
Simulation time 34517470627 ps
CPU time 312.18 seconds
Started Jul 07 06:30:52 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 250532 kb
Host smart-4e70ce00-5749-47d5-ac06-2667dbfd3a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436377259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.436377259
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1154071692
Short name T747
Test name
Test status
Simulation time 18256582870 ps
CPU time 164.76 seconds
Started Jul 07 06:30:51 PM PDT 24
Finished Jul 07 06:33:36 PM PDT 24
Peak memory 253548 kb
Host smart-dab6cbf8-807b-4a39-9b8c-9a5d15a383c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154071692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1154071692
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3453996006
Short name T153
Test name
Test status
Simulation time 3310687760 ps
CPU time 13.39 seconds
Started Jul 07 06:30:50 PM PDT 24
Finished Jul 07 06:31:04 PM PDT 24
Peak memory 233860 kb
Host smart-0d0c0371-54ec-42ae-b6ba-19b1197dffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453996006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3453996006
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2077396464
Short name T625
Test name
Test status
Simulation time 1970210337 ps
CPU time 43.99 seconds
Started Jul 07 06:30:50 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 250184 kb
Host smart-e9ad39da-ab29-459b-8e83-21cb7d2a2362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077396464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2077396464
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2295890243
Short name T729
Test name
Test status
Simulation time 295334999 ps
CPU time 6.12 seconds
Started Jul 07 06:30:50 PM PDT 24
Finished Jul 07 06:30:56 PM PDT 24
Peak memory 233768 kb
Host smart-abf5b47b-6931-4201-8544-58ce3879d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295890243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2295890243
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2309182442
Short name T76
Test name
Test status
Simulation time 30223906124 ps
CPU time 51.34 seconds
Started Jul 07 06:30:53 PM PDT 24
Finished Jul 07 06:31:44 PM PDT 24
Peak memory 233844 kb
Host smart-aa570f25-c581-46bb-9d52-b5c1c34d1c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309182442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2309182442
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2872804906
Short name T489
Test name
Test status
Simulation time 40096599 ps
CPU time 1.08 seconds
Started Jul 07 06:30:46 PM PDT 24
Finished Jul 07 06:30:47 PM PDT 24
Peak memory 217616 kb
Host smart-1b6f900f-5d1a-4373-a5eb-2ec823b42fef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872804906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2872804906
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3173565284
Short name T255
Test name
Test status
Simulation time 4747279814 ps
CPU time 13.34 seconds
Started Jul 07 06:30:49 PM PDT 24
Finished Jul 07 06:31:02 PM PDT 24
Peak memory 236440 kb
Host smart-af5cb411-339c-4104-b880-8968ae615117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173565284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3173565284
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2473507443
Short name T63
Test name
Test status
Simulation time 5277485396 ps
CPU time 10.62 seconds
Started Jul 07 06:30:52 PM PDT 24
Finished Jul 07 06:31:03 PM PDT 24
Peak memory 233868 kb
Host smart-2fff0d87-9c8b-4661-a139-ab36dc243b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473507443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2473507443
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3731113283
Short name T395
Test name
Test status
Simulation time 3806567222 ps
CPU time 10.02 seconds
Started Jul 07 06:30:48 PM PDT 24
Finished Jul 07 06:30:58 PM PDT 24
Peak memory 223260 kb
Host smart-643e91db-3a3c-4745-954c-9872194038aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3731113283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3731113283
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2945176511
Short name T960
Test name
Test status
Simulation time 74482728070 ps
CPU time 196.93 seconds
Started Jul 07 06:30:51 PM PDT 24
Finished Jul 07 06:34:09 PM PDT 24
Peak memory 256252 kb
Host smart-e6c1d1b3-b10d-4efb-8c96-4dc9fda219fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945176511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2945176511
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1187491011
Short name T708
Test name
Test status
Simulation time 30144139104 ps
CPU time 43.78 seconds
Started Jul 07 06:30:46 PM PDT 24
Finished Jul 07 06:31:30 PM PDT 24
Peak memory 217472 kb
Host smart-31978f99-e673-4788-8b9d-b22b716cb7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187491011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1187491011
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2451385321
Short name T682
Test name
Test status
Simulation time 4046067112 ps
CPU time 11.04 seconds
Started Jul 07 06:30:47 PM PDT 24
Finished Jul 07 06:30:59 PM PDT 24
Peak memory 217428 kb
Host smart-6335f173-0d4d-4985-aa86-7eab712bd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451385321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2451385321
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.717048549
Short name T406
Test name
Test status
Simulation time 207246561 ps
CPU time 5.21 seconds
Started Jul 07 06:30:53 PM PDT 24
Finished Jul 07 06:30:58 PM PDT 24
Peak memory 217384 kb
Host smart-5e0b154b-82c6-4b61-b8e7-9b6f4dfca058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717048549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.717048549
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3260246295
Short name T977
Test name
Test status
Simulation time 53688620 ps
CPU time 0.83 seconds
Started Jul 07 06:30:51 PM PDT 24
Finished Jul 07 06:30:52 PM PDT 24
Peak memory 206936 kb
Host smart-b40dc19a-2235-4ca0-b763-2a675633648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260246295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3260246295
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1059178841
Short name T628
Test name
Test status
Simulation time 1431174464 ps
CPU time 2.9 seconds
Started Jul 07 06:31:05 PM PDT 24
Finished Jul 07 06:31:08 PM PDT 24
Peak memory 233832 kb
Host smart-ad4f6678-88f2-4394-a0b7-089a4a3f813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059178841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1059178841
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3112017
Short name T355
Test name
Test status
Simulation time 11090827 ps
CPU time 0.68 seconds
Started Jul 07 06:31:01 PM PDT 24
Finished Jul 07 06:31:01 PM PDT 24
Peak memory 206396 kb
Host smart-d8bd4e68-03e8-4cce-86fb-32b1dbdba3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3112017
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3471138817
Short name T519
Test name
Test status
Simulation time 917906907 ps
CPU time 9.74 seconds
Started Jul 07 06:30:57 PM PDT 24
Finished Jul 07 06:31:07 PM PDT 24
Peak memory 233748 kb
Host smart-e1cd0202-d592-44ca-95bb-e254be2467b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471138817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3471138817
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3527426919
Short name T621
Test name
Test status
Simulation time 21160994 ps
CPU time 0.79 seconds
Started Jul 07 06:30:50 PM PDT 24
Finished Jul 07 06:30:51 PM PDT 24
Peak memory 207552 kb
Host smart-b106e9f8-0900-460e-b34a-0fb8f7edb604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527426919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3527426919
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1780098943
Short name T46
Test name
Test status
Simulation time 4708483509 ps
CPU time 30.53 seconds
Started Jul 07 06:30:59 PM PDT 24
Finished Jul 07 06:31:30 PM PDT 24
Peak memory 255972 kb
Host smart-f5bf37b1-81c0-4b14-bf90-253e25ffbaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780098943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1780098943
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1100506905
Short name T763
Test name
Test status
Simulation time 25647232647 ps
CPU time 89.54 seconds
Started Jul 07 06:30:56 PM PDT 24
Finished Jul 07 06:32:26 PM PDT 24
Peak memory 257776 kb
Host smart-321cae19-bc1e-46bc-9710-298bf77ba524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100506905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1100506905
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2378093323
Short name T216
Test name
Test status
Simulation time 1961855061 ps
CPU time 17.35 seconds
Started Jul 07 06:30:57 PM PDT 24
Finished Jul 07 06:31:14 PM PDT 24
Peak memory 225560 kb
Host smart-3028415c-77cb-4075-b941-31c330d276c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378093323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2378093323
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.16521268
Short name T648
Test name
Test status
Simulation time 491560189 ps
CPU time 3.92 seconds
Started Jul 07 06:30:59 PM PDT 24
Finished Jul 07 06:31:03 PM PDT 24
Peak memory 233768 kb
Host smart-08b16b1b-6876-48c5-acf7-2608aa59aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16521268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.16521268
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.539048942
Short name T633
Test name
Test status
Simulation time 3996302055 ps
CPU time 20.04 seconds
Started Jul 07 06:30:58 PM PDT 24
Finished Jul 07 06:31:18 PM PDT 24
Peak memory 225640 kb
Host smart-2a338d1b-4e7f-4e69-a2d1-a81460019b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539048942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.539048942
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1727375641
Short name T460
Test name
Test status
Simulation time 90911885 ps
CPU time 1.02 seconds
Started Jul 07 06:30:53 PM PDT 24
Finished Jul 07 06:30:55 PM PDT 24
Peak memory 218828 kb
Host smart-2355e499-7af8-4c80-b506-39e3ff743037
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727375641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1727375641
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2864967452
Short name T922
Test name
Test status
Simulation time 5284715490 ps
CPU time 16.44 seconds
Started Jul 07 06:30:59 PM PDT 24
Finished Jul 07 06:31:15 PM PDT 24
Peak memory 233872 kb
Host smart-49bacde3-2608-4ced-acf8-6aef57236928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864967452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2864967452
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4152032798
Short name T693
Test name
Test status
Simulation time 3272399481 ps
CPU time 7.83 seconds
Started Jul 07 06:30:58 PM PDT 24
Finished Jul 07 06:31:06 PM PDT 24
Peak memory 233848 kb
Host smart-431156e7-6bba-4b9e-aba6-15038dedf071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152032798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4152032798
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.504059907
Short name T726
Test name
Test status
Simulation time 285261531 ps
CPU time 4.38 seconds
Started Jul 07 06:30:57 PM PDT 24
Finished Jul 07 06:31:02 PM PDT 24
Peak memory 224028 kb
Host smart-b55831d3-8dc3-4bdf-b0c3-ee2e01106a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=504059907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.504059907
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1054397431
Short name T535
Test name
Test status
Simulation time 872302730 ps
CPU time 7.05 seconds
Started Jul 07 06:31:01 PM PDT 24
Finished Jul 07 06:31:08 PM PDT 24
Peak memory 218676 kb
Host smart-1e026502-313f-4ebf-a515-474c84073629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054397431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1054397431
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2790269798
Short name T721
Test name
Test status
Simulation time 1657632010 ps
CPU time 18.49 seconds
Started Jul 07 06:30:55 PM PDT 24
Finished Jul 07 06:31:14 PM PDT 24
Peak memory 217632 kb
Host smart-0a20441a-bf53-4249-9c3b-fa43632e3b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790269798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2790269798
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1818343396
Short name T879
Test name
Test status
Simulation time 14402604589 ps
CPU time 14.38 seconds
Started Jul 07 06:30:53 PM PDT 24
Finished Jul 07 06:31:08 PM PDT 24
Peak memory 217436 kb
Host smart-413accb8-d192-4b0b-afa1-6cd24a7f79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818343396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1818343396
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2454506824
Short name T376
Test name
Test status
Simulation time 88955459 ps
CPU time 1.37 seconds
Started Jul 07 06:31:00 PM PDT 24
Finished Jul 07 06:31:02 PM PDT 24
Peak memory 217364 kb
Host smart-b28ed12b-dabf-4f9c-9566-e26311a5fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454506824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2454506824
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1970198138
Short name T620
Test name
Test status
Simulation time 45760631 ps
CPU time 0.82 seconds
Started Jul 07 06:30:55 PM PDT 24
Finished Jul 07 06:30:56 PM PDT 24
Peak memory 206968 kb
Host smart-6fb2c921-2791-4dab-b653-d31310faccc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970198138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1970198138
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2940164875
Short name T876
Test name
Test status
Simulation time 343567671 ps
CPU time 3.89 seconds
Started Jul 07 06:31:00 PM PDT 24
Finished Jul 07 06:31:04 PM PDT 24
Peak memory 233696 kb
Host smart-f5be5848-45d4-498f-bb9f-ba1311bf6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940164875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2940164875
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2719520340
Short name T66
Test name
Test status
Simulation time 15191104 ps
CPU time 0.76 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:31:12 PM PDT 24
Peak memory 205804 kb
Host smart-6e2fc354-0be0-4ac8-a521-74cd6fbe333b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719520340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2719520340
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1405655679
Short name T359
Test name
Test status
Simulation time 143907990 ps
CPU time 2.42 seconds
Started Jul 07 06:31:08 PM PDT 24
Finished Jul 07 06:31:10 PM PDT 24
Peak memory 233500 kb
Host smart-d1c31b40-f74e-4fae-aba2-9c624371bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405655679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1405655679
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1775095549
Short name T993
Test name
Test status
Simulation time 20415091 ps
CPU time 0.77 seconds
Started Jul 07 06:31:00 PM PDT 24
Finished Jul 07 06:31:01 PM PDT 24
Peak memory 206464 kb
Host smart-a691a18a-a174-48d4-86ac-a8e5ae29df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775095549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1775095549
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3758867075
Short name T474
Test name
Test status
Simulation time 26059684679 ps
CPU time 57.05 seconds
Started Jul 07 06:31:09 PM PDT 24
Finished Jul 07 06:32:07 PM PDT 24
Peak memory 242072 kb
Host smart-f6077d08-a1f8-491f-8e80-ebb5515b2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758867075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3758867075
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3300677718
Short name T230
Test name
Test status
Simulation time 30358881875 ps
CPU time 285.23 seconds
Started Jul 07 06:31:09 PM PDT 24
Finished Jul 07 06:35:54 PM PDT 24
Peak memory 251236 kb
Host smart-bbf89a2d-9c3c-4306-b0e8-9e7653fd9675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300677718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3300677718
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.128149298
Short name T339
Test name
Test status
Simulation time 4427479215 ps
CPU time 31.3 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:31:43 PM PDT 24
Peak memory 218952 kb
Host smart-58295e65-54ef-4317-9456-66ce2ec05584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128149298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.128149298
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.884991539
Short name T604
Test name
Test status
Simulation time 798840020 ps
CPU time 7.06 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:31:18 PM PDT 24
Peak memory 225588 kb
Host smart-b1a939c8-be2b-474b-8bfa-8ccfd8f6f719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884991539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.884991539
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3057118826
Short name T1013
Test name
Test status
Simulation time 428050210 ps
CPU time 5.32 seconds
Started Jul 07 06:31:05 PM PDT 24
Finished Jul 07 06:31:11 PM PDT 24
Peak memory 233652 kb
Host smart-d50ef8aa-2770-4a91-8e9f-9a7ace9c3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057118826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3057118826
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3617918966
Short name T847
Test name
Test status
Simulation time 952491041 ps
CPU time 13.09 seconds
Started Jul 07 06:31:05 PM PDT 24
Finished Jul 07 06:31:18 PM PDT 24
Peak memory 241848 kb
Host smart-6821b63b-fc79-4339-ba53-a5d04276d0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617918966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3617918966
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.280121952
Short name T41
Test name
Test status
Simulation time 63872506 ps
CPU time 1.09 seconds
Started Jul 07 06:31:02 PM PDT 24
Finished Jul 07 06:31:04 PM PDT 24
Peak memory 217660 kb
Host smart-d6ddd505-bcbe-4eb6-9c18-b78763ffc114
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280121952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.280121952
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2305882233
Short name T572
Test name
Test status
Simulation time 79737022 ps
CPU time 2.33 seconds
Started Jul 07 06:31:04 PM PDT 24
Finished Jul 07 06:31:06 PM PDT 24
Peak memory 225148 kb
Host smart-111e0149-102f-4e9d-80ba-d63e1715f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305882233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2305882233
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.967352653
Short name T774
Test name
Test status
Simulation time 17403172678 ps
CPU time 10.62 seconds
Started Jul 07 06:31:04 PM PDT 24
Finished Jul 07 06:31:15 PM PDT 24
Peak memory 238996 kb
Host smart-36b910b7-91d7-4e8c-b8d8-1e063555c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967352653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.967352653
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4134860776
Short name T452
Test name
Test status
Simulation time 510519488 ps
CPU time 5.67 seconds
Started Jul 07 06:31:08 PM PDT 24
Finished Jul 07 06:31:14 PM PDT 24
Peak memory 223540 kb
Host smart-86b25212-fa77-4ad7-b6dc-6abaec08eb64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4134860776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4134860776
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2079678034
Short name T30
Test name
Test status
Simulation time 158888354 ps
CPU time 0.98 seconds
Started Jul 07 06:31:09 PM PDT 24
Finished Jul 07 06:31:10 PM PDT 24
Peak memory 208400 kb
Host smart-ba80ed83-3529-48a5-b35a-09d4ebd086c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079678034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2079678034
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3805338850
Short name T898
Test name
Test status
Simulation time 1837065452 ps
CPU time 27.8 seconds
Started Jul 07 06:31:06 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 217660 kb
Host smart-37e71753-ecb8-4235-ba37-e1b3ecf48e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805338850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3805338850
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4028029045
Short name T561
Test name
Test status
Simulation time 3559136357 ps
CPU time 2.68 seconds
Started Jul 07 06:31:00 PM PDT 24
Finished Jul 07 06:31:03 PM PDT 24
Peak memory 209012 kb
Host smart-2b312a21-3c66-4847-a3bc-475f7b6b36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028029045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4028029045
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1745708718
Short name T654
Test name
Test status
Simulation time 57969161 ps
CPU time 3.15 seconds
Started Jul 07 06:31:05 PM PDT 24
Finished Jul 07 06:31:08 PM PDT 24
Peak memory 209140 kb
Host smart-36a4e069-7d02-4727-ac6e-53513f24cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745708718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1745708718
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.747436688
Short name T885
Test name
Test status
Simulation time 24459486 ps
CPU time 0.78 seconds
Started Jul 07 06:31:06 PM PDT 24
Finished Jul 07 06:31:07 PM PDT 24
Peak memory 206944 kb
Host smart-c75d3af6-da1d-4570-a668-058a9cf5cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747436688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.747436688
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.780892629
Short name T268
Test name
Test status
Simulation time 927072466 ps
CPU time 6.42 seconds
Started Jul 07 06:31:05 PM PDT 24
Finished Jul 07 06:31:12 PM PDT 24
Peak memory 233688 kb
Host smart-76f257b0-815b-4a07-93be-8f9472923b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780892629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.780892629
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2856099771
Short name T698
Test name
Test status
Simulation time 15200536 ps
CPU time 0.72 seconds
Started Jul 07 06:31:23 PM PDT 24
Finished Jul 07 06:31:24 PM PDT 24
Peak memory 206288 kb
Host smart-bf2144e6-ef9a-4027-ad56-d977de3b9422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856099771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2856099771
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1002810276
Short name T380
Test name
Test status
Simulation time 1165086201 ps
CPU time 13.33 seconds
Started Jul 07 06:31:16 PM PDT 24
Finished Jul 07 06:31:30 PM PDT 24
Peak memory 233748 kb
Host smart-229a43cc-b52a-4dfb-92ef-f471b9c49546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002810276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1002810276
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.813906135
Short name T982
Test name
Test status
Simulation time 37401530 ps
CPU time 0.81 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:31:12 PM PDT 24
Peak memory 207848 kb
Host smart-a1178424-4d7c-4490-882d-1385b60a996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813906135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.813906135
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.77473337
Short name T249
Test name
Test status
Simulation time 1453946662 ps
CPU time 26.25 seconds
Started Jul 07 06:31:19 PM PDT 24
Finished Jul 07 06:31:45 PM PDT 24
Peak memory 242004 kb
Host smart-a2252770-ed47-4ec3-9270-b33fec5de4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77473337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.77473337
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.849009874
Short name T997
Test name
Test status
Simulation time 122732245688 ps
CPU time 305.31 seconds
Started Jul 07 06:31:21 PM PDT 24
Finished Jul 07 06:36:27 PM PDT 24
Peak memory 262084 kb
Host smart-188057e9-1137-465c-8a45-da921640a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849009874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.849009874
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3415056363
Short name T390
Test name
Test status
Simulation time 5165142390 ps
CPU time 40.11 seconds
Started Jul 07 06:31:16 PM PDT 24
Finished Jul 07 06:31:56 PM PDT 24
Peak memory 238512 kb
Host smart-e869a1e8-56ae-45e4-aafe-64edda9286da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415056363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3415056363
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2040396452
Short name T914
Test name
Test status
Simulation time 3530617691 ps
CPU time 27.24 seconds
Started Jul 07 06:31:12 PM PDT 24
Finished Jul 07 06:31:39 PM PDT 24
Peak memory 225596 kb
Host smart-d1360ea7-042b-4006-ad37-1573b0cc287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040396452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2040396452
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1911159259
Short name T107
Test name
Test status
Simulation time 1756399596 ps
CPU time 21.67 seconds
Started Jul 07 06:31:13 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 233724 kb
Host smart-c0f831e0-939d-4e66-a38a-d9c901730fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911159259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1911159259
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2414728700
Short name T447
Test name
Test status
Simulation time 86016766 ps
CPU time 1.05 seconds
Started Jul 07 06:31:14 PM PDT 24
Finished Jul 07 06:31:15 PM PDT 24
Peak memory 218896 kb
Host smart-d4f8eac4-0740-4079-afd6-a5329eab0230
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414728700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2414728700
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.849715076
Short name T291
Test name
Test status
Simulation time 616475256 ps
CPU time 3.35 seconds
Started Jul 07 06:31:13 PM PDT 24
Finished Jul 07 06:31:17 PM PDT 24
Peak memory 225572 kb
Host smart-1f0f0682-93ed-4541-8bfc-ce2ecf9e7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849715076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.849715076
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.834303554
Short name T832
Test name
Test status
Simulation time 250691239 ps
CPU time 2.65 seconds
Started Jul 07 06:31:13 PM PDT 24
Finished Jul 07 06:31:16 PM PDT 24
Peak memory 225484 kb
Host smart-39ae9f21-7cdd-4049-b4ed-d315e523f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834303554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.834303554
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2223782963
Short name T419
Test name
Test status
Simulation time 302840436 ps
CPU time 5.04 seconds
Started Jul 07 06:31:18 PM PDT 24
Finished Jul 07 06:31:24 PM PDT 24
Peak memory 221500 kb
Host smart-7966e955-005a-41ba-876d-9038cba1da91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2223782963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2223782963
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2604561903
Short name T306
Test name
Test status
Simulation time 381701882035 ps
CPU time 911.56 seconds
Started Jul 07 06:31:18 PM PDT 24
Finished Jul 07 06:46:30 PM PDT 24
Peak memory 290700 kb
Host smart-2e3cfa94-9f70-4463-b5c1-ff3d43c4cbd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604561903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2604561903
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2956092608
Short name T27
Test name
Test status
Simulation time 1844182414 ps
CPU time 10.95 seconds
Started Jul 07 06:31:11 PM PDT 24
Finished Jul 07 06:31:22 PM PDT 24
Peak memory 217616 kb
Host smart-049779f0-1ffe-48b6-aee9-996c7fa02e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956092608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2956092608
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1005152061
Short name T564
Test name
Test status
Simulation time 1679102041 ps
CPU time 7.07 seconds
Started Jul 07 06:31:15 PM PDT 24
Finished Jul 07 06:31:22 PM PDT 24
Peak memory 217332 kb
Host smart-d4170240-f63a-457d-9db4-d36cd44df625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005152061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1005152061
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3403848042
Short name T353
Test name
Test status
Simulation time 35878381 ps
CPU time 0.68 seconds
Started Jul 07 06:31:13 PM PDT 24
Finished Jul 07 06:31:14 PM PDT 24
Peak memory 206912 kb
Host smart-8bc64fd7-2660-48fa-8303-feff58581603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403848042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3403848042
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.864719249
Short name T516
Test name
Test status
Simulation time 38089811 ps
CPU time 0.69 seconds
Started Jul 07 06:31:13 PM PDT 24
Finished Jul 07 06:31:14 PM PDT 24
Peak memory 206404 kb
Host smart-e4c50f7d-cea9-4b52-afb8-6be164a04899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864719249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.864719249
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2736979400
Short name T886
Test name
Test status
Simulation time 10527937794 ps
CPU time 11.58 seconds
Started Jul 07 06:31:12 PM PDT 24
Finished Jul 07 06:31:24 PM PDT 24
Peak memory 241780 kb
Host smart-a75b6d72-0c59-4029-acc5-cf92bb9e7814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736979400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2736979400
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1765121247
Short name T780
Test name
Test status
Simulation time 12596345 ps
CPU time 0.72 seconds
Started Jul 07 06:31:27 PM PDT 24
Finished Jul 07 06:31:28 PM PDT 24
Peak memory 206340 kb
Host smart-ce4f99d8-0292-4c91-ba62-1239030ca388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765121247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1765121247
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1166176647
Short name T787
Test name
Test status
Simulation time 6519883534 ps
CPU time 27.6 seconds
Started Jul 07 06:31:25 PM PDT 24
Finished Jul 07 06:31:52 PM PDT 24
Peak memory 225700 kb
Host smart-26e575d5-f12c-42c0-9767-00d5bd8cce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166176647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1166176647
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3276873977
Short name T64
Test name
Test status
Simulation time 26265197 ps
CPU time 0.74 seconds
Started Jul 07 06:31:20 PM PDT 24
Finished Jul 07 06:31:21 PM PDT 24
Peak memory 207512 kb
Host smart-8dbe3ec1-895c-404a-ad2d-2ac58797c5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276873977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3276873977
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.575529854
Short name T842
Test name
Test status
Simulation time 14791476379 ps
CPU time 59.73 seconds
Started Jul 07 06:31:29 PM PDT 24
Finished Jul 07 06:32:29 PM PDT 24
Peak memory 255736 kb
Host smart-5d34ea98-d660-4d06-8c1b-f99e72215e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575529854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.575529854
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1476121122
Short name T786
Test name
Test status
Simulation time 9821461286 ps
CPU time 46.89 seconds
Started Jul 07 06:31:28 PM PDT 24
Finished Jul 07 06:32:15 PM PDT 24
Peak memory 239748 kb
Host smart-3d2ff4f8-1b0f-40cb-adac-ab6bca2c5db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476121122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1476121122
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.523477599
Short name T336
Test name
Test status
Simulation time 3613437571 ps
CPU time 23.68 seconds
Started Jul 07 06:31:23 PM PDT 24
Finished Jul 07 06:31:47 PM PDT 24
Peak memory 234496 kb
Host smart-d428b15e-7573-4055-9cb4-b7498ed1f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523477599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.523477599
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3552634382
Short name T1026
Test name
Test status
Simulation time 172509481 ps
CPU time 3.59 seconds
Started Jul 07 06:31:25 PM PDT 24
Finished Jul 07 06:31:28 PM PDT 24
Peak memory 225528 kb
Host smart-658ed4de-71e8-436d-aadf-affa674f59c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552634382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3552634382
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3881291306
Short name T275
Test name
Test status
Simulation time 936962539 ps
CPU time 6.05 seconds
Started Jul 07 06:31:26 PM PDT 24
Finished Jul 07 06:31:32 PM PDT 24
Peak memory 233764 kb
Host smart-83702cf0-ba1a-438c-bfb9-6490068b6d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881291306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3881291306
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.672095541
Short name T588
Test name
Test status
Simulation time 51488585 ps
CPU time 1.01 seconds
Started Jul 07 06:31:19 PM PDT 24
Finished Jul 07 06:31:20 PM PDT 24
Peak memory 217640 kb
Host smart-dbe3d940-27fb-4b73-bf1d-a2f209cc2052
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672095541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.672095541
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3957922741
Short name T554
Test name
Test status
Simulation time 34524151 ps
CPU time 2.5 seconds
Started Jul 07 06:31:18 PM PDT 24
Finished Jul 07 06:31:21 PM PDT 24
Peak memory 233452 kb
Host smart-ca228ba5-cbf3-4be0-9ba7-43db708a183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957922741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3957922741
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3794834907
Short name T602
Test name
Test status
Simulation time 24986233300 ps
CPU time 19.27 seconds
Started Jul 07 06:31:22 PM PDT 24
Finished Jul 07 06:31:41 PM PDT 24
Peak memory 233948 kb
Host smart-654274d8-8518-48e8-9d3a-4353a6f6ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794834907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3794834907
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2918537807
Short name T816
Test name
Test status
Simulation time 515219921 ps
CPU time 6.13 seconds
Started Jul 07 06:31:28 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 222668 kb
Host smart-aedc726d-239b-4914-8756-d6ab63fad6f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2918537807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2918537807
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2064335135
Short name T740
Test name
Test status
Simulation time 5769455002 ps
CPU time 90.63 seconds
Started Jul 07 06:31:25 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 250448 kb
Host smart-11eeeed6-a7ae-4ee7-bbcd-1d3c10f13592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064335135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2064335135
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2790013146
Short name T990
Test name
Test status
Simulation time 6066029492 ps
CPU time 15.63 seconds
Started Jul 07 06:31:20 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 217480 kb
Host smart-561193c3-e8e3-4332-91d8-0c1d6df90036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790013146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2790013146
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3154389208
Short name T869
Test name
Test status
Simulation time 1223551856 ps
CPU time 2.52 seconds
Started Jul 07 06:31:23 PM PDT 24
Finished Jul 07 06:31:26 PM PDT 24
Peak memory 217312 kb
Host smart-8ac51bd8-d8b2-4cec-9c67-2683d5e0757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154389208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3154389208
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1381591737
Short name T629
Test name
Test status
Simulation time 163419590 ps
CPU time 0.94 seconds
Started Jul 07 06:31:20 PM PDT 24
Finished Jul 07 06:31:21 PM PDT 24
Peak memory 208000 kb
Host smart-416d3b7f-7042-4dfd-a3a5-e9e8d88be139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381591737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1381591737
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3441782037
Short name T515
Test name
Test status
Simulation time 5814727921 ps
CPU time 19.51 seconds
Started Jul 07 06:31:25 PM PDT 24
Finished Jul 07 06:31:44 PM PDT 24
Peak memory 250280 kb
Host smart-6cb73027-4b3c-45e8-84cb-e10df2d6c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441782037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3441782037
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1997028539
Short name T393
Test name
Test status
Simulation time 29904623 ps
CPU time 0.72 seconds
Started Jul 07 06:31:34 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 206736 kb
Host smart-521738aa-6150-4335-8679-171d0ee66b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997028539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1997028539
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1718445306
Short name T454
Test name
Test status
Simulation time 107671214 ps
CPU time 2.71 seconds
Started Jul 07 06:31:34 PM PDT 24
Finished Jul 07 06:31:37 PM PDT 24
Peak memory 233788 kb
Host smart-587dc0b9-cd3f-4c38-9a0f-a0b1c6d793d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718445306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1718445306
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3502809336
Short name T927
Test name
Test status
Simulation time 148569756 ps
CPU time 0.74 seconds
Started Jul 07 06:31:33 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 207504 kb
Host smart-aba0dd9f-d840-4a2a-b5ff-c897c2d2024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502809336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3502809336
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2929218252
Short name T537
Test name
Test status
Simulation time 487438835 ps
CPU time 6.56 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:45 PM PDT 24
Peak memory 221812 kb
Host smart-5458814d-964d-4662-8f8e-60dc312d6799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929218252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2929218252
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1025096699
Short name T584
Test name
Test status
Simulation time 30393954740 ps
CPU time 105.49 seconds
Started Jul 07 06:31:37 PM PDT 24
Finished Jul 07 06:33:23 PM PDT 24
Peak memory 254072 kb
Host smart-7cb030b3-9ad6-42de-b86b-9e386ca274cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025096699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1025096699
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2400472632
Short name T531
Test name
Test status
Simulation time 30011435534 ps
CPU time 305.8 seconds
Started Jul 07 06:31:36 PM PDT 24
Finished Jul 07 06:36:43 PM PDT 24
Peak memory 258556 kb
Host smart-ed4f68d4-6f3d-4b21-bd48-95190c7d7c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400472632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2400472632
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1641347305
Short name T530
Test name
Test status
Simulation time 12184343887 ps
CPU time 80.89 seconds
Started Jul 07 06:31:42 PM PDT 24
Finished Jul 07 06:33:03 PM PDT 24
Peak memory 250308 kb
Host smart-1d0a0c08-114c-4bf9-b864-c3b6deb2ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641347305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1641347305
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3726092047
Short name T525
Test name
Test status
Simulation time 1259258725 ps
CPU time 8.57 seconds
Started Jul 07 06:31:34 PM PDT 24
Finished Jul 07 06:31:43 PM PDT 24
Peak memory 225504 kb
Host smart-fbf7c6fb-f458-4873-a0c8-f948ccebf3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726092047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3726092047
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.871794047
Short name T642
Test name
Test status
Simulation time 6791350887 ps
CPU time 38.74 seconds
Started Jul 07 06:31:36 PM PDT 24
Finished Jul 07 06:32:15 PM PDT 24
Peak memory 233900 kb
Host smart-a2999e7a-7f23-446d-be62-c9c8b6643cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871794047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.871794047
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3957324929
Short name T377
Test name
Test status
Simulation time 28461456 ps
CPU time 1.01 seconds
Started Jul 07 06:31:33 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 217664 kb
Host smart-8ec888d7-b5e8-438c-929d-6aa73490719f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957324929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3957324929
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.541192957
Short name T569
Test name
Test status
Simulation time 7121005797 ps
CPU time 5.74 seconds
Started Jul 07 06:31:37 PM PDT 24
Finished Jul 07 06:31:43 PM PDT 24
Peak memory 225628 kb
Host smart-6a1fc726-0916-4bf3-a59d-f20e0d7027bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541192957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.541192957
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.775876861
Short name T510
Test name
Test status
Simulation time 8897562846 ps
CPU time 11.18 seconds
Started Jul 07 06:31:32 PM PDT 24
Finished Jul 07 06:31:44 PM PDT 24
Peak memory 233840 kb
Host smart-b98f1bab-e0a0-4a47-b55a-47b42a44ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775876861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.775876861
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3977222233
Short name T539
Test name
Test status
Simulation time 3319414436 ps
CPU time 7.59 seconds
Started Jul 07 06:31:34 PM PDT 24
Finished Jul 07 06:31:42 PM PDT 24
Peak memory 221880 kb
Host smart-343b86ed-6588-4b46-b3af-59447d357589
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977222233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3977222233
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.641876719
Short name T38
Test name
Test status
Simulation time 55235398445 ps
CPU time 144.68 seconds
Started Jul 07 06:31:40 PM PDT 24
Finished Jul 07 06:34:05 PM PDT 24
Peak memory 265528 kb
Host smart-a7515708-fff3-4a88-ae41-a9295422e959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641876719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.641876719
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2247040803
Short name T538
Test name
Test status
Simulation time 1124683970 ps
CPU time 4.48 seconds
Started Jul 07 06:31:31 PM PDT 24
Finished Jul 07 06:31:36 PM PDT 24
Peak memory 217392 kb
Host smart-306a7704-4d24-4129-980e-a7086897e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247040803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2247040803
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.326035857
Short name T450
Test name
Test status
Simulation time 241077340 ps
CPU time 1.24 seconds
Started Jul 07 06:31:32 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 208748 kb
Host smart-4359e3df-39e0-469c-946a-2db2ead66d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326035857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.326035857
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2152599325
Short name T802
Test name
Test status
Simulation time 241313859 ps
CPU time 5.36 seconds
Started Jul 07 06:31:30 PM PDT 24
Finished Jul 07 06:31:36 PM PDT 24
Peak memory 217388 kb
Host smart-ddeb4c54-b3e1-492e-a40d-a682e24bb30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152599325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2152599325
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3438502805
Short name T570
Test name
Test status
Simulation time 183544877 ps
CPU time 0.95 seconds
Started Jul 07 06:31:32 PM PDT 24
Finished Jul 07 06:31:34 PM PDT 24
Peak memory 207996 kb
Host smart-ef998f6a-2de2-4abc-b99a-a03de11f3a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438502805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3438502805
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.928692266
Short name T449
Test name
Test status
Simulation time 2767790740 ps
CPU time 13.81 seconds
Started Jul 07 06:31:34 PM PDT 24
Finished Jul 07 06:31:48 PM PDT 24
Peak memory 233876 kb
Host smart-e42316c5-5666-45f1-97c3-ffeb4273b336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928692266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.928692266
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4198347961
Short name T392
Test name
Test status
Simulation time 46617819 ps
CPU time 0.69 seconds
Started Jul 07 06:29:08 PM PDT 24
Finished Jul 07 06:29:09 PM PDT 24
Peak memory 205816 kb
Host smart-66376310-420c-46b8-ac8b-e95a40adce70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198347961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
198347961
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.728965139
Short name T902
Test name
Test status
Simulation time 128432268 ps
CPU time 3.38 seconds
Started Jul 07 06:29:02 PM PDT 24
Finished Jul 07 06:29:06 PM PDT 24
Peak memory 225580 kb
Host smart-ad6884aa-b746-4d48-8ffa-6bb35261b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728965139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.728965139
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2971514467
Short name T640
Test name
Test status
Simulation time 20132223 ps
CPU time 0.78 seconds
Started Jul 07 06:28:56 PM PDT 24
Finished Jul 07 06:28:57 PM PDT 24
Peak memory 207472 kb
Host smart-b5238984-4170-4a9d-bf03-dfba6ea2a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971514467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2971514467
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.699932450
Short name T692
Test name
Test status
Simulation time 43465413 ps
CPU time 0.78 seconds
Started Jul 07 06:29:09 PM PDT 24
Finished Jul 07 06:29:10 PM PDT 24
Peak memory 216924 kb
Host smart-5cfb30d4-a632-43fe-9d7f-2e07c6b00eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699932450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.699932450
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2092208496
Short name T994
Test name
Test status
Simulation time 35702621970 ps
CPU time 371.17 seconds
Started Jul 07 06:29:11 PM PDT 24
Finished Jul 07 06:35:22 PM PDT 24
Peak memory 273220 kb
Host smart-ddd7031c-f55a-4de6-be72-163788238df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092208496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2092208496
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4151118836
Short name T1027
Test name
Test status
Simulation time 5095907810 ps
CPU time 29.59 seconds
Started Jul 07 06:29:10 PM PDT 24
Finished Jul 07 06:29:40 PM PDT 24
Peak memory 238720 kb
Host smart-29ce07a0-97f4-4bc5-a28c-4a426d432049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151118836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4151118836
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1540402893
Short name T850
Test name
Test status
Simulation time 5079923348 ps
CPU time 44.1 seconds
Started Jul 07 06:29:00 PM PDT 24
Finished Jul 07 06:29:45 PM PDT 24
Peak memory 225648 kb
Host smart-9bf444fb-63b9-450f-bbaf-dcab2dc4af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540402893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1540402893
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1572737576
Short name T844
Test name
Test status
Simulation time 211180163 ps
CPU time 4.55 seconds
Started Jul 07 06:29:01 PM PDT 24
Finished Jul 07 06:29:06 PM PDT 24
Peak memory 225508 kb
Host smart-07d9b405-71bc-40eb-9e85-ed9a8ea24a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572737576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1572737576
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.814262641
Short name T403
Test name
Test status
Simulation time 6692785620 ps
CPU time 9.53 seconds
Started Jul 07 06:29:03 PM PDT 24
Finished Jul 07 06:29:13 PM PDT 24
Peak memory 233904 kb
Host smart-76e7ad8d-5572-42ba-a114-9a668f749655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814262641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.814262641
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1345400465
Short name T575
Test name
Test status
Simulation time 120890974 ps
CPU time 1.17 seconds
Started Jul 07 06:29:00 PM PDT 24
Finished Jul 07 06:29:01 PM PDT 24
Peak memory 217640 kb
Host smart-581f1ca0-8682-47e1-a541-5d3c299f5019
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345400465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1345400465
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3462186195
Short name T771
Test name
Test status
Simulation time 37221323 ps
CPU time 2.53 seconds
Started Jul 07 06:29:02 PM PDT 24
Finished Jul 07 06:29:05 PM PDT 24
Peak memory 233716 kb
Host smart-8e534712-979f-4254-b200-ed21f070b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462186195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3462186195
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3439804078
Short name T98
Test name
Test status
Simulation time 16199068557 ps
CPU time 16.04 seconds
Started Jul 07 06:29:02 PM PDT 24
Finished Jul 07 06:29:18 PM PDT 24
Peak memory 241324 kb
Host smart-c0caf11f-8dd7-47d3-bea3-7fdbe422b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439804078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3439804078
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1844123260
Short name T730
Test name
Test status
Simulation time 658680912 ps
CPU time 5.16 seconds
Started Jul 07 06:29:05 PM PDT 24
Finished Jul 07 06:29:11 PM PDT 24
Peak memory 221116 kb
Host smart-3e35eaf9-85b3-44ac-a39b-5b0564add2c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844123260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1844123260
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2346041597
Short name T72
Test name
Test status
Simulation time 87235195 ps
CPU time 1.13 seconds
Started Jul 07 06:29:10 PM PDT 24
Finished Jul 07 06:29:12 PM PDT 24
Peak memory 236320 kb
Host smart-80fb301f-2588-40dc-b39d-855e8b72dc8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346041597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2346041597
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2114962886
Short name T180
Test name
Test status
Simulation time 33361859 ps
CPU time 0.93 seconds
Started Jul 07 06:29:10 PM PDT 24
Finished Jul 07 06:29:11 PM PDT 24
Peak memory 207888 kb
Host smart-4dad5693-6b6b-4c73-92a3-9357a96aaa01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114962886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2114962886
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.104079953
Short name T935
Test name
Test status
Simulation time 4836774925 ps
CPU time 8.39 seconds
Started Jul 07 06:28:59 PM PDT 24
Finished Jul 07 06:29:08 PM PDT 24
Peak memory 217492 kb
Host smart-030dd3b4-923f-4ad2-896a-147e79734dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104079953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.104079953
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2902798709
Short name T1011
Test name
Test status
Simulation time 2583194667 ps
CPU time 4.01 seconds
Started Jul 07 06:28:58 PM PDT 24
Finished Jul 07 06:29:02 PM PDT 24
Peak memory 217392 kb
Host smart-3c8bba7c-dd99-438b-a85c-3db4d908f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902798709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2902798709
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1514337050
Short name T8
Test name
Test status
Simulation time 165582928 ps
CPU time 2.41 seconds
Started Jul 07 06:29:02 PM PDT 24
Finished Jul 07 06:29:05 PM PDT 24
Peak memory 217660 kb
Host smart-f45ac76e-a9c5-4683-9b42-be445866f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514337050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1514337050
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.555285067
Short name T909
Test name
Test status
Simulation time 31352874 ps
CPU time 0.77 seconds
Started Jul 07 06:28:58 PM PDT 24
Finished Jul 07 06:28:59 PM PDT 24
Peak memory 206964 kb
Host smart-3bcd02c8-5b17-4549-accb-f1d598be04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555285067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.555285067
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3740004553
Short name T883
Test name
Test status
Simulation time 250222485 ps
CPU time 3.19 seconds
Started Jul 07 06:29:02 PM PDT 24
Finished Jul 07 06:29:05 PM PDT 24
Peak memory 233728 kb
Host smart-bb8dc623-cabf-42cd-bac2-c136ad5d76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740004553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3740004553
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.409152225
Short name T845
Test name
Test status
Simulation time 58205553 ps
CPU time 0.74 seconds
Started Jul 07 06:31:47 PM PDT 24
Finished Jul 07 06:31:48 PM PDT 24
Peak memory 205820 kb
Host smart-55855dd8-7213-4d9e-ad7f-c42a9430003b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409152225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.409152225
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3969429928
Short name T301
Test name
Test status
Simulation time 39025348 ps
CPU time 2.61 seconds
Started Jul 07 06:31:39 PM PDT 24
Finished Jul 07 06:31:42 PM PDT 24
Peak memory 233768 kb
Host smart-8b403f5b-8c71-4d15-8458-de958ba805f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969429928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3969429928
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2959357101
Short name T396
Test name
Test status
Simulation time 19867056 ps
CPU time 0.79 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:40 PM PDT 24
Peak memory 207520 kb
Host smart-63ab9d56-b82b-420d-8cad-45b5c1969e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959357101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2959357101
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2717394649
Short name T541
Test name
Test status
Simulation time 6318065978 ps
CPU time 15.39 seconds
Started Jul 07 06:31:43 PM PDT 24
Finished Jul 07 06:31:59 PM PDT 24
Peak memory 236224 kb
Host smart-544ebedb-3b65-41df-a2e2-07ee42431576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717394649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2717394649
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.771375141
Short name T308
Test name
Test status
Simulation time 15346404075 ps
CPU time 186.91 seconds
Started Jul 07 06:31:43 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 256376 kb
Host smart-03d7dca5-e83e-457b-94e0-6ac844fb6ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771375141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.771375141
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2002038124
Short name T873
Test name
Test status
Simulation time 218839010534 ps
CPU time 158.13 seconds
Started Jul 07 06:31:45 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 257476 kb
Host smart-49a78696-fcf3-4235-a8f3-6a9ae9f4a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002038124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2002038124
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4152802809
Short name T330
Test name
Test status
Simulation time 768053782 ps
CPU time 13.63 seconds
Started Jul 07 06:31:43 PM PDT 24
Finished Jul 07 06:31:57 PM PDT 24
Peak memory 235600 kb
Host smart-b4d7906e-61cb-4a81-9009-b75041af2c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152802809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4152802809
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.995196145
Short name T1016
Test name
Test status
Simulation time 3375994878 ps
CPU time 87.91 seconds
Started Jul 07 06:31:42 PM PDT 24
Finished Jul 07 06:33:10 PM PDT 24
Peak memory 258420 kb
Host smart-e1b77b24-0de3-43a2-876b-61186666be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995196145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.995196145
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2314470318
Short name T298
Test name
Test status
Simulation time 2528632980 ps
CPU time 10.36 seconds
Started Jul 07 06:31:41 PM PDT 24
Finished Jul 07 06:31:51 PM PDT 24
Peak memory 233840 kb
Host smart-2b6bc79d-5709-48b8-9655-10c27e675f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314470318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2314470318
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.499785941
Short name T417
Test name
Test status
Simulation time 93355079 ps
CPU time 2.4 seconds
Started Jul 07 06:31:42 PM PDT 24
Finished Jul 07 06:31:44 PM PDT 24
Peak memory 233520 kb
Host smart-28de2677-af21-4533-821c-97ab299c6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499785941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.499785941
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1484030869
Short name T694
Test name
Test status
Simulation time 28711803313 ps
CPU time 10.26 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:49 PM PDT 24
Peak memory 233836 kb
Host smart-77ca2c6a-5cd2-45ee-bb7a-f288916f86f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484030869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1484030869
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1216192354
Short name T157
Test name
Test status
Simulation time 219184601 ps
CPU time 2.55 seconds
Started Jul 07 06:31:39 PM PDT 24
Finished Jul 07 06:31:42 PM PDT 24
Peak memory 225564 kb
Host smart-ee90c874-a07a-47ac-823e-8aa1058f936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216192354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1216192354
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2545326517
Short name T407
Test name
Test status
Simulation time 2712008258 ps
CPU time 7.57 seconds
Started Jul 07 06:31:42 PM PDT 24
Finished Jul 07 06:31:50 PM PDT 24
Peak memory 224236 kb
Host smart-f74229f8-a637-43ec-8c7c-fe8a86420652
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545326517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2545326517
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3085535497
Short name T29
Test name
Test status
Simulation time 518368008 ps
CPU time 1.28 seconds
Started Jul 07 06:31:47 PM PDT 24
Finished Jul 07 06:31:48 PM PDT 24
Peak memory 208768 kb
Host smart-87b9c025-0464-46a2-9da5-144498de0632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085535497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3085535497
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.131334466
Short name T656
Test name
Test status
Simulation time 2577745264 ps
CPU time 23.03 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:32:01 PM PDT 24
Peak memory 217788 kb
Host smart-95a63dd2-2b32-4940-8b97-efb6c841fb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131334466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.131334466
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.34304136
Short name T58
Test name
Test status
Simulation time 4094202018 ps
CPU time 11.77 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:50 PM PDT 24
Peak memory 217392 kb
Host smart-6385bfff-f19a-4c00-aa70-04ff7002fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34304136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.34304136
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4193413633
Short name T781
Test name
Test status
Simulation time 171833009 ps
CPU time 0.88 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:39 PM PDT 24
Peak memory 208912 kb
Host smart-b15b27de-4aa9-40ec-a253-dc96dc305aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193413633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4193413633
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3573995632
Short name T137
Test name
Test status
Simulation time 30921419 ps
CPU time 0.88 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:40 PM PDT 24
Peak memory 208016 kb
Host smart-760e2d3f-9231-4a30-8719-977a378d1746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573995632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3573995632
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1154666733
Short name T305
Test name
Test status
Simulation time 2715297932 ps
CPU time 10.36 seconds
Started Jul 07 06:31:38 PM PDT 24
Finished Jul 07 06:31:49 PM PDT 24
Peak memory 233816 kb
Host smart-2620c67e-deb1-4804-9b1a-6fef716bc549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154666733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1154666733
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1490216303
Short name T714
Test name
Test status
Simulation time 4246674043 ps
CPU time 5.16 seconds
Started Jul 07 06:31:49 PM PDT 24
Finished Jul 07 06:31:54 PM PDT 24
Peak memory 233876 kb
Host smart-1a53c862-20dc-4439-8c11-66939794d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490216303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1490216303
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2206188973
Short name T556
Test name
Test status
Simulation time 69759830 ps
CPU time 0.84 seconds
Started Jul 07 06:31:47 PM PDT 24
Finished Jul 07 06:31:48 PM PDT 24
Peak memory 207508 kb
Host smart-c522dbf4-24f7-4a53-acca-325ba45dfd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206188973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2206188973
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1058684494
Short name T595
Test name
Test status
Simulation time 36424877 ps
CPU time 0.75 seconds
Started Jul 07 06:31:51 PM PDT 24
Finished Jul 07 06:31:52 PM PDT 24
Peak memory 216900 kb
Host smart-74c2b5cc-d37a-4ad9-8089-a9bdde5c23fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058684494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1058684494
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2493889294
Short name T700
Test name
Test status
Simulation time 6392838877 ps
CPU time 34.3 seconds
Started Jul 07 06:31:49 PM PDT 24
Finished Jul 07 06:32:24 PM PDT 24
Peak memory 234000 kb
Host smart-a9aeffea-dc17-49a7-aa3f-b8bdcb59ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493889294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2493889294
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2108583927
Short name T871
Test name
Test status
Simulation time 6507170603 ps
CPU time 16.26 seconds
Started Jul 07 06:31:52 PM PDT 24
Finished Jul 07 06:32:09 PM PDT 24
Peak memory 218880 kb
Host smart-4fb4168c-fd7d-4e87-8063-273512c6be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108583927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2108583927
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.805800386
Short name T514
Test name
Test status
Simulation time 2618728277 ps
CPU time 24.25 seconds
Started Jul 07 06:31:48 PM PDT 24
Finished Jul 07 06:32:13 PM PDT 24
Peak memory 233896 kb
Host smart-86f40342-2739-4348-ae40-71aee126a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805800386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.805800386
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1591615269
Short name T1015
Test name
Test status
Simulation time 10953032 ps
CPU time 0.72 seconds
Started Jul 07 06:31:49 PM PDT 24
Finished Jul 07 06:31:50 PM PDT 24
Peak memory 216916 kb
Host smart-6cd73aaa-88c5-4b57-bc42-5411b8e4f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591615269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1591615269
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1986475426
Short name T271
Test name
Test status
Simulation time 3716356791 ps
CPU time 20.25 seconds
Started Jul 07 06:31:48 PM PDT 24
Finished Jul 07 06:32:09 PM PDT 24
Peak memory 233840 kb
Host smart-20734521-c1e6-4d08-a4a1-7fafc372f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986475426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1986475426
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4017432123
Short name T754
Test name
Test status
Simulation time 141689038 ps
CPU time 2.31 seconds
Started Jul 07 06:31:44 PM PDT 24
Finished Jul 07 06:31:47 PM PDT 24
Peak memory 228192 kb
Host smart-2f2cea5b-0a10-46fa-a9cc-6d257ef90fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017432123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4017432123
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.155798246
Short name T971
Test name
Test status
Simulation time 1685273214 ps
CPU time 4.14 seconds
Started Jul 07 06:31:45 PM PDT 24
Finished Jul 07 06:31:49 PM PDT 24
Peak memory 225556 kb
Host smart-db7c2b93-c9ba-4ea8-9197-c756b1c42977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155798246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.155798246
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.142552929
Short name T139
Test name
Test status
Simulation time 1599336270 ps
CPU time 9.57 seconds
Started Jul 07 06:31:46 PM PDT 24
Finished Jul 07 06:31:55 PM PDT 24
Peak memory 241808 kb
Host smart-15cb65ea-e41e-43b6-ba2f-c36583f9fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142552929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.142552929
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1323309617
Short name T795
Test name
Test status
Simulation time 2925211244 ps
CPU time 15.69 seconds
Started Jul 07 06:31:48 PM PDT 24
Finished Jul 07 06:32:05 PM PDT 24
Peak memory 223180 kb
Host smart-a0c6de68-e55f-46da-b0eb-ebfc629b9f15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1323309617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1323309617
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.260104553
Short name T19
Test name
Test status
Simulation time 249630656 ps
CPU time 1.11 seconds
Started Jul 07 06:31:51 PM PDT 24
Finished Jul 07 06:31:52 PM PDT 24
Peak memory 207892 kb
Host smart-151b35b8-9825-439c-884b-53b1fed8572f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260104553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.260104553
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2658141996
Short name T346
Test name
Test status
Simulation time 6507733822 ps
CPU time 18.09 seconds
Started Jul 07 06:31:46 PM PDT 24
Finished Jul 07 06:32:05 PM PDT 24
Peak memory 217504 kb
Host smart-ab06ab5f-57f1-4504-bd24-97718fa130fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658141996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2658141996
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2262330775
Short name T910
Test name
Test status
Simulation time 1629789954 ps
CPU time 8.91 seconds
Started Jul 07 06:31:46 PM PDT 24
Finished Jul 07 06:31:55 PM PDT 24
Peak memory 217324 kb
Host smart-17c05f3f-3f06-4d64-8321-b35e7818fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262330775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2262330775
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1348075142
Short name T547
Test name
Test status
Simulation time 122946546 ps
CPU time 4.72 seconds
Started Jul 07 06:31:45 PM PDT 24
Finished Jul 07 06:31:50 PM PDT 24
Peak memory 217332 kb
Host smart-1d3af78e-a05f-45d1-9568-b98bd6132c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348075142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1348075142
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.350008839
Short name T400
Test name
Test status
Simulation time 17073569 ps
CPU time 0.69 seconds
Started Jul 07 06:31:48 PM PDT 24
Finished Jul 07 06:31:49 PM PDT 24
Peak memory 206552 kb
Host smart-c82e45df-834f-4176-91fe-6e655863ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350008839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.350008839
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3583079137
Short name T779
Test name
Test status
Simulation time 9083939971 ps
CPU time 32.7 seconds
Started Jul 07 06:31:45 PM PDT 24
Finished Jul 07 06:32:18 PM PDT 24
Peak memory 250188 kb
Host smart-12cf9459-eff6-4ffc-b9ba-75e277868684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583079137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3583079137
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1947422074
Short name T482
Test name
Test status
Simulation time 34835185 ps
CPU time 0.73 seconds
Started Jul 07 06:31:53 PM PDT 24
Finished Jul 07 06:31:54 PM PDT 24
Peak memory 205788 kb
Host smart-5c4dbd74-e8a9-4515-a827-d2d7932e650a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947422074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1947422074
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3293447673
Short name T849
Test name
Test status
Simulation time 75482260 ps
CPU time 0.83 seconds
Started Jul 07 06:31:54 PM PDT 24
Finished Jul 07 06:31:55 PM PDT 24
Peak memory 207768 kb
Host smart-b1322998-7898-44ad-9722-6735ec2095bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293447673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3293447673
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2987088760
Short name T766
Test name
Test status
Simulation time 13939693243 ps
CPU time 51.69 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 257600 kb
Host smart-26594925-b96b-410f-b2e8-e50f778a8703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987088760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2987088760
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3852774913
Short name T37
Test name
Test status
Simulation time 82550367962 ps
CPU time 204.47 seconds
Started Jul 07 06:32:01 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 250424 kb
Host smart-1175ae45-35c9-43f1-9f7f-e85d9ba29bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852774913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3852774913
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3750757087
Short name T759
Test name
Test status
Simulation time 88263869440 ps
CPU time 75.83 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 251740 kb
Host smart-0dfe41ad-1903-4dd5-b012-d368170e7cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750757087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3750757087
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3957380900
Short name T335
Test name
Test status
Simulation time 13863017600 ps
CPU time 56.41 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:59 PM PDT 24
Peak memory 242384 kb
Host smart-cdd28168-97cf-4d86-bcf0-8a8305cc059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957380900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3957380900
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.662514767
Short name T229
Test name
Test status
Simulation time 7450795018 ps
CPU time 24.43 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 242092 kb
Host smart-61d867f5-e402-4eeb-8257-7a0635b200fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662514767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.662514767
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3603473421
Short name T670
Test name
Test status
Simulation time 441978045 ps
CPU time 3.53 seconds
Started Jul 07 06:31:53 PM PDT 24
Finished Jul 07 06:31:57 PM PDT 24
Peak memory 233760 kb
Host smart-58f3c334-0d13-407c-b22a-9710946d789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603473421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3603473421
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3537305713
Short name T560
Test name
Test status
Simulation time 2682640394 ps
CPU time 12.97 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:32:18 PM PDT 24
Peak memory 233880 kb
Host smart-5ac2aa2a-c085-428a-af78-7f7ccc80bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537305713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3537305713
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.396656039
Short name T415
Test name
Test status
Simulation time 193812194 ps
CPU time 3.44 seconds
Started Jul 07 06:31:51 PM PDT 24
Finished Jul 07 06:31:54 PM PDT 24
Peak memory 233788 kb
Host smart-3bc7ade4-df8d-4acf-8ff1-76083f881089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396656039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.396656039
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3015814905
Short name T304
Test name
Test status
Simulation time 2466223246 ps
CPU time 13.33 seconds
Started Jul 07 06:31:50 PM PDT 24
Finished Jul 07 06:32:04 PM PDT 24
Peak memory 236572 kb
Host smart-c388faf2-1456-4707-910e-68c31ab3de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015814905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3015814905
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3994608417
Short name T462
Test name
Test status
Simulation time 2810370149 ps
CPU time 9.69 seconds
Started Jul 07 06:31:55 PM PDT 24
Finished Jul 07 06:32:05 PM PDT 24
Peak memory 221944 kb
Host smart-d1c0c0d0-878f-4c6e-942e-64ad9389f44c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3994608417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3994608417
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2406679670
Short name T974
Test name
Test status
Simulation time 89926071417 ps
CPU time 73 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 256396 kb
Host smart-fc96cc37-b1e7-468f-8a87-479e1752d585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406679670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2406679670
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.495766789
Short name T975
Test name
Test status
Simulation time 838263000 ps
CPU time 5.66 seconds
Started Jul 07 06:31:50 PM PDT 24
Finished Jul 07 06:31:56 PM PDT 24
Peak memory 219408 kb
Host smart-5c82846b-8929-4b7a-9433-7b3834859982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495766789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.495766789
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3734587830
Short name T872
Test name
Test status
Simulation time 15730611 ps
CPU time 0.71 seconds
Started Jul 07 06:31:50 PM PDT 24
Finished Jul 07 06:31:51 PM PDT 24
Peak memory 206544 kb
Host smart-8611c661-0bba-4dae-b734-6b771c6712bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734587830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3734587830
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1380694253
Short name T710
Test name
Test status
Simulation time 315190811 ps
CPU time 2.09 seconds
Started Jul 07 06:31:53 PM PDT 24
Finished Jul 07 06:31:55 PM PDT 24
Peak memory 217280 kb
Host smart-79b58c3d-9941-4032-b2d9-9deb77e0b053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380694253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1380694253
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2145939856
Short name T394
Test name
Test status
Simulation time 136803756 ps
CPU time 0.82 seconds
Started Jul 07 06:31:51 PM PDT 24
Finished Jul 07 06:31:52 PM PDT 24
Peak memory 206960 kb
Host smart-29b043a9-f58e-4cde-bbc7-83eff782c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145939856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2145939856
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4198727258
Short name T533
Test name
Test status
Simulation time 12713042365 ps
CPU time 22.58 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:26 PM PDT 24
Peak memory 233852 kb
Host smart-55166636-a6ff-40fa-95d1-2a36c6f0aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198727258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4198727258
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2450762959
Short name T459
Test name
Test status
Simulation time 11793981 ps
CPU time 0.74 seconds
Started Jul 07 06:32:07 PM PDT 24
Finished Jul 07 06:32:08 PM PDT 24
Peak memory 205808 kb
Host smart-8fb83c09-f02c-4698-a015-20a782f44f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450762959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2450762959
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.560057144
Short name T741
Test name
Test status
Simulation time 1606282323 ps
CPU time 21.38 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:24 PM PDT 24
Peak memory 233764 kb
Host smart-bc1eee24-c7d3-460c-99cb-5997b744f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560057144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.560057144
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.311366343
Short name T383
Test name
Test status
Simulation time 19069007 ps
CPU time 0.77 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:04 PM PDT 24
Peak memory 207512 kb
Host smart-4bf777fc-e160-4008-9004-25bc78f883d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311366343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.311366343
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1154715343
Short name T481
Test name
Test status
Simulation time 1207627969 ps
CPU time 12.79 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:16 PM PDT 24
Peak memory 235076 kb
Host smart-c710bd97-0258-44c0-ba7b-7e22b739329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154715343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1154715343
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.874263134
Short name T808
Test name
Test status
Simulation time 2576564225 ps
CPU time 26.44 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:30 PM PDT 24
Peak memory 219032 kb
Host smart-9b86c982-47aa-4f7a-8a6a-ace81b869ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874263134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.874263134
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2764337718
Short name T239
Test name
Test status
Simulation time 5105847276 ps
CPU time 25 seconds
Started Jul 07 06:32:05 PM PDT 24
Finished Jul 07 06:32:30 PM PDT 24
Peak memory 250228 kb
Host smart-9f35857e-96d6-4f32-b7e4-de49fcb49dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764337718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2764337718
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3209458106
Short name T503
Test name
Test status
Simulation time 38083632 ps
CPU time 2.87 seconds
Started Jul 07 06:32:00 PM PDT 24
Finished Jul 07 06:32:05 PM PDT 24
Peak memory 233784 kb
Host smart-5c170a33-f2b8-4302-8f67-9f8aee3c5cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209458106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3209458106
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.4046474006
Short name T47
Test name
Test status
Simulation time 10721958258 ps
CPU time 74.04 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:33:18 PM PDT 24
Peak memory 255720 kb
Host smart-786e6ec0-be29-46de-9499-484ba8662574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046474006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.4046474006
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3459091774
Short name T643
Test name
Test status
Simulation time 49718954 ps
CPU time 2.56 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:06 PM PDT 24
Peak memory 233576 kb
Host smart-d4c4ee70-3327-4b23-9caa-31505ef03d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459091774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3459091774
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2335229006
Short name T237
Test name
Test status
Simulation time 2647898147 ps
CPU time 21.33 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:32:25 PM PDT 24
Peak memory 225652 kb
Host smart-7db042d2-274b-4c91-8385-e8b868ea6082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335229006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2335229006
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3282835208
Short name T957
Test name
Test status
Simulation time 7662879197 ps
CPU time 4.66 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:08 PM PDT 24
Peak memory 225660 kb
Host smart-cde3853b-7985-44b3-9291-473dba8e4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282835208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3282835208
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4018458742
Short name T1009
Test name
Test status
Simulation time 544690953 ps
CPU time 2.86 seconds
Started Jul 07 06:32:04 PM PDT 24
Finished Jul 07 06:32:07 PM PDT 24
Peak memory 233720 kb
Host smart-97084d41-c70e-47bd-8d55-9aef972fd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018458742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4018458742
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.331284544
Short name T756
Test name
Test status
Simulation time 3633939318 ps
CPU time 10.26 seconds
Started Jul 07 06:32:01 PM PDT 24
Finished Jul 07 06:32:12 PM PDT 24
Peak memory 221272 kb
Host smart-3aebe98b-8410-4a01-acc4-8ab2346e5441
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=331284544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.331284544
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3319478854
Short name T169
Test name
Test status
Simulation time 142383950515 ps
CPU time 394.65 seconds
Started Jul 07 06:32:05 PM PDT 24
Finished Jul 07 06:38:40 PM PDT 24
Peak memory 266640 kb
Host smart-eb6690ee-35d8-41ad-b550-526aeb9edace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319478854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3319478854
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2511685149
Short name T108
Test name
Test status
Simulation time 165936620 ps
CPU time 2.84 seconds
Started Jul 07 06:32:01 PM PDT 24
Finished Jul 07 06:32:05 PM PDT 24
Peak memory 217544 kb
Host smart-5a95ea5f-cbd1-40a1-a6ea-d2a0ec6183f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511685149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2511685149
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3272454536
Short name T558
Test name
Test status
Simulation time 769787583 ps
CPU time 3.33 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:06 PM PDT 24
Peak memory 217392 kb
Host smart-074b18dd-e628-4bbc-b9d1-e99ff933de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272454536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3272454536
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3142281984
Short name T408
Test name
Test status
Simulation time 57095784 ps
CPU time 0.99 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:04 PM PDT 24
Peak memory 208000 kb
Host smart-83b451ca-2260-40f2-ae25-edbfe990d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142281984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3142281984
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4031783756
Short name T356
Test name
Test status
Simulation time 12304319 ps
CPU time 0.71 seconds
Started Jul 07 06:32:02 PM PDT 24
Finished Jul 07 06:32:03 PM PDT 24
Peak memory 206560 kb
Host smart-bf51e133-f4a4-4160-9672-0b4841e12f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031783756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4031783756
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4187692119
Short name T666
Test name
Test status
Simulation time 1480970319 ps
CPU time 12.51 seconds
Started Jul 07 06:32:03 PM PDT 24
Finished Jul 07 06:32:16 PM PDT 24
Peak memory 241764 kb
Host smart-c6d415cc-0a69-4b7f-9529-316bb8fadaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187692119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4187692119
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1299725359
Short name T522
Test name
Test status
Simulation time 66191385 ps
CPU time 0.79 seconds
Started Jul 07 06:32:11 PM PDT 24
Finished Jul 07 06:32:12 PM PDT 24
Peak memory 205732 kb
Host smart-b744cc91-4a3a-4a5a-bd32-783df88f0f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299725359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1299725359
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2492765107
Short name T875
Test name
Test status
Simulation time 326352126 ps
CPU time 3.26 seconds
Started Jul 07 06:32:11 PM PDT 24
Finished Jul 07 06:32:15 PM PDT 24
Peak memory 225464 kb
Host smart-05e08570-ffbd-4ce8-a0ca-dd435669d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492765107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2492765107
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1494761899
Short name T410
Test name
Test status
Simulation time 21487945 ps
CPU time 0.79 seconds
Started Jul 07 06:32:05 PM PDT 24
Finished Jul 07 06:32:06 PM PDT 24
Peak memory 207492 kb
Host smart-1f6ae698-2be5-4f4c-92e3-9f1bf8c5a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494761899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1494761899
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3897491592
Short name T686
Test name
Test status
Simulation time 14367421216 ps
CPU time 65.91 seconds
Started Jul 07 06:32:11 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 256632 kb
Host smart-8d123971-5df3-4798-bbdb-aa91ed360e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897491592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3897491592
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2999307004
Short name T965
Test name
Test status
Simulation time 25525744162 ps
CPU time 58.97 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:33:07 PM PDT 24
Peak memory 241676 kb
Host smart-01565650-277a-4f4d-ae7c-9092cd364b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999307004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2999307004
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3852363325
Short name T984
Test name
Test status
Simulation time 2891360282 ps
CPU time 61.73 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:33:10 PM PDT 24
Peak memory 253812 kb
Host smart-050e733f-5d80-42c5-b1e5-101788812e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852363325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3852363325
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2622830843
Short name T652
Test name
Test status
Simulation time 6211421027 ps
CPU time 26.2 seconds
Started Jul 07 06:32:10 PM PDT 24
Finished Jul 07 06:32:37 PM PDT 24
Peak memory 225660 kb
Host smart-31f55bc6-2c27-477b-9672-0563c5d54dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622830843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2622830843
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2230665484
Short name T430
Test name
Test status
Simulation time 21958909213 ps
CPU time 147.6 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:34:36 PM PDT 24
Peak memory 256384 kb
Host smart-6ee3a429-f39c-403e-af4a-01f0a23fdbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230665484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2230665484
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3012139953
Short name T553
Test name
Test status
Simulation time 4835330151 ps
CPU time 9.76 seconds
Started Jul 07 06:32:09 PM PDT 24
Finished Jul 07 06:32:19 PM PDT 24
Peak memory 225640 kb
Host smart-72abc8b0-05e8-4de6-9441-b4c8f48fac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012139953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3012139953
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3451969868
Short name T513
Test name
Test status
Simulation time 1207370215 ps
CPU time 19.24 seconds
Started Jul 07 06:32:09 PM PDT 24
Finished Jul 07 06:32:28 PM PDT 24
Peak memory 225528 kb
Host smart-0e669a9f-1f14-474a-8386-ebe628c028d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451969868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3451969868
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3684661567
Short name T328
Test name
Test status
Simulation time 9112070066 ps
CPU time 13.13 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:32:22 PM PDT 24
Peak memory 235112 kb
Host smart-c4bd0fe0-6c73-4ed9-a504-839ea6e0c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684661567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3684661567
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.18398605
Short name T270
Test name
Test status
Simulation time 8384471449 ps
CPU time 9.83 seconds
Started Jul 07 06:32:09 PM PDT 24
Finished Jul 07 06:32:19 PM PDT 24
Peak memory 241912 kb
Host smart-61acfb20-006e-483d-8454-2d96a4a6da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18398605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.18398605
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1749487644
Short name T562
Test name
Test status
Simulation time 803533274 ps
CPU time 7.78 seconds
Started Jul 07 06:32:09 PM PDT 24
Finished Jul 07 06:32:17 PM PDT 24
Peak memory 223016 kb
Host smart-63b43ea7-3147-4857-bb21-83073be12e7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749487644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1749487644
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4100327884
Short name T166
Test name
Test status
Simulation time 39860620 ps
CPU time 0.93 seconds
Started Jul 07 06:32:07 PM PDT 24
Finished Jul 07 06:32:08 PM PDT 24
Peak memory 206476 kb
Host smart-dad708b3-c167-4ae5-8908-93703732cfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100327884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4100327884
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.870783786
Short name T551
Test name
Test status
Simulation time 3404562149 ps
CPU time 20.32 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:32:28 PM PDT 24
Peak memory 217504 kb
Host smart-6c465529-8d25-4665-ac59-cf4878c23c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870783786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.870783786
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3996775712
Short name T855
Test name
Test status
Simulation time 1002953433 ps
CPU time 2.78 seconds
Started Jul 07 06:32:07 PM PDT 24
Finished Jul 07 06:32:10 PM PDT 24
Peak memory 217376 kb
Host smart-a2034876-8699-457d-b2a9-956732ff3da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996775712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3996775712
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3432738187
Short name T62
Test name
Test status
Simulation time 79027370 ps
CPU time 1.26 seconds
Started Jul 07 06:32:08 PM PDT 24
Finished Jul 07 06:32:10 PM PDT 24
Peak memory 209076 kb
Host smart-20746f4a-7354-45ba-94fb-e63f6bce79fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432738187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3432738187
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1702071308
Short name T631
Test name
Test status
Simulation time 296376880 ps
CPU time 0.96 seconds
Started Jul 07 06:32:07 PM PDT 24
Finished Jul 07 06:32:08 PM PDT 24
Peak memory 207388 kb
Host smart-0ac46592-0892-4450-9f8c-cb871216eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702071308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1702071308
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1353339029
Short name T273
Test name
Test status
Simulation time 37000466025 ps
CPU time 28.85 seconds
Started Jul 07 06:32:09 PM PDT 24
Finished Jul 07 06:32:38 PM PDT 24
Peak memory 233852 kb
Host smart-4b96f8b3-8f4f-4732-87ca-bb4250a644a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353339029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1353339029
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1690617515
Short name T784
Test name
Test status
Simulation time 11917813 ps
CPU time 0.72 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:16 PM PDT 24
Peak memory 206736 kb
Host smart-8a1b9426-0ec1-4da2-b9be-7cf2d070aaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690617515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1690617515
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1358985690
Short name T201
Test name
Test status
Simulation time 392714195 ps
CPU time 5.09 seconds
Started Jul 07 06:32:16 PM PDT 24
Finished Jul 07 06:32:22 PM PDT 24
Peak memory 233768 kb
Host smart-66bf1559-3a5d-4d3c-bce9-75b1b854f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358985690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1358985690
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3361013934
Short name T817
Test name
Test status
Simulation time 86054005 ps
CPU time 0.79 seconds
Started Jul 07 06:32:13 PM PDT 24
Finished Jul 07 06:32:14 PM PDT 24
Peak memory 207528 kb
Host smart-35b098fa-3de4-4435-86d8-e79e2aefead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361013934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3361013934
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4248976305
Short name T313
Test name
Test status
Simulation time 22522651394 ps
CPU time 55.77 seconds
Started Jul 07 06:32:16 PM PDT 24
Finished Jul 07 06:33:12 PM PDT 24
Peak memory 265688 kb
Host smart-10d4009a-32a4-4004-90f2-18dae7003a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248976305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4248976305
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.452969018
Short name T232
Test name
Test status
Simulation time 111107926104 ps
CPU time 261.02 seconds
Started Jul 07 06:32:18 PM PDT 24
Finished Jul 07 06:36:39 PM PDT 24
Peak memory 258584 kb
Host smart-e1065d8e-f540-4d52-8689-ab21eac7a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452969018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.452969018
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2678252080
Short name T50
Test name
Test status
Simulation time 1290825835 ps
CPU time 38.58 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:54 PM PDT 24
Peak memory 254604 kb
Host smart-410ae258-e2e0-4926-88ed-de8a4b3b46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678252080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2678252080
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3403329761
Short name T172
Test name
Test status
Simulation time 474762530 ps
CPU time 3.06 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:18 PM PDT 24
Peak memory 225612 kb
Host smart-5477c9e7-18c3-4b6b-8646-756d4f37b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403329761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3403329761
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2907005559
Short name T466
Test name
Test status
Simulation time 167124038991 ps
CPU time 124.57 seconds
Started Jul 07 06:32:14 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 252856 kb
Host smart-90db10e1-3353-4982-9919-53ae11ce2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907005559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2907005559
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3240077342
Short name T887
Test name
Test status
Simulation time 1427438187 ps
CPU time 6.51 seconds
Started Jul 07 06:32:14 PM PDT 24
Finished Jul 07 06:32:21 PM PDT 24
Peak memory 233768 kb
Host smart-aef835e5-515f-4c61-8822-cbcc22e2be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240077342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3240077342
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.31901546
Short name T733
Test name
Test status
Simulation time 8451100684 ps
CPU time 103.68 seconds
Started Jul 07 06:32:16 PM PDT 24
Finished Jul 07 06:34:00 PM PDT 24
Peak memory 234900 kb
Host smart-b3c2cfdc-8dae-4024-adb2-454bbcf265a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31901546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.31901546
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1559028688
Short name T917
Test name
Test status
Simulation time 573720687 ps
CPU time 7.93 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:23 PM PDT 24
Peak memory 241628 kb
Host smart-f3f962d1-dacb-4db0-b107-95769d926281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559028688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1559028688
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3323716150
Short name T479
Test name
Test status
Simulation time 1921505767 ps
CPU time 7.28 seconds
Started Jul 07 06:32:12 PM PDT 24
Finished Jul 07 06:32:19 PM PDT 24
Peak memory 233784 kb
Host smart-845469cf-cd2c-48ae-801f-cd32ba892c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323716150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3323716150
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2473082979
Short name T488
Test name
Test status
Simulation time 2369285781 ps
CPU time 19.37 seconds
Started Jul 07 06:32:16 PM PDT 24
Finished Jul 07 06:32:36 PM PDT 24
Peak memory 221636 kb
Host smart-c2cf25f9-a704-450b-abf4-03839d43c810
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2473082979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2473082979
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.924433514
Short name T265
Test name
Test status
Simulation time 149701827558 ps
CPU time 352.96 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:38:08 PM PDT 24
Peak memory 256480 kb
Host smart-025dfb56-2223-4fec-a0d5-df9e450f8948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924433514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.924433514
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2396917378
Short name T486
Test name
Test status
Simulation time 3376348179 ps
CPU time 26.95 seconds
Started Jul 07 06:32:10 PM PDT 24
Finished Jul 07 06:32:37 PM PDT 24
Peak memory 217532 kb
Host smart-9e6879ff-2a7e-4cb0-924d-064b06b6f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396917378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2396917378
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.985747361
Short name T465
Test name
Test status
Simulation time 16024136137 ps
CPU time 18.99 seconds
Started Jul 07 06:32:12 PM PDT 24
Finished Jul 07 06:32:31 PM PDT 24
Peak memory 217508 kb
Host smart-3221819d-0fb3-40cc-b203-48051a8fd292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985747361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.985747361
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3081313531
Short name T665
Test name
Test status
Simulation time 21309155 ps
CPU time 1.39 seconds
Started Jul 07 06:32:12 PM PDT 24
Finished Jul 07 06:32:13 PM PDT 24
Peak memory 217368 kb
Host smart-cec51365-4e87-4c72-a272-d7fba00ba176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081313531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3081313531
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.473898817
Short name T511
Test name
Test status
Simulation time 354947919 ps
CPU time 0.98 seconds
Started Jul 07 06:32:14 PM PDT 24
Finished Jul 07 06:32:15 PM PDT 24
Peak memory 208020 kb
Host smart-02e199b8-5609-48f9-8a2c-8b8078422fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473898817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.473898817
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2833373780
Short name T890
Test name
Test status
Simulation time 1796528125 ps
CPU time 7.99 seconds
Started Jul 07 06:32:23 PM PDT 24
Finished Jul 07 06:32:31 PM PDT 24
Peak memory 233716 kb
Host smart-a91473d7-b6b8-4410-a804-fe86a9202ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833373780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2833373780
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4199529398
Short name T177
Test name
Test status
Simulation time 13244125 ps
CPU time 0.7 seconds
Started Jul 07 06:32:21 PM PDT 24
Finished Jul 07 06:32:22 PM PDT 24
Peak memory 205856 kb
Host smart-f4f398f4-5733-41ff-9bc9-22661276579d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199529398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4199529398
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2886491582
Short name T868
Test name
Test status
Simulation time 2880642966 ps
CPU time 7.38 seconds
Started Jul 07 06:32:19 PM PDT 24
Finished Jul 07 06:32:26 PM PDT 24
Peak memory 233924 kb
Host smart-3d56117e-8f90-45a9-aa4c-345df3ad42a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886491582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2886491582
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.621789170
Short name T677
Test name
Test status
Simulation time 99836970 ps
CPU time 0.79 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:16 PM PDT 24
Peak memory 207448 kb
Host smart-dacdad18-d292-4596-ac26-2b8f8750b576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621789170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.621789170
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3233643404
Short name T807
Test name
Test status
Simulation time 42484339242 ps
CPU time 140.86 seconds
Started Jul 07 06:32:24 PM PDT 24
Finished Jul 07 06:34:45 PM PDT 24
Peak memory 258468 kb
Host smart-e4eab92e-e806-4936-9d9a-cbe363272e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233643404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3233643404
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1822480594
Short name T220
Test name
Test status
Simulation time 330767555432 ps
CPU time 199.21 seconds
Started Jul 07 06:32:23 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 251292 kb
Host smart-0f0d0000-2103-421d-bf4b-b568e08983f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822480594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1822480594
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2238686671
Short name T51
Test name
Test status
Simulation time 8037657277 ps
CPU time 96.07 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:33:59 PM PDT 24
Peak memory 250396 kb
Host smart-260a3411-7342-4279-9e8e-d7d54fcaf670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238686671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2238686671
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3477913729
Short name T331
Test name
Test status
Simulation time 79104191453 ps
CPU time 69.39 seconds
Started Jul 07 06:32:20 PM PDT 24
Finished Jul 07 06:33:30 PM PDT 24
Peak memory 249740 kb
Host smart-fdc4d563-704c-4c80-b8f7-4e708f65367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477913729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3477913729
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1550624464
Short name T94
Test name
Test status
Simulation time 2654519494 ps
CPU time 65.61 seconds
Started Jul 07 06:32:20 PM PDT 24
Finished Jul 07 06:33:26 PM PDT 24
Peak memory 258476 kb
Host smart-869036ad-5ee7-4470-ad0a-c324201e91bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550624464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1550624464
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.495154187
Short name T724
Test name
Test status
Simulation time 110632313 ps
CPU time 2.9 seconds
Started Jul 07 06:32:18 PM PDT 24
Finished Jul 07 06:32:21 PM PDT 24
Peak memory 225544 kb
Host smart-8ab20c63-e4a8-4090-92d1-48a3b171ccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495154187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.495154187
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.909754347
Short name T276
Test name
Test status
Simulation time 7365822180 ps
CPU time 33.3 seconds
Started Jul 07 06:32:20 PM PDT 24
Finished Jul 07 06:32:53 PM PDT 24
Peak memory 233864 kb
Host smart-f3ed8e0b-4c0c-4952-b313-6aaccd7e0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909754347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.909754347
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.19988951
Short name T238
Test name
Test status
Simulation time 2102200790 ps
CPU time 7.73 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:32:31 PM PDT 24
Peak memory 233752 kb
Host smart-34edb2a0-6a2a-4732-9585-05932fcf8db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19988951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.19988951
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.409582824
Short name T616
Test name
Test status
Simulation time 1319228168 ps
CPU time 4.15 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 225580 kb
Host smart-d388065e-bec0-43f2-aa88-af7475d63d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409582824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.409582824
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1853439792
Short name T155
Test name
Test status
Simulation time 7120083489 ps
CPU time 22.42 seconds
Started Jul 07 06:32:28 PM PDT 24
Finished Jul 07 06:32:50 PM PDT 24
Peak memory 221336 kb
Host smart-6e893577-6fc4-4dd7-b309-dc312c068da6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853439792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1853439792
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.86174114
Short name T293
Test name
Test status
Simulation time 105272999669 ps
CPU time 476.59 seconds
Started Jul 07 06:32:25 PM PDT 24
Finished Jul 07 06:40:22 PM PDT 24
Peak memory 274568 kb
Host smart-4cfd7b3e-e432-4674-8581-78bd70dcb91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86174114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.86174114
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1833731362
Short name T439
Test name
Test status
Simulation time 1212733146 ps
CPU time 17.21 seconds
Started Jul 07 06:32:13 PM PDT 24
Finished Jul 07 06:32:31 PM PDT 24
Peak memory 217392 kb
Host smart-ef7d3cb5-d612-48da-9ec9-61e23465d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833731362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1833731362
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3874937235
Short name T680
Test name
Test status
Simulation time 1111101928 ps
CPU time 1.61 seconds
Started Jul 07 06:32:15 PM PDT 24
Finished Jul 07 06:32:17 PM PDT 24
Peak memory 208152 kb
Host smart-bb8d0f3e-fb94-4b82-9df8-82a8fb2c5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874937235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3874937235
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.974537549
Short name T931
Test name
Test status
Simulation time 205302973 ps
CPU time 4.6 seconds
Started Jul 07 06:32:17 PM PDT 24
Finished Jul 07 06:32:22 PM PDT 24
Peak memory 217276 kb
Host smart-7be15c90-4eac-4830-a93a-3bc7e24fc4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974537549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.974537549
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2869686077
Short name T703
Test name
Test status
Simulation time 77570618 ps
CPU time 0.75 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:32:23 PM PDT 24
Peak memory 206960 kb
Host smart-4721f7b0-a102-4837-a5a5-609c5ec3de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869686077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2869686077
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1783336091
Short name T896
Test name
Test status
Simulation time 4343868414 ps
CPU time 15.06 seconds
Started Jul 07 06:32:20 PM PDT 24
Finished Jul 07 06:32:36 PM PDT 24
Peak memory 233752 kb
Host smart-b5de4b43-35aa-4fb1-8913-38a2ab21a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783336091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1783336091
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.865223788
Short name T473
Test name
Test status
Simulation time 39994870 ps
CPU time 0.75 seconds
Started Jul 07 06:32:25 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 205800 kb
Host smart-84170939-b562-4309-b6ed-986d109c8780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865223788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.865223788
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4194360685
Short name T12
Test name
Test status
Simulation time 541001291 ps
CPU time 3.85 seconds
Started Jul 07 06:32:25 PM PDT 24
Finished Jul 07 06:32:29 PM PDT 24
Peak memory 233748 kb
Host smart-52f6d78b-868e-41b8-b1a5-e413e0a4a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194360685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4194360685
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3128651636
Short name T634
Test name
Test status
Simulation time 22102376 ps
CPU time 0.78 seconds
Started Jul 07 06:32:25 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 207544 kb
Host smart-11b32807-93c6-40ff-b75b-1f11c7a841bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128651636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3128651636
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2199496358
Short name T85
Test name
Test status
Simulation time 6913539662 ps
CPU time 97.63 seconds
Started Jul 07 06:32:28 PM PDT 24
Finished Jul 07 06:34:05 PM PDT 24
Peak memory 251280 kb
Host smart-cbd164dc-89ad-40c1-82a2-b4347a7b8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199496358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2199496358
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1496741363
Short name T991
Test name
Test status
Simulation time 21021770082 ps
CPU time 51.93 seconds
Started Jul 07 06:32:24 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 235192 kb
Host smart-b340f333-fc12-4a27-8377-c7ca76ee3da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496741363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1496741363
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2319170463
Short name T13
Test name
Test status
Simulation time 21796345983 ps
CPU time 116.64 seconds
Started Jul 07 06:32:28 PM PDT 24
Finished Jul 07 06:34:24 PM PDT 24
Peak memory 240168 kb
Host smart-17fe23ab-e2c1-4b75-88b2-dabce82e671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319170463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2319170463
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3422601331
Short name T404
Test name
Test status
Simulation time 5788541994 ps
CPU time 13.01 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:32:39 PM PDT 24
Peak memory 233896 kb
Host smart-b4abf53b-0cbf-4e8d-91a0-8581a0c3f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422601331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3422601331
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4086686074
Short name T204
Test name
Test status
Simulation time 5450602078 ps
CPU time 10.22 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:32:37 PM PDT 24
Peak memory 225648 kb
Host smart-1ed8b4fa-789f-4e04-bfc2-b17543c23be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086686074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4086686074
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2710796561
Short name T234
Test name
Test status
Simulation time 897164760 ps
CPU time 11.76 seconds
Started Jul 07 06:32:23 PM PDT 24
Finished Jul 07 06:32:35 PM PDT 24
Peak memory 233644 kb
Host smart-6f6b3bf2-9b8f-434c-9de2-133c390a41a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710796561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2710796561
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1873676182
Short name T783
Test name
Test status
Simulation time 1923566045 ps
CPU time 7.48 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:32:30 PM PDT 24
Peak memory 225572 kb
Host smart-c9d20f3d-0b2c-4a2e-8b73-f6b458e43fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873676182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1873676182
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2630423178
Short name T711
Test name
Test status
Simulation time 5291597978 ps
CPU time 16.84 seconds
Started Jul 07 06:32:23 PM PDT 24
Finished Jul 07 06:32:40 PM PDT 24
Peak memory 233912 kb
Host smart-a723140d-7001-454c-98b2-388b56dab551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630423178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2630423178
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.302039778
Short name T33
Test name
Test status
Simulation time 5333882990 ps
CPU time 16.19 seconds
Started Jul 07 06:32:27 PM PDT 24
Finished Jul 07 06:32:43 PM PDT 24
Peak memory 223264 kb
Host smart-77a8ae80-2406-4d98-98a3-cf837a86b26d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302039778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.302039778
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2647732251
Short name T496
Test name
Test status
Simulation time 3486233052 ps
CPU time 25.86 seconds
Started Jul 07 06:32:24 PM PDT 24
Finished Jul 07 06:32:50 PM PDT 24
Peak memory 217648 kb
Host smart-caa20e48-a10b-4e3f-a87c-88b0a96a717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647732251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2647732251
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4243975909
Short name T1001
Test name
Test status
Simulation time 12938143437 ps
CPU time 8.28 seconds
Started Jul 07 06:32:23 PM PDT 24
Finished Jul 07 06:32:32 PM PDT 24
Peak memory 217476 kb
Host smart-ba405f6b-5228-48ca-9eac-9bcf80d5a5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243975909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4243975909
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3093586538
Short name T424
Test name
Test status
Simulation time 111806776 ps
CPU time 2.02 seconds
Started Jul 07 06:32:24 PM PDT 24
Finished Jul 07 06:32:26 PM PDT 24
Peak memory 217292 kb
Host smart-cd2ae62d-8641-4676-8572-f444f845efda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093586538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3093586538
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1955714119
Short name T440
Test name
Test status
Simulation time 149168543 ps
CPU time 0.73 seconds
Started Jul 07 06:32:22 PM PDT 24
Finished Jul 07 06:32:23 PM PDT 24
Peak memory 206984 kb
Host smart-ef18d8ab-cbad-411d-84c5-b4a5999cbff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955714119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1955714119
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1078070183
Short name T443
Test name
Test status
Simulation time 2184556604 ps
CPU time 16.37 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:32:42 PM PDT 24
Peak memory 231328 kb
Host smart-4fba4da0-f07e-471a-89d4-26693034da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078070183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1078070183
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3847291747
Short name T512
Test name
Test status
Simulation time 36493452 ps
CPU time 0.75 seconds
Started Jul 07 06:32:34 PM PDT 24
Finished Jul 07 06:32:35 PM PDT 24
Peak memory 206692 kb
Host smart-c0cdcda0-c59d-47f2-b02e-8d0d422c02c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847291747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3847291747
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1163026746
Short name T484
Test name
Test status
Simulation time 1190402337 ps
CPU time 5.57 seconds
Started Jul 07 06:32:31 PM PDT 24
Finished Jul 07 06:32:37 PM PDT 24
Peak memory 225612 kb
Host smart-54a77bd8-7469-46de-9248-3bf86d28fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163026746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1163026746
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.534223898
Short name T791
Test name
Test status
Simulation time 22159419 ps
CPU time 0.77 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:32:28 PM PDT 24
Peak memory 207512 kb
Host smart-5c7ffba7-97bb-4594-9bec-fab5ef93bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534223898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.534223898
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2533859731
Short name T81
Test name
Test status
Simulation time 55353236506 ps
CPU time 80.68 seconds
Started Jul 07 06:32:32 PM PDT 24
Finished Jul 07 06:33:53 PM PDT 24
Peak memory 250292 kb
Host smart-a2b1d3d6-e3e4-41fa-9f53-48abef9c29f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533859731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2533859731
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4018145451
Short name T853
Test name
Test status
Simulation time 153251183803 ps
CPU time 248.88 seconds
Started Jul 07 06:32:33 PM PDT 24
Finished Jul 07 06:36:42 PM PDT 24
Peak memory 257228 kb
Host smart-56f94e4a-2cf0-4f05-89f3-fcec3b514d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018145451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4018145451
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.885308691
Short name T242
Test name
Test status
Simulation time 8969071384 ps
CPU time 46.2 seconds
Started Jul 07 06:32:32 PM PDT 24
Finished Jul 07 06:33:18 PM PDT 24
Peak memory 255828 kb
Host smart-20b7b509-17f7-485f-961b-cdf154eea77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885308691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.885308691
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3213627813
Short name T401
Test name
Test status
Simulation time 1263517224 ps
CPU time 8.02 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:32:38 PM PDT 24
Peak memory 237136 kb
Host smart-cfe880a7-822b-4223-9754-a616efcd9a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213627813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3213627813
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.918132164
Short name T543
Test name
Test status
Simulation time 5456867904 ps
CPU time 63.54 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:33:34 PM PDT 24
Peak memory 263752 kb
Host smart-b6e4572d-9048-4349-a3f6-9e27af1daac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918132164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.918132164
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1510252008
Short name T967
Test name
Test status
Simulation time 1080701863 ps
CPU time 9.56 seconds
Started Jul 07 06:32:29 PM PDT 24
Finished Jul 07 06:32:39 PM PDT 24
Peak memory 233744 kb
Host smart-65f2c007-4848-4f4a-962e-9a72654f61d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510252008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1510252008
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.15943176
Short name T490
Test name
Test status
Simulation time 25553116578 ps
CPU time 38.67 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:33:09 PM PDT 24
Peak memory 233872 kb
Host smart-c60de4e7-ea25-4e26-93b1-8965c822f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15943176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.15943176
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1237993890
Short name T863
Test name
Test status
Simulation time 13233285938 ps
CPU time 17.45 seconds
Started Jul 07 06:32:32 PM PDT 24
Finished Jul 07 06:32:49 PM PDT 24
Peak memory 231064 kb
Host smart-338eb10c-3e54-47fc-91cd-69fe007ca542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237993890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1237993890
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1812831070
Short name T302
Test name
Test status
Simulation time 10316729023 ps
CPU time 8.45 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:32:39 PM PDT 24
Peak memory 233872 kb
Host smart-d8950f77-30b2-4070-8cc2-4f1dfecec10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812831070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1812831070
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.216547471
Short name T485
Test name
Test status
Simulation time 240714483 ps
CPU time 4.77 seconds
Started Jul 07 06:32:31 PM PDT 24
Finished Jul 07 06:32:36 PM PDT 24
Peak memory 221400 kb
Host smart-c1cc8faa-6cbe-420d-9d38-639bcc79484e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=216547471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.216547471
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.694424123
Short name T20
Test name
Test status
Simulation time 73664306 ps
CPU time 1.11 seconds
Started Jul 07 06:32:35 PM PDT 24
Finished Jul 07 06:32:36 PM PDT 24
Peak memory 208784 kb
Host smart-bc397156-533a-49f8-b91a-264da5e0a31a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694424123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.694424123
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2811422054
Short name T725
Test name
Test status
Simulation time 4553144294 ps
CPU time 18.78 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:32:49 PM PDT 24
Peak memory 217508 kb
Host smart-a5606dbf-1e7c-475e-aa16-ad22aa24b42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811422054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2811422054
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1539752067
Short name T358
Test name
Test status
Simulation time 40421589331 ps
CPU time 18.56 seconds
Started Jul 07 06:32:30 PM PDT 24
Finished Jul 07 06:32:49 PM PDT 24
Peak memory 217504 kb
Host smart-1a5f74e5-a15d-4262-8d45-d2cbe6f4bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539752067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1539752067
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3487140039
Short name T375
Test name
Test status
Simulation time 60234136 ps
CPU time 1.07 seconds
Started Jul 07 06:32:26 PM PDT 24
Finished Jul 07 06:32:27 PM PDT 24
Peak memory 208416 kb
Host smart-9f16fe76-90a0-4532-a394-c6346e5eb52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487140039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3487140039
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.339192496
Short name T576
Test name
Test status
Simulation time 65840272 ps
CPU time 0.87 seconds
Started Jul 07 06:32:27 PM PDT 24
Finished Jul 07 06:32:28 PM PDT 24
Peak memory 206968 kb
Host smart-1e9d58de-750b-47c3-aa63-428639501bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339192496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.339192496
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3046215436
Short name T297
Test name
Test status
Simulation time 138499574 ps
CPU time 3.2 seconds
Started Jul 07 06:32:31 PM PDT 24
Finished Jul 07 06:32:35 PM PDT 24
Peak memory 233772 kb
Host smart-fe4e4e77-08b0-494c-8081-06dcaec2bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046215436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3046215436
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.148920070
Short name T402
Test name
Test status
Simulation time 12610017 ps
CPU time 0.71 seconds
Started Jul 07 06:32:42 PM PDT 24
Finished Jul 07 06:32:43 PM PDT 24
Peak memory 205816 kb
Host smart-5aa03a48-f07b-47ef-89a0-708360dd69a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148920070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.148920070
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.230386996
Short name T833
Test name
Test status
Simulation time 435309771 ps
CPU time 2.41 seconds
Started Jul 07 06:32:36 PM PDT 24
Finished Jul 07 06:32:39 PM PDT 24
Peak memory 225456 kb
Host smart-4efd6201-9b1e-41e6-9b12-0b606e79c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230386996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.230386996
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.9257999
Short name T75
Test name
Test status
Simulation time 47558529 ps
CPU time 0.77 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:32:38 PM PDT 24
Peak memory 207548 kb
Host smart-75782cae-874c-4113-b4d6-c51f3acda6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9257999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.9257999
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.248801938
Short name T221
Test name
Test status
Simulation time 25775145245 ps
CPU time 68.64 seconds
Started Jul 07 06:32:40 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 252224 kb
Host smart-f9c71229-c0cb-4f47-a3b9-646e0eef7344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248801938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.248801938
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1380038678
Short name T796
Test name
Test status
Simulation time 14649917037 ps
CPU time 39.17 seconds
Started Jul 07 06:32:41 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 258352 kb
Host smart-a8e2c88a-78c9-476c-a757-784ba6df660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380038678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1380038678
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.693199032
Short name T748
Test name
Test status
Simulation time 132253834649 ps
CPU time 164.22 seconds
Started Jul 07 06:32:42 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 253672 kb
Host smart-3f251b85-e05c-4722-bf96-7a3731b1dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693199032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.693199032
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1425537932
Short name T426
Test name
Test status
Simulation time 4847751207 ps
CPU time 18.08 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 225668 kb
Host smart-c07e1bf5-f91b-49a2-9236-30c62e5250dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425537932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1425537932
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1306817837
Short name T254
Test name
Test status
Simulation time 1757272249 ps
CPU time 11.16 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:32:48 PM PDT 24
Peak memory 225592 kb
Host smart-bce6486f-3759-43d8-bbd4-33e296c14a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306817837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1306817837
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1214536825
Short name T717
Test name
Test status
Simulation time 2449482751 ps
CPU time 6.18 seconds
Started Jul 07 06:32:43 PM PDT 24
Finished Jul 07 06:32:49 PM PDT 24
Peak memory 233868 kb
Host smart-130bc33a-5d99-4ed2-8f4f-368c5480259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214536825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1214536825
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4030125736
Short name T805
Test name
Test status
Simulation time 5608477894 ps
CPU time 17.63 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:32:55 PM PDT 24
Peak memory 233892 kb
Host smart-ed387b11-16d4-4a02-82d2-593626716d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030125736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4030125736
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3168450304
Short name T663
Test name
Test status
Simulation time 3241996103 ps
CPU time 4.78 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:32:42 PM PDT 24
Peak memory 233864 kb
Host smart-2ed966eb-8c93-4594-a200-05311344437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168450304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3168450304
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.787454521
Short name T421
Test name
Test status
Simulation time 30759176 ps
CPU time 2.2 seconds
Started Jul 07 06:32:42 PM PDT 24
Finished Jul 07 06:32:45 PM PDT 24
Peak memory 223992 kb
Host smart-359d883a-96ba-4be4-af4d-9fb539b6c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787454521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.787454521
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.830149960
Short name T504
Test name
Test status
Simulation time 1417725381 ps
CPU time 10.7 seconds
Started Jul 07 06:32:42 PM PDT 24
Finished Jul 07 06:32:53 PM PDT 24
Peak memory 221004 kb
Host smart-47b669e0-0d62-4c8a-bfad-c1010a35381e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=830149960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.830149960
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1790776807
Short name T317
Test name
Test status
Simulation time 178508283849 ps
CPU time 880.05 seconds
Started Jul 07 06:32:41 PM PDT 24
Finished Jul 07 06:47:21 PM PDT 24
Peak memory 274056 kb
Host smart-1dc0e784-63f0-420a-92b1-f5c0b41c104a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790776807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1790776807
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.390462172
Short name T345
Test name
Test status
Simulation time 11945333450 ps
CPU time 33.51 seconds
Started Jul 07 06:32:37 PM PDT 24
Finished Jul 07 06:33:11 PM PDT 24
Peak memory 217444 kb
Host smart-92a3f1a3-e888-4ddb-952d-60f00754c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390462172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.390462172
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1673814228
Short name T371
Test name
Test status
Simulation time 44818523 ps
CPU time 0.72 seconds
Started Jul 07 06:32:39 PM PDT 24
Finished Jul 07 06:32:40 PM PDT 24
Peak memory 206608 kb
Host smart-0a2f11c3-eac3-4c6e-835e-25b14d262c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673814228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1673814228
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3254185983
Short name T386
Test name
Test status
Simulation time 110323099 ps
CPU time 0.81 seconds
Started Jul 07 06:32:38 PM PDT 24
Finished Jul 07 06:32:39 PM PDT 24
Peak memory 206928 kb
Host smart-25472731-8246-4b45-8199-1c61dbc95a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254185983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3254185983
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2835754854
Short name T770
Test name
Test status
Simulation time 53563207 ps
CPU time 0.75 seconds
Started Jul 07 06:32:36 PM PDT 24
Finished Jul 07 06:32:37 PM PDT 24
Peak memory 206940 kb
Host smart-ed382676-cc97-4032-b7e8-716a0df69315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835754854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2835754854
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4000002054
Short name T758
Test name
Test status
Simulation time 559155824 ps
CPU time 3 seconds
Started Jul 07 06:32:38 PM PDT 24
Finished Jul 07 06:32:41 PM PDT 24
Peak memory 225560 kb
Host smart-428b48c7-2029-44f6-92c8-6ff8eae66308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000002054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4000002054
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2335813061
Short name T363
Test name
Test status
Simulation time 21494380 ps
CPU time 0.74 seconds
Started Jul 07 06:29:23 PM PDT 24
Finished Jul 07 06:29:24 PM PDT 24
Peak memory 206384 kb
Host smart-efbdabe5-d514-498f-9c56-2bf0bd12a028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335813061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
335813061
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2982629179
Short name T370
Test name
Test status
Simulation time 53533905 ps
CPU time 2.06 seconds
Started Jul 07 06:29:12 PM PDT 24
Finished Jul 07 06:29:14 PM PDT 24
Peak memory 225160 kb
Host smart-2551e7aa-a824-4109-9de9-050e1c8c814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982629179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2982629179
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1990274816
Short name T384
Test name
Test status
Simulation time 61895267 ps
CPU time 0.78 seconds
Started Jul 07 06:29:10 PM PDT 24
Finished Jul 07 06:29:11 PM PDT 24
Peak memory 207876 kb
Host smart-3b356e02-100e-4bf9-8ab1-fab0043a7fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990274816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1990274816
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4179801981
Short name T248
Test name
Test status
Simulation time 3576071913 ps
CPU time 66.89 seconds
Started Jul 07 06:29:17 PM PDT 24
Finished Jul 07 06:30:24 PM PDT 24
Peak memory 274564 kb
Host smart-40ea3692-e34d-4d5b-8e35-606bfd9681c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179801981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4179801981
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.537413908
Short name T348
Test name
Test status
Simulation time 4490337684 ps
CPU time 31.31 seconds
Started Jul 07 06:29:16 PM PDT 24
Finished Jul 07 06:29:47 PM PDT 24
Peak memory 225760 kb
Host smart-2879b83e-7f65-43c5-a5a6-f07041243bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537413908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.537413908
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.666159123
Short name T256
Test name
Test status
Simulation time 8389291729 ps
CPU time 46.91 seconds
Started Jul 07 06:29:16 PM PDT 24
Finished Jul 07 06:30:03 PM PDT 24
Peak memory 250432 kb
Host smart-a7c32035-785d-404b-be34-00f5b7bb2bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666159123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
666159123
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.392967315
Short name T594
Test name
Test status
Simulation time 1261312044 ps
CPU time 8.57 seconds
Started Jul 07 06:29:15 PM PDT 24
Finished Jul 07 06:29:24 PM PDT 24
Peak memory 234808 kb
Host smart-b1bf861f-4f66-4ced-8332-47c5e898205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392967315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.392967315
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1992066071
Short name T97
Test name
Test status
Simulation time 10757943732 ps
CPU time 26.55 seconds
Started Jul 07 06:29:13 PM PDT 24
Finished Jul 07 06:29:40 PM PDT 24
Peak memory 238724 kb
Host smart-65473bed-6f46-4f2b-9c0d-65e4a32a9067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992066071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1992066071
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2246758124
Short name T24
Test name
Test status
Simulation time 160217660 ps
CPU time 2.72 seconds
Started Jul 07 06:29:15 PM PDT 24
Finished Jul 07 06:29:18 PM PDT 24
Peak memory 233744 kb
Host smart-d2e7ed30-f476-4e82-ba52-4d0684b8624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246758124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2246758124
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2593696445
Short name T563
Test name
Test status
Simulation time 680050895 ps
CPU time 14.02 seconds
Started Jul 07 06:29:15 PM PDT 24
Finished Jul 07 06:29:29 PM PDT 24
Peak memory 233796 kb
Host smart-e78a6d98-72bf-4394-90ab-5e0f23deda1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593696445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2593696445
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1915713935
Short name T40
Test name
Test status
Simulation time 24572443 ps
CPU time 1.02 seconds
Started Jul 07 06:29:11 PM PDT 24
Finished Jul 07 06:29:12 PM PDT 24
Peak memory 217692 kb
Host smart-2a0bbe06-f704-43ce-b275-a513a72feb1c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915713935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1915713935
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3841164421
Short name T630
Test name
Test status
Simulation time 67036037 ps
CPU time 2.42 seconds
Started Jul 07 06:29:15 PM PDT 24
Finished Jul 07 06:29:18 PM PDT 24
Peak memory 233544 kb
Host smart-986501c5-048c-4a49-9138-0383530a0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841164421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3841164421
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.50029056
Short name T812
Test name
Test status
Simulation time 851484629 ps
CPU time 2.48 seconds
Started Jul 07 06:29:17 PM PDT 24
Finished Jul 07 06:29:20 PM PDT 24
Peak memory 225568 kb
Host smart-4afabb7f-768b-429f-92f2-df768130a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50029056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.50029056
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4037966727
Short name T613
Test name
Test status
Simulation time 2082377644 ps
CPU time 4.57 seconds
Started Jul 07 06:29:15 PM PDT 24
Finished Jul 07 06:29:20 PM PDT 24
Peak memory 219956 kb
Host smart-8674852e-1ffc-42bd-a89c-b63bfea819fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4037966727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4037966727
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3183679754
Short name T347
Test name
Test status
Simulation time 1529796128 ps
CPU time 11.61 seconds
Started Jul 07 06:29:13 PM PDT 24
Finished Jul 07 06:29:25 PM PDT 24
Peak memory 217392 kb
Host smart-6f2c956c-d256-4b57-88ac-aae94e986da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183679754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3183679754
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.501487906
Short name T477
Test name
Test status
Simulation time 4161099161 ps
CPU time 4.95 seconds
Started Jul 07 06:29:13 PM PDT 24
Finished Jul 07 06:29:18 PM PDT 24
Peak memory 217456 kb
Host smart-09a1e568-2870-4231-b381-d759e4f19611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501487906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.501487906
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3765663238
Short name T445
Test name
Test status
Simulation time 72841245 ps
CPU time 2.25 seconds
Started Jul 07 06:29:13 PM PDT 24
Finished Jul 07 06:29:16 PM PDT 24
Peak memory 217320 kb
Host smart-7956ef7b-fd29-44a6-8b77-3c6c419e2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765663238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3765663238
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.433976725
Short name T416
Test name
Test status
Simulation time 449581731 ps
CPU time 1.01 seconds
Started Jul 07 06:29:14 PM PDT 24
Finished Jul 07 06:29:15 PM PDT 24
Peak memory 206960 kb
Host smart-6343d46d-3c42-4f3f-869f-c9216831f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433976725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.433976725
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3471378306
Short name T546
Test name
Test status
Simulation time 5970069157 ps
CPU time 4.84 seconds
Started Jul 07 06:29:16 PM PDT 24
Finished Jul 07 06:29:21 PM PDT 24
Peak memory 233864 kb
Host smart-0dba75e9-055c-43b3-890e-3ffc8bc5bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471378306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3471378306
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3893566363
Short name T142
Test name
Test status
Simulation time 53429594 ps
CPU time 0.76 seconds
Started Jul 07 06:32:48 PM PDT 24
Finished Jul 07 06:32:49 PM PDT 24
Peak memory 205864 kb
Host smart-6a803f6e-02a3-438a-8279-6d97649168f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893566363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3893566363
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1920055348
Short name T713
Test name
Test status
Simulation time 553067455 ps
CPU time 6.77 seconds
Started Jul 07 06:32:46 PM PDT 24
Finished Jul 07 06:32:53 PM PDT 24
Peak memory 225524 kb
Host smart-96f24a53-3d90-4448-9fe4-58f3f0a72261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920055348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1920055348
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3173811809
Short name T391
Test name
Test status
Simulation time 48612683 ps
CPU time 0.75 seconds
Started Jul 07 06:32:40 PM PDT 24
Finished Jul 07 06:32:41 PM PDT 24
Peak memory 207504 kb
Host smart-f71d9944-5aec-49be-a601-13baa943afe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173811809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3173811809
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2582278593
Short name T647
Test name
Test status
Simulation time 26241506001 ps
CPU time 96.25 seconds
Started Jul 07 06:32:46 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 258428 kb
Host smart-9f587085-d278-4bd7-85fd-ef88395759af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582278593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2582278593
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3722805337
Short name T607
Test name
Test status
Simulation time 14537849478 ps
CPU time 80.43 seconds
Started Jul 07 06:32:47 PM PDT 24
Finished Jul 07 06:34:07 PM PDT 24
Peak memory 250428 kb
Host smart-d4ac73e2-4691-429f-9d36-dd9230c2069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722805337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3722805337
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1283226702
Short name T311
Test name
Test status
Simulation time 642379352932 ps
CPU time 713.47 seconds
Started Jul 07 06:32:48 PM PDT 24
Finished Jul 07 06:44:41 PM PDT 24
Peak memory 258108 kb
Host smart-f3cb2800-86d1-4073-8722-10a613255bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283226702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1283226702
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4117930845
Short name T329
Test name
Test status
Simulation time 751208708 ps
CPU time 8.5 seconds
Started Jul 07 06:32:48 PM PDT 24
Finished Jul 07 06:32:57 PM PDT 24
Peak memory 225588 kb
Host smart-77aa0238-7097-4802-8b48-c311091342fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117930845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4117930845
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3028024718
Short name T196
Test name
Test status
Simulation time 532149802815 ps
CPU time 351.6 seconds
Started Jul 07 06:32:47 PM PDT 24
Finished Jul 07 06:38:39 PM PDT 24
Peak memory 250396 kb
Host smart-2742208e-3bc8-466b-aba4-4243bbe6d95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028024718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3028024718
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.106741245
Short name T681
Test name
Test status
Simulation time 11068864605 ps
CPU time 13.6 seconds
Started Jul 07 06:32:43 PM PDT 24
Finished Jul 07 06:32:57 PM PDT 24
Peak memory 225656 kb
Host smart-1f8f428f-3e25-482b-82f9-2c4956985436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106741245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.106741245
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3993064638
Short name T932
Test name
Test status
Simulation time 30636193064 ps
CPU time 28.01 seconds
Started Jul 07 06:32:47 PM PDT 24
Finished Jul 07 06:33:15 PM PDT 24
Peak memory 225668 kb
Host smart-19568c55-8d11-4e53-ac50-522c623f54a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993064638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3993064638
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1777511591
Short name T637
Test name
Test status
Simulation time 44209701 ps
CPU time 2.58 seconds
Started Jul 07 06:32:45 PM PDT 24
Finished Jul 07 06:32:48 PM PDT 24
Peak memory 233748 kb
Host smart-16cb335a-f5f9-417b-8f63-349da2fa38c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777511591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1777511591
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4062127421
Short name T722
Test name
Test status
Simulation time 3995938461 ps
CPU time 10.99 seconds
Started Jul 07 06:32:43 PM PDT 24
Finished Jul 07 06:32:54 PM PDT 24
Peak memory 225584 kb
Host smart-b5600115-cd95-42b6-a0ab-5f91f9c212f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062127421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4062127421
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1516443121
Short name T446
Test name
Test status
Simulation time 480416550 ps
CPU time 5.46 seconds
Started Jul 07 06:32:47 PM PDT 24
Finished Jul 07 06:32:52 PM PDT 24
Peak memory 223516 kb
Host smart-4ed59802-dca7-4dc8-9cbe-9379992008f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1516443121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1516443121
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1176596187
Short name T744
Test name
Test status
Simulation time 6748880989 ps
CPU time 70.28 seconds
Started Jul 07 06:32:50 PM PDT 24
Finished Jul 07 06:34:00 PM PDT 24
Peak memory 242188 kb
Host smart-d8f392e0-cb48-4659-97d4-be353c3fef27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176596187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1176596187
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1780750370
Short name T468
Test name
Test status
Simulation time 1286282374 ps
CPU time 12.86 seconds
Started Jul 07 06:32:44 PM PDT 24
Finished Jul 07 06:32:57 PM PDT 24
Peak memory 217336 kb
Host smart-05433c87-520a-4aca-9ec0-a48756f30148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780750370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1780750370
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.436779874
Short name T944
Test name
Test status
Simulation time 112819477 ps
CPU time 6.35 seconds
Started Jul 07 06:32:44 PM PDT 24
Finished Jul 07 06:32:50 PM PDT 24
Peak memory 217352 kb
Host smart-23c3e906-1e34-4cc3-8eb1-dec4befee28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436779874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.436779874
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.789112962
Short name T174
Test name
Test status
Simulation time 28642299 ps
CPU time 0.77 seconds
Started Jul 07 06:32:43 PM PDT 24
Finished Jul 07 06:32:44 PM PDT 24
Peak memory 206968 kb
Host smart-f2dcd67b-446a-430d-aed8-eab3ab1ac79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789112962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.789112962
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.149119086
Short name T649
Test name
Test status
Simulation time 1866480928 ps
CPU time 6.56 seconds
Started Jul 07 06:32:48 PM PDT 24
Finished Jul 07 06:32:55 PM PDT 24
Peak memory 233764 kb
Host smart-359021b3-8ef6-4c71-b053-6df5801c7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149119086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.149119086
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2274342962
Short name T134
Test name
Test status
Simulation time 37103020 ps
CPU time 0.75 seconds
Started Jul 07 06:32:56 PM PDT 24
Finished Jul 07 06:32:57 PM PDT 24
Peak memory 205740 kb
Host smart-a1e25a5b-359d-4767-a035-5f39a228f16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274342962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2274342962
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.70745320
Short name T745
Test name
Test status
Simulation time 252693505 ps
CPU time 4.29 seconds
Started Jul 07 06:32:49 PM PDT 24
Finished Jul 07 06:32:54 PM PDT 24
Peak memory 233768 kb
Host smart-26e196c5-78b7-443a-8c29-5b230371ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70745320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.70745320
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.615417634
Short name T1017
Test name
Test status
Simulation time 19523261 ps
CPU time 0.81 seconds
Started Jul 07 06:32:50 PM PDT 24
Finished Jul 07 06:32:51 PM PDT 24
Peak memory 207776 kb
Host smart-0e880243-1120-4e4c-9fda-73e5617b6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615417634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.615417634
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3932979799
Short name T704
Test name
Test status
Simulation time 34867276151 ps
CPU time 41.43 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 251316 kb
Host smart-50b47303-4919-4849-a7dc-2cb81ace3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932979799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3932979799
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1347753336
Short name T969
Test name
Test status
Simulation time 107872851058 ps
CPU time 464.18 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:40:40 PM PDT 24
Peak memory 273780 kb
Host smart-394d7dba-7077-4f4b-97e9-9cfbbc1e4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347753336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1347753336
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4246873816
Short name T865
Test name
Test status
Simulation time 2155754929 ps
CPU time 15.71 seconds
Started Jul 07 06:32:51 PM PDT 24
Finished Jul 07 06:33:07 PM PDT 24
Peak memory 242016 kb
Host smart-fa286d14-f83e-4578-beb7-54f9754c3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246873816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4246873816
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2053992197
Short name T706
Test name
Test status
Simulation time 54031719919 ps
CPU time 52.38 seconds
Started Jul 07 06:32:49 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 250308 kb
Host smart-498fbe62-60bf-44a9-925a-75f57cd9f3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053992197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2053992197
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.341613543
Short name T171
Test name
Test status
Simulation time 384271644 ps
CPU time 4.44 seconds
Started Jul 07 06:32:51 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 233692 kb
Host smart-ffe88c30-bd0f-4330-880c-43bb7f3c2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341613543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.341613543
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4138011182
Short name T776
Test name
Test status
Simulation time 2331957471 ps
CPU time 25.79 seconds
Started Jul 07 06:32:54 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 233848 kb
Host smart-b8175d1f-7fb9-4ad0-b09d-88a4a8cbd208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138011182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4138011182
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2444064226
Short name T989
Test name
Test status
Simulation time 217423001 ps
CPU time 2.26 seconds
Started Jul 07 06:32:51 PM PDT 24
Finished Jul 07 06:32:54 PM PDT 24
Peak memory 233540 kb
Host smart-e2d5e78f-5cc3-440e-a8c7-8fb7097749af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444064226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2444064226
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3262720193
Short name T908
Test name
Test status
Simulation time 6167879087 ps
CPU time 24.85 seconds
Started Jul 07 06:32:53 PM PDT 24
Finished Jul 07 06:33:18 PM PDT 24
Peak memory 242104 kb
Host smart-8bbac557-a4b9-4553-9fa8-092f1f413aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262720193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3262720193
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3509965895
Short name T614
Test name
Test status
Simulation time 431172907 ps
CPU time 5.37 seconds
Started Jul 07 06:32:56 PM PDT 24
Finished Jul 07 06:33:02 PM PDT 24
Peak memory 221656 kb
Host smart-9a41f92f-d95b-4a9b-9494-4af1e9075c47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3509965895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3509965895
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.706215323
Short name T1029
Test name
Test status
Simulation time 8607485434 ps
CPU time 19.98 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:33:16 PM PDT 24
Peak memory 218888 kb
Host smart-2f908641-9698-443b-8871-db56bc8f690f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706215323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.706215323
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.137123620
Short name T697
Test name
Test status
Simulation time 18651321443 ps
CPU time 20.89 seconds
Started Jul 07 06:32:54 PM PDT 24
Finished Jul 07 06:33:15 PM PDT 24
Peak memory 217456 kb
Host smart-d1c4f704-356d-43d9-bae8-f7d5c96d2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137123620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.137123620
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.11945129
Short name T761
Test name
Test status
Simulation time 24788105447 ps
CPU time 11.35 seconds
Started Jul 07 06:32:51 PM PDT 24
Finished Jul 07 06:33:02 PM PDT 24
Peak memory 217536 kb
Host smart-50c43f56-9618-4db3-a669-7c9c0ca2ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11945129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.11945129
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1648444463
Short name T877
Test name
Test status
Simulation time 738961005 ps
CPU time 1.84 seconds
Started Jul 07 06:32:51 PM PDT 24
Finished Jul 07 06:32:53 PM PDT 24
Peak memory 217380 kb
Host smart-17d24b1c-ac22-463e-baf1-e96694f8ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648444463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1648444463
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.915827521
Short name T918
Test name
Test status
Simulation time 94083968 ps
CPU time 0.89 seconds
Started Jul 07 06:32:50 PM PDT 24
Finished Jul 07 06:32:51 PM PDT 24
Peak memory 207196 kb
Host smart-c6ac519e-ec7b-495a-b789-d26762a3adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915827521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.915827521
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3007962146
Short name T608
Test name
Test status
Simulation time 16532786080 ps
CPU time 16.29 seconds
Started Jul 07 06:32:52 PM PDT 24
Finished Jul 07 06:33:09 PM PDT 24
Peak memory 233836 kb
Host smart-c9bafc64-6bf3-4d53-b08d-ee662704994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007962146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3007962146
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1035586056
Short name T660
Test name
Test status
Simulation time 12669645 ps
CPU time 0.75 seconds
Started Jul 07 06:33:01 PM PDT 24
Finished Jul 07 06:33:02 PM PDT 24
Peak memory 205792 kb
Host smart-0115ac23-818a-48f6-9ce8-7d12f2e1aa0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035586056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1035586056
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1282072219
Short name T988
Test name
Test status
Simulation time 3417279525 ps
CPU time 20.99 seconds
Started Jul 07 06:32:58 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 233880 kb
Host smart-7c9848c4-20cb-4d5d-b394-1d15e0af9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282072219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1282072219
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2689210202
Short name T411
Test name
Test status
Simulation time 28236314 ps
CPU time 0.75 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 207848 kb
Host smart-1f4d8859-7ff7-484c-aa3c-d427ca898e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689210202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2689210202
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.451560465
Short name T723
Test name
Test status
Simulation time 81478728919 ps
CPU time 297.47 seconds
Started Jul 07 06:32:59 PM PDT 24
Finished Jul 07 06:37:56 PM PDT 24
Peak memory 256532 kb
Host smart-16dde984-9044-439d-a262-1216d81c41b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451560465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.451560465
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.91393280
Short name T10
Test name
Test status
Simulation time 4317274738 ps
CPU time 6.94 seconds
Started Jul 07 06:32:58 PM PDT 24
Finished Jul 07 06:33:05 PM PDT 24
Peak memory 219024 kb
Host smart-8c8f0ebb-71e8-474e-9e5f-6a1dce912b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91393280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.91393280
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1095806990
Short name T775
Test name
Test status
Simulation time 13808021054 ps
CPU time 115.4 seconds
Started Jul 07 06:33:03 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 254084 kb
Host smart-47f8657e-d2cb-4764-8879-4255f9d98ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095806990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1095806990
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3041712303
Short name T837
Test name
Test status
Simulation time 2791955761 ps
CPU time 6.28 seconds
Started Jul 07 06:32:59 PM PDT 24
Finished Jul 07 06:33:05 PM PDT 24
Peak memory 225632 kb
Host smart-af39c1b8-02b2-41e9-bc98-fec07f19f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041712303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3041712303
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2983365650
Short name T976
Test name
Test status
Simulation time 23216911553 ps
CPU time 163.93 seconds
Started Jul 07 06:32:56 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 250400 kb
Host smart-b2527bb0-b0cb-402a-8c66-d00b76c3b16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983365650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2983365650
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1068162721
Short name T848
Test name
Test status
Simulation time 505331754 ps
CPU time 5.08 seconds
Started Jul 07 06:32:57 PM PDT 24
Finished Jul 07 06:33:03 PM PDT 24
Peak memory 225516 kb
Host smart-23b43765-29a7-4ba4-8072-da115e29ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068162721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1068162721
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3223994334
Short name T259
Test name
Test status
Simulation time 5023862576 ps
CPU time 10.66 seconds
Started Jul 07 06:32:57 PM PDT 24
Finished Jul 07 06:33:08 PM PDT 24
Peak memory 233840 kb
Host smart-a4f48e85-f5a7-4374-8ab4-1b37343432bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223994334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3223994334
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1000179496
Short name T716
Test name
Test status
Simulation time 177562900 ps
CPU time 3.54 seconds
Started Jul 07 06:32:56 PM PDT 24
Finished Jul 07 06:32:59 PM PDT 24
Peak memory 233720 kb
Host smart-95a1be25-f752-4b21-89a8-52bfb27297b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000179496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1000179496
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4193347914
Short name T705
Test name
Test status
Simulation time 8839368923 ps
CPU time 7.65 seconds
Started Jul 07 06:32:58 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 235724 kb
Host smart-e87fe4bf-c870-4635-a20d-f15267e4fae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193347914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4193347914
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4020557141
Short name T529
Test name
Test status
Simulation time 125565238 ps
CPU time 3.88 seconds
Started Jul 07 06:32:58 PM PDT 24
Finished Jul 07 06:33:02 PM PDT 24
Peak memory 221568 kb
Host smart-4a469e83-81b3-4abb-8bec-43daddc6d161
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020557141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4020557141
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.403083555
Short name T286
Test name
Test status
Simulation time 35821988656 ps
CPU time 403.97 seconds
Started Jul 07 06:33:01 PM PDT 24
Finished Jul 07 06:39:46 PM PDT 24
Peak memory 274112 kb
Host smart-ffa85d5d-9333-4078-974c-00f0369f8763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403083555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.403083555
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1669988874
Short name T487
Test name
Test status
Simulation time 918238527 ps
CPU time 6.38 seconds
Started Jul 07 06:32:53 PM PDT 24
Finished Jul 07 06:33:00 PM PDT 24
Peak memory 217512 kb
Host smart-a87ebdb7-ec09-4451-88ce-899e9889b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669988874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1669988874
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2175045808
Short name T361
Test name
Test status
Simulation time 93934048 ps
CPU time 1.44 seconds
Started Jul 07 06:32:54 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 208892 kb
Host smart-dd026417-42d3-433b-9be5-ddd71908c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175045808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2175045808
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.242086221
Short name T357
Test name
Test status
Simulation time 171252852 ps
CPU time 5.01 seconds
Started Jul 07 06:32:57 PM PDT 24
Finished Jul 07 06:33:02 PM PDT 24
Peak memory 217412 kb
Host smart-19fd83fd-0d52-48f2-bcac-e28efa71ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242086221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.242086221
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2203891838
Short name T414
Test name
Test status
Simulation time 43528381 ps
CPU time 0.83 seconds
Started Jul 07 06:32:55 PM PDT 24
Finished Jul 07 06:32:56 PM PDT 24
Peak memory 206924 kb
Host smart-fdba0f8a-0666-4e6d-9ec0-a0e8830d2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203891838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2203891838
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2984791487
Short name T494
Test name
Test status
Simulation time 2811336292 ps
CPU time 3.05 seconds
Started Jul 07 06:32:58 PM PDT 24
Finished Jul 07 06:33:01 PM PDT 24
Peak memory 237744 kb
Host smart-5b21e611-4814-41ee-8138-e50027c5f552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984791487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2984791487
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4018879649
Short name T998
Test name
Test status
Simulation time 13486872 ps
CPU time 0.7 seconds
Started Jul 07 06:33:05 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 205796 kb
Host smart-c42bb897-7833-498c-bb09-048045868832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018879649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4018879649
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1332668150
Short name T202
Test name
Test status
Simulation time 140124709 ps
CPU time 2.28 seconds
Started Jul 07 06:33:05 PM PDT 24
Finished Jul 07 06:33:07 PM PDT 24
Peak memory 233752 kb
Host smart-5d9d19e5-ae8e-471b-8009-d93899683309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332668150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1332668150
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3748600558
Short name T9
Test name
Test status
Simulation time 16611816 ps
CPU time 0.78 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:05 PM PDT 24
Peak memory 207544 kb
Host smart-5d9c3482-7742-4d4e-b41c-0da99266733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748600558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3748600558
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1940695163
Short name T210
Test name
Test status
Simulation time 9500308357 ps
CPU time 67.44 seconds
Started Jul 07 06:33:06 PM PDT 24
Finished Jul 07 06:34:13 PM PDT 24
Peak memory 234220 kb
Host smart-95d25f82-a011-439d-b5d4-0e704ed9bd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940695163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1940695163
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2108990033
Short name T900
Test name
Test status
Simulation time 4951954108 ps
CPU time 62.59 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:34:07 PM PDT 24
Peak memory 250676 kb
Host smart-89c8cdf9-c0b6-464c-838d-08c37e1c2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108990033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2108990033
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.744066512
Short name T623
Test name
Test status
Simulation time 5246056559 ps
CPU time 52.07 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:57 PM PDT 24
Peak memory 252256 kb
Host smart-e01cb555-03f3-45fd-bb9b-2b03b2ce4536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744066512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.744066512
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3902668319
Short name T427
Test name
Test status
Simulation time 201975457 ps
CPU time 5.38 seconds
Started Jul 07 06:33:08 PM PDT 24
Finished Jul 07 06:33:13 PM PDT 24
Peak memory 234452 kb
Host smart-21bb0203-efeb-4b24-a605-721f7c54689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902668319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3902668319
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4233945135
Short name T284
Test name
Test status
Simulation time 134319428950 ps
CPU time 125.14 seconds
Started Jul 07 06:33:05 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 250240 kb
Host smart-690dd05a-a16f-48b5-a2a4-18353bed2eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233945135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4233945135
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2138041191
Short name T591
Test name
Test status
Simulation time 841072525 ps
CPU time 5.55 seconds
Started Jul 07 06:33:03 PM PDT 24
Finished Jul 07 06:33:09 PM PDT 24
Peak memory 233748 kb
Host smart-d222d331-f055-44e4-9c24-83be7349634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138041191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2138041191
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1771053598
Short name T597
Test name
Test status
Simulation time 547058043 ps
CPU time 5.65 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:10 PM PDT 24
Peak memory 225624 kb
Host smart-078a4738-b588-452b-bebb-d256f70b3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771053598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1771053598
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1084750235
Short name T954
Test name
Test status
Simulation time 518021131 ps
CPU time 3.68 seconds
Started Jul 07 06:33:02 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 233772 kb
Host smart-5a5b9f88-e9dd-4668-92ac-6dbe256750f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084750235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1084750235
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3851807647
Short name T675
Test name
Test status
Simulation time 196863824 ps
CPU time 3.62 seconds
Started Jul 07 06:33:02 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 233804 kb
Host smart-e2d67877-c9f1-44e8-a3eb-2e21a7481e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851807647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3851807647
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3185060841
Short name T764
Test name
Test status
Simulation time 522395862 ps
CPU time 3.96 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:08 PM PDT 24
Peak memory 224096 kb
Host smart-4e1a34fe-4455-4fd4-8f72-9bed08b03622
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185060841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3185060841
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3367266785
Short name T181
Test name
Test status
Simulation time 3148196050 ps
CPU time 51.85 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:56 PM PDT 24
Peak memory 225860 kb
Host smart-94be9fe0-fb6b-4e2c-830b-e9c3a1a2d0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367266785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3367266785
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3492890207
Short name T509
Test name
Test status
Simulation time 5150297884 ps
CPU time 26.9 seconds
Started Jul 07 06:33:01 PM PDT 24
Finished Jul 07 06:33:28 PM PDT 24
Peak memory 217520 kb
Host smart-30dc9632-0c27-4fa7-8f9a-f37e99a39fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492890207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3492890207
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4101390376
Short name T827
Test name
Test status
Simulation time 19718035988 ps
CPU time 24.05 seconds
Started Jul 07 06:33:00 PM PDT 24
Finished Jul 07 06:33:24 PM PDT 24
Peak memory 217512 kb
Host smart-28a99c26-86cb-4ee7-8a36-34b4fe55ca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101390376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4101390376
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.835300875
Short name T587
Test name
Test status
Simulation time 20851236 ps
CPU time 0.96 seconds
Started Jul 07 06:33:04 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 208196 kb
Host smart-4ce07659-e8fa-4c24-ad3e-17c888e6611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835300875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.835300875
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2406800307
Short name T1018
Test name
Test status
Simulation time 36555342 ps
CPU time 0.72 seconds
Started Jul 07 06:33:03 PM PDT 24
Finished Jul 07 06:33:04 PM PDT 24
Peak memory 206948 kb
Host smart-17caae26-86ec-476e-a93a-dfd693d69d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406800307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2406800307
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2772174448
Short name T1004
Test name
Test status
Simulation time 128271535 ps
CPU time 2.51 seconds
Started Jul 07 06:33:02 PM PDT 24
Finished Jul 07 06:33:05 PM PDT 24
Peak memory 225576 kb
Host smart-5feef824-7949-4c88-812b-cbea0a2dd9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772174448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2772174448
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1818850985
Short name T1000
Test name
Test status
Simulation time 67033303 ps
CPU time 0.71 seconds
Started Jul 07 06:33:13 PM PDT 24
Finished Jul 07 06:33:14 PM PDT 24
Peak memory 206360 kb
Host smart-735d67ec-934a-4413-9f96-97cfde9ce6ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818850985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1818850985
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3635572096
Short name T942
Test name
Test status
Simulation time 81276467 ps
CPU time 2.4 seconds
Started Jul 07 06:33:08 PM PDT 24
Finished Jul 07 06:33:11 PM PDT 24
Peak memory 225536 kb
Host smart-083a8789-946a-4cb8-91f5-16d9b3589f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635572096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3635572096
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4000511039
Short name T1014
Test name
Test status
Simulation time 81499883 ps
CPU time 0.77 seconds
Started Jul 07 06:33:05 PM PDT 24
Finished Jul 07 06:33:06 PM PDT 24
Peak memory 207516 kb
Host smart-a0e3fa99-1f47-42b1-b5ba-1cd6dedbf753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000511039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4000511039
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1654565881
Short name T429
Test name
Test status
Simulation time 2212999513 ps
CPU time 9.69 seconds
Started Jul 07 06:33:09 PM PDT 24
Finished Jul 07 06:33:19 PM PDT 24
Peak memory 242348 kb
Host smart-46b88873-35ff-4617-ba92-78752b04d644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654565881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1654565881
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3391621103
Short name T731
Test name
Test status
Simulation time 1855733551 ps
CPU time 38.06 seconds
Started Jul 07 06:33:14 PM PDT 24
Finished Jul 07 06:33:52 PM PDT 24
Peak memory 250020 kb
Host smart-893b9214-d3b1-4aa1-a89a-afa64210d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391621103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3391621103
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3377457560
Short name T14
Test name
Test status
Simulation time 387851698 ps
CPU time 7.99 seconds
Started Jul 07 06:33:09 PM PDT 24
Finished Jul 07 06:33:18 PM PDT 24
Peak memory 233784 kb
Host smart-b8255bba-7b10-4288-ba39-0bad592af16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377457560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3377457560
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3500303463
Short name T679
Test name
Test status
Simulation time 16285200810 ps
CPU time 25.01 seconds
Started Jul 07 06:33:07 PM PDT 24
Finished Jul 07 06:33:33 PM PDT 24
Peak memory 238000 kb
Host smart-079acf4c-17ba-486a-8986-758b2c99d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500303463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3500303463
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2000370456
Short name T217
Test name
Test status
Simulation time 2697332865 ps
CPU time 24.5 seconds
Started Jul 07 06:33:07 PM PDT 24
Finished Jul 07 06:33:32 PM PDT 24
Peak memory 233872 kb
Host smart-de470978-66a6-4a19-b37b-d58b7a6423fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000370456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2000370456
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2745621989
Short name T627
Test name
Test status
Simulation time 1830498969 ps
CPU time 17.75 seconds
Started Jul 07 06:33:08 PM PDT 24
Finished Jul 07 06:33:26 PM PDT 24
Peak memory 233716 kb
Host smart-f172a85c-53e8-4d80-a8bc-2b35c028fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745621989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2745621989
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2272849844
Short name T281
Test name
Test status
Simulation time 953615016 ps
CPU time 5.64 seconds
Started Jul 07 06:33:10 PM PDT 24
Finished Jul 07 06:33:16 PM PDT 24
Peak memory 240288 kb
Host smart-e359d385-3539-4d93-975c-2024f184b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272849844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2272849844
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3192520236
Short name T819
Test name
Test status
Simulation time 1195561447 ps
CPU time 4.94 seconds
Started Jul 07 06:33:10 PM PDT 24
Finished Jul 07 06:33:15 PM PDT 24
Peak memory 225592 kb
Host smart-8330780d-abbd-4a34-9020-96c2e3e93042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192520236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3192520236
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2541298230
Short name T418
Test name
Test status
Simulation time 564881262 ps
CPU time 5.75 seconds
Started Jul 07 06:33:10 PM PDT 24
Finished Jul 07 06:33:16 PM PDT 24
Peak memory 219808 kb
Host smart-d8baa241-454e-4803-b1c9-13bd380017ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541298230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2541298230
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2797343278
Short name T798
Test name
Test status
Simulation time 58352882 ps
CPU time 1.08 seconds
Started Jul 07 06:33:13 PM PDT 24
Finished Jul 07 06:33:14 PM PDT 24
Peak memory 207828 kb
Host smart-69ca1364-f513-4e98-97ce-c7dd4a86da40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797343278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2797343278
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3287195503
Short name T344
Test name
Test status
Simulation time 2287430986 ps
CPU time 14.36 seconds
Started Jul 07 06:33:09 PM PDT 24
Finished Jul 07 06:33:24 PM PDT 24
Peak memory 217500 kb
Host smart-2cff4842-40af-455c-af0a-a90e7164df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287195503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3287195503
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3970441684
Short name T880
Test name
Test status
Simulation time 4782571962 ps
CPU time 4.14 seconds
Started Jul 07 06:33:13 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 217536 kb
Host smart-9d9de534-7093-4fcf-a65e-31c67e44bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970441684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3970441684
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2176923895
Short name T545
Test name
Test status
Simulation time 24030249 ps
CPU time 0.71 seconds
Started Jul 07 06:33:12 PM PDT 24
Finished Jul 07 06:33:13 PM PDT 24
Peak memory 206972 kb
Host smart-3ea85144-0a2b-402f-a818-1a0bd8b0fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176923895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2176923895
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3222107455
Short name T1031
Test name
Test status
Simulation time 1030565562 ps
CPU time 0.84 seconds
Started Jul 07 06:33:09 PM PDT 24
Finished Jul 07 06:33:10 PM PDT 24
Peak memory 206980 kb
Host smart-defb7830-0cf9-4d55-a870-fd621bac0ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222107455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3222107455
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1577599715
Short name T303
Test name
Test status
Simulation time 658676813 ps
CPU time 9.32 seconds
Started Jul 07 06:33:10 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 235080 kb
Host smart-8310383e-0d22-4bd6-930e-21a1ec66bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577599715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1577599715
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2993907538
Short name T483
Test name
Test status
Simulation time 137649872 ps
CPU time 0.72 seconds
Started Jul 07 06:33:21 PM PDT 24
Finished Jul 07 06:33:22 PM PDT 24
Peak memory 206432 kb
Host smart-6c3e67bf-c96c-4ad8-a2f1-1d23fec3f042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993907538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2993907538
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4143056741
Short name T79
Test name
Test status
Simulation time 4308011184 ps
CPU time 18.59 seconds
Started Jul 07 06:33:15 PM PDT 24
Finished Jul 07 06:33:34 PM PDT 24
Peak memory 233972 kb
Host smart-e9b67482-6c0d-4c81-881b-5d8044ee9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143056741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4143056741
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3292961286
Short name T821
Test name
Test status
Simulation time 15990237 ps
CPU time 0.8 seconds
Started Jul 07 06:33:11 PM PDT 24
Finished Jul 07 06:33:12 PM PDT 24
Peak memory 207456 kb
Host smart-8c59d785-fa1f-4399-b72b-5eb2d4c30947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292961286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3292961286
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3490866262
Short name T657
Test name
Test status
Simulation time 11281079010 ps
CPU time 115.91 seconds
Started Jul 07 06:33:15 PM PDT 24
Finished Jul 07 06:35:11 PM PDT 24
Peak memory 250280 kb
Host smart-50120c5b-0825-451a-b3a5-48a54ee15bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490866262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3490866262
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4140206089
Short name T956
Test name
Test status
Simulation time 18976259028 ps
CPU time 166.36 seconds
Started Jul 07 06:33:19 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 266788 kb
Host smart-d7021c1f-f8c3-4a8e-943b-df40854466f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140206089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4140206089
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4245494896
Short name T240
Test name
Test status
Simulation time 2297669722 ps
CPU time 45.02 seconds
Started Jul 07 06:33:19 PM PDT 24
Finished Jul 07 06:34:04 PM PDT 24
Peak memory 250284 kb
Host smart-94e4e346-0fac-41f3-8385-b1beddbf612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245494896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4245494896
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3272356692
Short name T333
Test name
Test status
Simulation time 457157150 ps
CPU time 5.3 seconds
Started Jul 07 06:33:17 PM PDT 24
Finished Jul 07 06:33:22 PM PDT 24
Peak memory 234832 kb
Host smart-8a0fd6a9-fa62-4867-9f2c-67db147f5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272356692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3272356692
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1159012917
Short name T755
Test name
Test status
Simulation time 5192949808 ps
CPU time 13.24 seconds
Started Jul 07 06:33:13 PM PDT 24
Finished Jul 07 06:33:27 PM PDT 24
Peak memory 233988 kb
Host smart-8a5b4aba-d66b-4743-8a9e-74beb0c88b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159012917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1159012917
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2913944101
Short name T399
Test name
Test status
Simulation time 60113862037 ps
CPU time 48.87 seconds
Started Jul 07 06:33:13 PM PDT 24
Finished Jul 07 06:34:02 PM PDT 24
Peak memory 234916 kb
Host smart-4b6c568f-d93d-47c4-95d2-5649f0fcd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913944101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2913944101
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3151512240
Short name T228
Test name
Test status
Simulation time 5212688555 ps
CPU time 12.91 seconds
Started Jul 07 06:33:12 PM PDT 24
Finished Jul 07 06:33:25 PM PDT 24
Peak memory 225592 kb
Host smart-1e7f21aa-1f6f-46da-8d57-d773bf2ec5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151512240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3151512240
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2677066851
Short name T610
Test name
Test status
Simulation time 12450613821 ps
CPU time 21.38 seconds
Started Jul 07 06:33:12 PM PDT 24
Finished Jul 07 06:33:34 PM PDT 24
Peak memory 242304 kb
Host smart-1ecc77d1-c9c8-4137-8f20-c8c4619a12bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677066851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2677066851
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.24362341
Short name T435
Test name
Test status
Simulation time 954318973 ps
CPU time 4.19 seconds
Started Jul 07 06:33:15 PM PDT 24
Finished Jul 07 06:33:20 PM PDT 24
Peak memory 221484 kb
Host smart-797c3179-2a15-4a15-82c3-edf7ea784b2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=24362341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direc
t.24362341
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1218402562
Short name T824
Test name
Test status
Simulation time 4199276663 ps
CPU time 80.6 seconds
Started Jul 07 06:33:23 PM PDT 24
Finished Jul 07 06:34:44 PM PDT 24
Peak memory 250316 kb
Host smart-fea9e0d9-8353-4171-a5a4-f7c0dfe8dcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218402562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1218402562
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2943838695
Short name T919
Test name
Test status
Simulation time 10824547 ps
CPU time 0.72 seconds
Started Jul 07 06:33:15 PM PDT 24
Finished Jul 07 06:33:16 PM PDT 24
Peak memory 206636 kb
Host smart-bab4d1fa-1231-4cce-ad75-8982e4f77f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943838695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2943838695
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3208756740
Short name T949
Test name
Test status
Simulation time 1524014632 ps
CPU time 5.03 seconds
Started Jul 07 06:33:12 PM PDT 24
Finished Jul 07 06:33:17 PM PDT 24
Peak memory 217268 kb
Host smart-6d0f2a58-615b-47a5-b935-1406f6941c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208756740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3208756740
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1000377135
Short name T606
Test name
Test status
Simulation time 184742983 ps
CPU time 3.51 seconds
Started Jul 07 06:33:12 PM PDT 24
Finished Jul 07 06:33:16 PM PDT 24
Peak memory 217376 kb
Host smart-c2bbc1a5-2f33-4d32-b20c-397d587cbd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000377135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1000377135
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3667698992
Short name T737
Test name
Test status
Simulation time 90911817 ps
CPU time 0.83 seconds
Started Jul 07 06:33:11 PM PDT 24
Finished Jul 07 06:33:12 PM PDT 24
Peak memory 206968 kb
Host smart-eaa0b367-24b1-4352-a226-74ad94748126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667698992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3667698992
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.683381084
Short name T1019
Test name
Test status
Simulation time 9883904624 ps
CPU time 10.75 seconds
Started Jul 07 06:33:14 PM PDT 24
Finished Jul 07 06:33:25 PM PDT 24
Peak memory 233792 kb
Host smart-c37840c9-7a29-4232-bbe5-d21c33cee8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683381084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.683381084
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1802781543
Short name T907
Test name
Test status
Simulation time 12302090 ps
CPU time 0.71 seconds
Started Jul 07 06:33:28 PM PDT 24
Finished Jul 07 06:33:30 PM PDT 24
Peak memory 205796 kb
Host smart-c833f5fc-a029-4873-9540-f7e75ff1001a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802781543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1802781543
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2903639096
Short name T1007
Test name
Test status
Simulation time 715379776 ps
CPU time 3.61 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:30 PM PDT 24
Peak memory 225588 kb
Host smart-e09f979a-ec71-431d-a8d2-065f6a0181eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903639096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2903639096
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.444305922
Short name T526
Test name
Test status
Simulation time 26325242 ps
CPU time 0.77 seconds
Started Jul 07 06:33:18 PM PDT 24
Finished Jul 07 06:33:19 PM PDT 24
Peak memory 207848 kb
Host smart-edf551e4-a246-4481-9f84-c73f8314c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444305922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.444305922
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3966452742
Short name T973
Test name
Test status
Simulation time 3809651295 ps
CPU time 56.59 seconds
Started Jul 07 06:33:27 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 250268 kb
Host smart-1e29e20f-d894-413f-873b-7ada6b5432ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966452742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3966452742
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3043887755
Short name T223
Test name
Test status
Simulation time 21511920310 ps
CPU time 218.73 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:37:05 PM PDT 24
Peak memory 250416 kb
Host smart-09cc5c5f-8478-4214-8ab4-a69cf74ccba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043887755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3043887755
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3225610598
Short name T300
Test name
Test status
Simulation time 87409997324 ps
CPU time 380.17 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:39:47 PM PDT 24
Peak memory 253548 kb
Host smart-8e7c77a4-49f9-4baa-bed8-9358e19796f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225610598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3225610598
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.654181015
Short name T859
Test name
Test status
Simulation time 5092789987 ps
CPU time 20.08 seconds
Started Jul 07 06:33:23 PM PDT 24
Finished Jul 07 06:33:43 PM PDT 24
Peak memory 225680 kb
Host smart-14a7ca77-e20b-40af-93b7-1c1775f2b1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654181015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.654181015
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3608496458
Short name T727
Test name
Test status
Simulation time 74859365633 ps
CPU time 174.66 seconds
Started Jul 07 06:33:27 PM PDT 24
Finished Jul 07 06:36:22 PM PDT 24
Peak memory 250272 kb
Host smart-57b2c447-e85e-4352-ab4f-57231c0bba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608496458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3608496458
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3026401630
Short name T800
Test name
Test status
Simulation time 784624965 ps
CPU time 10.56 seconds
Started Jul 07 06:33:23 PM PDT 24
Finished Jul 07 06:33:34 PM PDT 24
Peak memory 225520 kb
Host smart-569ff4b5-8e4f-4f8f-8659-8af61b3906c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026401630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3026401630
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2752742008
Short name T950
Test name
Test status
Simulation time 127272329 ps
CPU time 2.14 seconds
Started Jul 07 06:33:23 PM PDT 24
Finished Jul 07 06:33:25 PM PDT 24
Peak memory 227892 kb
Host smart-d3afaa73-f7e5-41aa-bcc6-ece2eeb3bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752742008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2752742008
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1598900739
Short name T746
Test name
Test status
Simulation time 2977761217 ps
CPU time 11.23 seconds
Started Jul 07 06:33:22 PM PDT 24
Finished Jul 07 06:33:34 PM PDT 24
Peak memory 225660 kb
Host smart-e917d677-7653-40a8-9dc0-c8c175d519a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598900739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1598900739
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.83259784
Short name T773
Test name
Test status
Simulation time 41640885631 ps
CPU time 31.16 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:58 PM PDT 24
Peak memory 251732 kb
Host smart-9844511b-9fb9-41a5-a187-52b345235696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83259784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.83259784
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1624715040
Short name T152
Test name
Test status
Simulation time 4650850836 ps
CPU time 10.54 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 221312 kb
Host smart-75e7a742-a145-440a-84e6-75d110610780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1624715040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1624715040
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3695841828
Short name T661
Test name
Test status
Simulation time 7981698777 ps
CPU time 16.77 seconds
Started Jul 07 06:33:20 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 221152 kb
Host smart-a723c64c-369f-4c89-8a45-adf314e2e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695841828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3695841828
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2501932461
Short name T502
Test name
Test status
Simulation time 43247605 ps
CPU time 0.66 seconds
Started Jul 07 06:33:18 PM PDT 24
Finished Jul 07 06:33:19 PM PDT 24
Peak memory 206640 kb
Host smart-005a621e-a37c-44dc-8be9-67a2c0bb4b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501932461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2501932461
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3601085446
Short name T831
Test name
Test status
Simulation time 115472838 ps
CPU time 0.93 seconds
Started Jul 07 06:33:25 PM PDT 24
Finished Jul 07 06:33:26 PM PDT 24
Peak memory 208956 kb
Host smart-036ab6a8-8f57-4782-b2e2-71c8e93d0ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601085446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3601085446
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1801314600
Short name T93
Test name
Test status
Simulation time 49899521 ps
CPU time 0.76 seconds
Started Jul 07 06:33:20 PM PDT 24
Finished Jul 07 06:33:21 PM PDT 24
Peak memory 206920 kb
Host smart-fee12e9f-47d1-4720-a180-e8306f69cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801314600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1801314600
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1541939602
Short name T851
Test name
Test status
Simulation time 765290233 ps
CPU time 5.68 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:32 PM PDT 24
Peak memory 225536 kb
Host smart-f8bc5572-908a-45f7-beb2-6020ef259a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541939602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1541939602
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.516228974
Short name T135
Test name
Test status
Simulation time 48565406 ps
CPU time 0.75 seconds
Started Jul 07 06:33:31 PM PDT 24
Finished Jul 07 06:33:31 PM PDT 24
Peak memory 206332 kb
Host smart-5b6780f1-2b36-4eec-bc4f-cd1a95ce453c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516228974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.516228974
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3514793782
Short name T943
Test name
Test status
Simulation time 618703945 ps
CPU time 5.36 seconds
Started Jul 07 06:33:30 PM PDT 24
Finished Jul 07 06:33:36 PM PDT 24
Peak memory 233724 kb
Host smart-a232869d-4d32-4b83-8c19-135370450deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514793782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3514793782
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2136450262
Short name T913
Test name
Test status
Simulation time 30965968 ps
CPU time 0.77 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:33:30 PM PDT 24
Peak memory 206496 kb
Host smart-d8c66f5e-1a57-4030-af75-f838c09ac714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136450262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2136450262
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1077020413
Short name T881
Test name
Test status
Simulation time 5538874820 ps
CPU time 70.73 seconds
Started Jul 07 06:33:30 PM PDT 24
Finished Jul 07 06:34:41 PM PDT 24
Peak memory 250212 kb
Host smart-278afafe-9e8e-4ff0-89a5-1ee9d5ffffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077020413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1077020413
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3492896815
Short name T309
Test name
Test status
Simulation time 60911924880 ps
CPU time 591.72 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:43:21 PM PDT 24
Peak memory 252788 kb
Host smart-0f16d9bb-ef9c-4058-8255-a81d3a475514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492896815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3492896815
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.742799218
Short name T314
Test name
Test status
Simulation time 43516600134 ps
CPU time 485.33 seconds
Started Jul 07 06:33:30 PM PDT 24
Finished Jul 07 06:41:35 PM PDT 24
Peak memory 268056 kb
Host smart-82d3a76a-6acb-4449-9238-1ccce17cd449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742799218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.742799218
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.725444952
Short name T566
Test name
Test status
Simulation time 117380394 ps
CPU time 5.58 seconds
Started Jul 07 06:33:31 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 235776 kb
Host smart-21610165-8062-4cf9-9429-ffca304d6ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725444952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.725444952
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1426604111
Short name T299
Test name
Test status
Simulation time 76848246191 ps
CPU time 120.49 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:35:30 PM PDT 24
Peak memory 233908 kb
Host smart-5e99227e-2ff1-4007-bea7-f901ae2ace0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426604111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1426604111
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3385721647
Short name T224
Test name
Test status
Simulation time 551680448 ps
CPU time 5.83 seconds
Started Jul 07 06:33:27 PM PDT 24
Finished Jul 07 06:33:33 PM PDT 24
Peak memory 225512 kb
Host smart-6b3ee8f8-4897-4476-8c2f-2099aaccacd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385721647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3385721647
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2632350086
Short name T856
Test name
Test status
Simulation time 8632903703 ps
CPU time 20.23 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:47 PM PDT 24
Peak memory 241612 kb
Host smart-1731e12c-eb68-4548-90b7-4bc56e8a6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632350086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2632350086
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1694343431
Short name T688
Test name
Test status
Simulation time 113522340 ps
CPU time 2.48 seconds
Started Jul 07 06:33:30 PM PDT 24
Finished Jul 07 06:33:33 PM PDT 24
Peak memory 225560 kb
Host smart-0a442a31-8be4-4bf2-9f5d-a3fd3d3297a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694343431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1694343431
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4133779419
Short name T899
Test name
Test status
Simulation time 10538588572 ps
CPU time 9.29 seconds
Started Jul 07 06:33:30 PM PDT 24
Finished Jul 07 06:33:39 PM PDT 24
Peak memory 233860 kb
Host smart-3d81412e-0871-486b-8e60-db5a9b015cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133779419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4133779419
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2230437437
Short name T734
Test name
Test status
Simulation time 993911921 ps
CPU time 12.76 seconds
Started Jul 07 06:33:35 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 222608 kb
Host smart-ccbd4285-3e1c-400f-9e1c-10f856a2fb1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2230437437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2230437437
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4152196560
Short name T542
Test name
Test status
Simulation time 6512897293 ps
CPU time 43.69 seconds
Started Jul 07 06:33:28 PM PDT 24
Finished Jul 07 06:34:13 PM PDT 24
Peak memory 258624 kb
Host smart-17db3a6f-f487-4532-96de-a8e89f144ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152196560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4152196560
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.901753369
Short name T559
Test name
Test status
Simulation time 13475566335 ps
CPU time 36.55 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:34:06 PM PDT 24
Peak memory 221784 kb
Host smart-b4357b1e-be2d-4f2d-8ff5-634f95a3c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901753369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.901753369
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4068718877
Short name T25
Test name
Test status
Simulation time 5027292154 ps
CPU time 17.11 seconds
Started Jul 07 06:33:27 PM PDT 24
Finished Jul 07 06:33:44 PM PDT 24
Peak memory 217464 kb
Host smart-6aa5427a-f609-48d9-a31a-031ce1a5c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068718877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4068718877
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1650811272
Short name T978
Test name
Test status
Simulation time 172422533 ps
CPU time 1 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:33:30 PM PDT 24
Peak memory 207652 kb
Host smart-4c541226-2180-4892-b885-7e139ab89257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650811272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1650811272
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2379945840
Short name T829
Test name
Test status
Simulation time 182084642 ps
CPU time 1 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:27 PM PDT 24
Peak memory 208272 kb
Host smart-2b6fcaa8-1fef-4a1e-ba7d-0768e8a93d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379945840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2379945840
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2250140122
Short name T246
Test name
Test status
Simulation time 12925005317 ps
CPU time 12.14 seconds
Started Jul 07 06:33:26 PM PDT 24
Finished Jul 07 06:33:39 PM PDT 24
Peak memory 225668 kb
Host smart-eaa8c740-d354-4f85-bf6c-cfc758085c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250140122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2250140122
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.203556764
Short name T567
Test name
Test status
Simulation time 32653400 ps
CPU time 0.7 seconds
Started Jul 07 06:33:36 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 206316 kb
Host smart-7bab3f00-e244-40c9-8429-abbca2a01e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203556764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.203556764
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3403295806
Short name T668
Test name
Test status
Simulation time 1080694246 ps
CPU time 7.28 seconds
Started Jul 07 06:33:35 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 233764 kb
Host smart-661b1a28-28d1-4e33-9d21-5cb46fe9b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403295806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3403295806
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1509890328
Short name T928
Test name
Test status
Simulation time 112827425 ps
CPU time 0.75 seconds
Started Jul 07 06:33:35 PM PDT 24
Finished Jul 07 06:33:36 PM PDT 24
Peak memory 207828 kb
Host smart-82d9531a-dfe8-43dc-b975-6f5d8334dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509890328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1509890328
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.455771069
Short name T233
Test name
Test status
Simulation time 28684457609 ps
CPU time 206.1 seconds
Started Jul 07 06:33:37 PM PDT 24
Finished Jul 07 06:37:03 PM PDT 24
Peak memory 250252 kb
Host smart-b36e1914-d899-4039-a418-b53cc4070eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455771069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.455771069
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2077185879
Short name T590
Test name
Test status
Simulation time 20792836128 ps
CPU time 49.37 seconds
Started Jul 07 06:33:38 PM PDT 24
Finished Jul 07 06:34:28 PM PDT 24
Peak memory 225824 kb
Host smart-50f00545-27dd-462c-ac3a-1b556e46d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077185879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2077185879
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.608741471
Short name T1021
Test name
Test status
Simulation time 4775115831 ps
CPU time 16.77 seconds
Started Jul 07 06:33:33 PM PDT 24
Finished Jul 07 06:33:50 PM PDT 24
Peak memory 233864 kb
Host smart-c6580f5f-dbee-48cf-b9a9-849b58562568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608741471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.608741471
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.973179453
Short name T897
Test name
Test status
Simulation time 3717010649 ps
CPU time 16.23 seconds
Started Jul 07 06:33:36 PM PDT 24
Finished Jul 07 06:33:52 PM PDT 24
Peak memory 239392 kb
Host smart-0ff39e6c-0f25-4308-ae38-a5e9dbee24d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973179453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.973179453
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2251201371
Short name T906
Test name
Test status
Simulation time 225519368 ps
CPU time 6.51 seconds
Started Jul 07 06:33:33 PM PDT 24
Finished Jul 07 06:33:39 PM PDT 24
Peak memory 233804 kb
Host smart-7a1f18ea-b0e1-4457-a9c4-50ca168c9424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251201371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2251201371
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2519300466
Short name T820
Test name
Test status
Simulation time 9130010372 ps
CPU time 47.63 seconds
Started Jul 07 06:33:34 PM PDT 24
Finished Jul 07 06:34:22 PM PDT 24
Peak memory 233928 kb
Host smart-58538e70-9118-46f9-a80b-3f2d8544e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519300466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2519300466
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.723316208
Short name T326
Test name
Test status
Simulation time 800105055 ps
CPU time 2.55 seconds
Started Jul 07 06:33:34 PM PDT 24
Finished Jul 07 06:33:37 PM PDT 24
Peak memory 225532 kb
Host smart-a6aa19fe-990e-431b-b5ff-5c703d317515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723316208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.723316208
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2106080055
Short name T767
Test name
Test status
Simulation time 1109527977 ps
CPU time 3.99 seconds
Started Jul 07 06:33:35 PM PDT 24
Finished Jul 07 06:33:39 PM PDT 24
Peak memory 233784 kb
Host smart-c0ad94a9-6c1f-4269-8165-0ae23c10801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106080055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2106080055
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3494245184
Short name T854
Test name
Test status
Simulation time 556693961 ps
CPU time 4.05 seconds
Started Jul 07 06:33:38 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 221468 kb
Host smart-02ae5697-1209-49c4-b250-02e0a604b5f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3494245184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3494245184
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.834801185
Short name T110
Test name
Test status
Simulation time 5834389767 ps
CPU time 11.57 seconds
Started Jul 07 06:33:29 PM PDT 24
Finished Jul 07 06:33:41 PM PDT 24
Peak memory 217532 kb
Host smart-ad92b153-940b-4eb0-9975-b72ec34435f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834801185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.834801185
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1769224574
Short name T672
Test name
Test status
Simulation time 27517176091 ps
CPU time 16.44 seconds
Started Jul 07 06:33:32 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 217552 kb
Host smart-7810b263-9c23-4066-8736-729898fec7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769224574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1769224574
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4024769842
Short name T28
Test name
Test status
Simulation time 525098152 ps
CPU time 4.59 seconds
Started Jul 07 06:33:34 PM PDT 24
Finished Jul 07 06:33:38 PM PDT 24
Peak memory 217360 kb
Host smart-2c08768d-339c-4952-afa6-04da974a0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024769842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4024769842
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.62402285
Short name T388
Test name
Test status
Simulation time 63148044 ps
CPU time 0.88 seconds
Started Jul 07 06:33:34 PM PDT 24
Finished Jul 07 06:33:35 PM PDT 24
Peak memory 207940 kb
Host smart-3ceef934-6c34-477b-b56b-c502da03c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62402285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.62402285
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3976859064
Short name T683
Test name
Test status
Simulation time 3609230290 ps
CPU time 8.28 seconds
Started Jul 07 06:33:33 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 233892 kb
Host smart-2d4392c4-1433-48e9-8a2f-74ac85d9648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976859064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3976859064
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.752334992
Short name T905
Test name
Test status
Simulation time 21192436 ps
CPU time 0.72 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:33:44 PM PDT 24
Peak memory 206752 kb
Host smart-44884672-e734-4eb3-9089-f701e7124924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752334992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.752334992
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3266010287
Short name T360
Test name
Test status
Simulation time 2357938296 ps
CPU time 7.41 seconds
Started Jul 07 06:33:39 PM PDT 24
Finished Jul 07 06:33:47 PM PDT 24
Peak memory 233888 kb
Host smart-987250c2-faef-4856-af4b-10693a04e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266010287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3266010287
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3033244873
Short name T580
Test name
Test status
Simulation time 67883936 ps
CPU time 0.76 seconds
Started Jul 07 06:33:39 PM PDT 24
Finished Jul 07 06:33:40 PM PDT 24
Peak memory 206476 kb
Host smart-aa3f64bd-eb6f-4d8e-a44a-01af0919e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033244873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3033244873
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.685743194
Short name T434
Test name
Test status
Simulation time 2946775993 ps
CPU time 62.18 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:34:43 PM PDT 24
Peak memory 256152 kb
Host smart-233e7ede-12d1-4d84-aa0d-18ed159f1f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685743194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.685743194
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.918756988
Short name T789
Test name
Test status
Simulation time 537868083 ps
CPU time 10.69 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:33:51 PM PDT 24
Peak memory 225516 kb
Host smart-7fc767ef-8c71-4bf4-b33c-a7c5b7995daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918756988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.918756988
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.4236937102
Short name T197
Test name
Test status
Simulation time 2078881160 ps
CPU time 43.69 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 250224 kb
Host smart-69887773-1685-4e53-b726-e48b155f9997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236937102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.4236937102
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3790866334
Short name T743
Test name
Test status
Simulation time 502083312 ps
CPU time 6.41 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:33:47 PM PDT 24
Peak memory 225604 kb
Host smart-7f1017c4-65da-4d52-bce5-6f778ddfe55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790866334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3790866334
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3337276898
Short name T801
Test name
Test status
Simulation time 836237158 ps
CPU time 5.8 seconds
Started Jul 07 06:33:42 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 225556 kb
Host smart-22042df5-2853-490f-b1da-220ea02a75f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337276898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3337276898
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1156311735
Short name T757
Test name
Test status
Simulation time 1278688482 ps
CPU time 6.69 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:33:50 PM PDT 24
Peak memory 233716 kb
Host smart-327f0ecf-c413-48e5-b296-ec7c499c9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156311735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1156311735
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.582396676
Short name T803
Test name
Test status
Simulation time 7572387331 ps
CPU time 12.33 seconds
Started Jul 07 06:33:39 PM PDT 24
Finished Jul 07 06:33:51 PM PDT 24
Peak memory 233832 kb
Host smart-766e6253-daeb-4bbb-a913-376077f9b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582396676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.582396676
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2128097786
Short name T645
Test name
Test status
Simulation time 2640261924 ps
CPU time 8.16 seconds
Started Jul 07 06:33:44 PM PDT 24
Finished Jul 07 06:33:52 PM PDT 24
Peak memory 220544 kb
Host smart-6ee9ba0f-942c-4195-b178-bde990d5f4bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2128097786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2128097786
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2072241566
Short name T598
Test name
Test status
Simulation time 3746773381 ps
CPU time 63.89 seconds
Started Jul 07 06:33:42 PM PDT 24
Finished Jul 07 06:34:46 PM PDT 24
Peak memory 250432 kb
Host smart-f6b0d79b-26cc-4d53-bc7c-b84db0ff1988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072241566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2072241566
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3390193456
Short name T611
Test name
Test status
Simulation time 979937618 ps
CPU time 8.08 seconds
Started Jul 07 06:33:39 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 217548 kb
Host smart-1a978d74-bf9c-45a8-a3e5-c09d40464d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390193456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3390193456
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2497270872
Short name T843
Test name
Test status
Simulation time 5487973234 ps
CPU time 5.86 seconds
Started Jul 07 06:33:36 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 217480 kb
Host smart-f109b9ce-dc16-4459-8776-ae059e737c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497270872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2497270872
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2814209475
Short name T772
Test name
Test status
Simulation time 101203051 ps
CPU time 1.31 seconds
Started Jul 07 06:33:44 PM PDT 24
Finished Jul 07 06:33:46 PM PDT 24
Peak memory 209180 kb
Host smart-32f6750b-14e7-4bda-af11-6c54190ec20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814209475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2814209475
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3601400578
Short name T59
Test name
Test status
Simulation time 93541045 ps
CPU time 0.96 seconds
Started Jul 07 06:33:40 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 206952 kb
Host smart-488a6629-2977-4aef-a6cd-1adac1cb89e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601400578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3601400578
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.493670422
Short name T60
Test name
Test status
Simulation time 41330696 ps
CPU time 2.81 seconds
Started Jul 07 06:33:42 PM PDT 24
Finished Jul 07 06:33:45 PM PDT 24
Peak memory 233816 kb
Host smart-32c2df19-98a2-46b9-a579-ad9c197698d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493670422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.493670422
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2976726430
Short name T65
Test name
Test status
Simulation time 46440513 ps
CPU time 0.69 seconds
Started Jul 07 06:29:32 PM PDT 24
Finished Jul 07 06:29:33 PM PDT 24
Peak memory 206388 kb
Host smart-19c2fea6-1da8-4013-b1a8-f7430f747802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976726430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
976726430
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.156517207
Short name T78
Test name
Test status
Simulation time 239276640 ps
CPU time 3.65 seconds
Started Jul 07 06:29:27 PM PDT 24
Finished Jul 07 06:29:30 PM PDT 24
Peak memory 225596 kb
Host smart-2008f8c4-4d51-4106-8dd9-dc1b8dfb0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156517207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.156517207
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1839163818
Short name T367
Test name
Test status
Simulation time 26391625 ps
CPU time 0.76 seconds
Started Jul 07 06:29:20 PM PDT 24
Finished Jul 07 06:29:21 PM PDT 24
Peak memory 207500 kb
Host smart-27792280-94c1-4513-8ce0-53a2abf9bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839163818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1839163818
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.684981568
Short name T540
Test name
Test status
Simulation time 5671522235 ps
CPU time 45.52 seconds
Started Jul 07 06:29:30 PM PDT 24
Finished Jul 07 06:30:15 PM PDT 24
Peak memory 233920 kb
Host smart-7c7ba4f5-2a62-47b6-8cb2-6729445152d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684981568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.684981568
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.406995619
Short name T432
Test name
Test status
Simulation time 88570066247 ps
CPU time 169.9 seconds
Started Jul 07 06:29:30 PM PDT 24
Finished Jul 07 06:32:20 PM PDT 24
Peak memory 264264 kb
Host smart-5ac260be-dedb-49a6-8fa6-7e2770d62ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406995619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.406995619
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.111068523
Short name T653
Test name
Test status
Simulation time 1662814028 ps
CPU time 16.31 seconds
Started Jul 07 06:29:27 PM PDT 24
Finished Jul 07 06:29:43 PM PDT 24
Peak memory 233740 kb
Host smart-a22217b6-89d9-4ed9-a653-805e32d7bf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111068523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.111068523
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3005536476
Short name T622
Test name
Test status
Simulation time 2311177594 ps
CPU time 18.54 seconds
Started Jul 07 06:29:31 PM PDT 24
Finished Jul 07 06:29:50 PM PDT 24
Peak memory 250284 kb
Host smart-1e2da222-bd2b-495b-ab69-b482281eae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005536476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3005536476
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.161177125
Short name T715
Test name
Test status
Simulation time 316551191 ps
CPU time 3.14 seconds
Started Jul 07 06:29:27 PM PDT 24
Finished Jul 07 06:29:30 PM PDT 24
Peak memory 233716 kb
Host smart-0264ae7c-3105-4175-8ac7-f66d193230b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161177125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.161177125
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.974418085
Short name T438
Test name
Test status
Simulation time 31865423 ps
CPU time 2.13 seconds
Started Jul 07 06:29:24 PM PDT 24
Finished Jul 07 06:29:26 PM PDT 24
Peak memory 225272 kb
Host smart-50f425e5-ea69-46c0-b2ff-e7f2740bf290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974418085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.974418085
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1716166668
Short name T959
Test name
Test status
Simulation time 33764146 ps
CPU time 1.07 seconds
Started Jul 07 06:29:21 PM PDT 24
Finished Jul 07 06:29:22 PM PDT 24
Peak memory 217644 kb
Host smart-c1b45744-4dcb-4e15-ab13-c7c3f7117b4b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716166668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1716166668
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1141497264
Short name T253
Test name
Test status
Simulation time 181353826 ps
CPU time 4.34 seconds
Started Jul 07 06:29:24 PM PDT 24
Finished Jul 07 06:29:29 PM PDT 24
Peak memory 233792 kb
Host smart-d7b9cc8d-8af4-4b95-80e2-a33f7c161989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141497264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1141497264
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2940638914
Short name T457
Test name
Test status
Simulation time 4579393225 ps
CPU time 5.34 seconds
Started Jul 07 06:29:22 PM PDT 24
Finished Jul 07 06:29:28 PM PDT 24
Peak memory 225712 kb
Host smart-00284a74-a2b3-4a9e-925d-758c4d79332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940638914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2940638914
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2136841035
Short name T544
Test name
Test status
Simulation time 1771362643 ps
CPU time 3.96 seconds
Started Jul 07 06:29:26 PM PDT 24
Finished Jul 07 06:29:30 PM PDT 24
Peak memory 220248 kb
Host smart-efb11475-67b5-475e-a7bf-ed6dec3f8998
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2136841035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2136841035
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1068711722
Short name T71
Test name
Test status
Simulation time 361398242 ps
CPU time 1.13 seconds
Started Jul 07 06:29:29 PM PDT 24
Finished Jul 07 06:29:31 PM PDT 24
Peak memory 236356 kb
Host smart-dc573d67-3735-4899-bfc0-be255dab0cef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068711722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1068711722
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.184382107
Short name T952
Test name
Test status
Simulation time 4561190772 ps
CPU time 111.17 seconds
Started Jul 07 06:29:31 PM PDT 24
Finished Jul 07 06:31:22 PM PDT 24
Peak memory 267004 kb
Host smart-dd7947d8-4882-436a-9744-e605b3433830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184382107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.184382107
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.975626663
Short name T351
Test name
Test status
Simulation time 4811949909 ps
CPU time 24.94 seconds
Started Jul 07 06:29:23 PM PDT 24
Finished Jul 07 06:29:48 PM PDT 24
Peak memory 217460 kb
Host smart-505761bd-b8a4-44ef-a040-f7276c1972e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975626663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.975626663
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3266932748
Short name T712
Test name
Test status
Simulation time 4624847718 ps
CPU time 1.53 seconds
Started Jul 07 06:29:20 PM PDT 24
Finished Jul 07 06:29:22 PM PDT 24
Peak memory 209036 kb
Host smart-f09c24f0-99fc-41fb-8cb8-46570e36106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266932748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3266932748
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.991661870
Short name T23
Test name
Test status
Simulation time 290969111 ps
CPU time 2.63 seconds
Started Jul 07 06:29:27 PM PDT 24
Finished Jul 07 06:29:30 PM PDT 24
Peak memory 217384 kb
Host smart-7329d5ae-46fc-4aad-a5b2-4cd95dea9da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991661870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.991661870
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3849588067
Short name T923
Test name
Test status
Simulation time 245748453 ps
CPU time 0.92 seconds
Started Jul 07 06:29:27 PM PDT 24
Finished Jul 07 06:29:28 PM PDT 24
Peak memory 206964 kb
Host smart-2ddcfd52-e0ba-40de-95b2-ca8be7e4f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849588067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3849588067
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3259107658
Short name T499
Test name
Test status
Simulation time 1375153761 ps
CPU time 4.94 seconds
Started Jul 07 06:29:28 PM PDT 24
Finished Jul 07 06:29:33 PM PDT 24
Peak memory 225540 kb
Host smart-4065fa56-1b23-4be9-b1e5-33cb2ee67139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259107658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3259107658
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.519065439
Short name T834
Test name
Test status
Simulation time 19650903 ps
CPU time 0.69 seconds
Started Jul 07 06:33:47 PM PDT 24
Finished Jul 07 06:33:48 PM PDT 24
Peak memory 205772 kb
Host smart-d65a8b00-95bb-4efc-bccd-b3400e663702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519065439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.519065439
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.153512751
Short name T968
Test name
Test status
Simulation time 448163174 ps
CPU time 5.84 seconds
Started Jul 07 06:33:48 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 233768 kb
Host smart-c27ec4e5-de42-4515-aaae-eb85d4c4f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153512751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.153512751
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.19094970
Short name T476
Test name
Test status
Simulation time 171806781 ps
CPU time 0.78 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:33:44 PM PDT 24
Peak memory 207548 kb
Host smart-affdee21-64bc-4dbb-a471-f256054c5dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19094970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.19094970
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2132179369
Short name T893
Test name
Test status
Simulation time 6375082175 ps
CPU time 39.88 seconds
Started Jul 07 06:33:46 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 237628 kb
Host smart-b9053fec-ce0b-4d78-8d26-240eaf76df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132179369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2132179369
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.509601349
Short name T54
Test name
Test status
Simulation time 59971439915 ps
CPU time 292.06 seconds
Started Jul 07 06:33:46 PM PDT 24
Finished Jul 07 06:38:39 PM PDT 24
Peak memory 257560 kb
Host smart-6d161340-0e7e-44e5-81cb-4ab09a26229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509601349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.509601349
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.528998481
Short name T337
Test name
Test status
Simulation time 784832721 ps
CPU time 6.03 seconds
Started Jul 07 06:33:47 PM PDT 24
Finished Jul 07 06:33:53 PM PDT 24
Peak memory 233784 kb
Host smart-0f7119e1-6c1f-4ea3-9fb2-3e391086686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528998481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.528998481
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.869632106
Short name T389
Test name
Test status
Simulation time 6559049749 ps
CPU time 38.37 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:34:28 PM PDT 24
Peak memory 250276 kb
Host smart-8516d48e-7563-4dbb-aee7-eac0ceb02d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869632106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.869632106
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.662645653
Short name T178
Test name
Test status
Simulation time 755532527 ps
CPU time 9 seconds
Started Jul 07 06:33:45 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 219880 kb
Host smart-76f862d3-a137-4632-b8e5-52de969f493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662645653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.662645653
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2167146191
Short name T236
Test name
Test status
Simulation time 830064625 ps
CPU time 9.76 seconds
Started Jul 07 06:33:46 PM PDT 24
Finished Jul 07 06:33:56 PM PDT 24
Peak memory 233600 kb
Host smart-e3e93876-6eb3-495a-8098-5c386bea815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167146191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2167146191
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3935347833
Short name T288
Test name
Test status
Simulation time 21563745039 ps
CPU time 28.58 seconds
Started Jul 07 06:33:42 PM PDT 24
Finished Jul 07 06:34:11 PM PDT 24
Peak memory 225644 kb
Host smart-41a150b5-34e5-41b8-81c3-f8eb01d9de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935347833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3935347833
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2274885491
Short name T1025
Test name
Test status
Simulation time 12933285730 ps
CPU time 12.59 seconds
Started Jul 07 06:33:46 PM PDT 24
Finished Jul 07 06:33:59 PM PDT 24
Peak memory 225692 kb
Host smart-abd950ee-cc6b-4d39-8f71-0a3e8102f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274885491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2274885491
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.578645738
Short name T596
Test name
Test status
Simulation time 2984962229 ps
CPU time 9.4 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:34:00 PM PDT 24
Peak memory 224116 kb
Host smart-5a13f8c9-8548-4415-8b66-96c75837669e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=578645738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.578645738
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.170708722
Short name T22
Test name
Test status
Simulation time 33885015465 ps
CPU time 64.83 seconds
Started Jul 07 06:33:47 PM PDT 24
Finished Jul 07 06:34:52 PM PDT 24
Peak memory 240212 kb
Host smart-af81418b-c341-42e2-b348-40a77dc7fae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170708722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.170708722
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2000907783
Short name T442
Test name
Test status
Simulation time 142992503 ps
CPU time 2.08 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:33:46 PM PDT 24
Peak memory 217616 kb
Host smart-b1e5b918-ffaa-47e1-b99d-963635b5eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000907783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2000907783
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.97036005
Short name T364
Test name
Test status
Simulation time 34397631 ps
CPU time 0.69 seconds
Started Jul 07 06:33:42 PM PDT 24
Finished Jul 07 06:33:43 PM PDT 24
Peak memory 206620 kb
Host smart-425a9f71-cd33-4586-9cec-e140e0155b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97036005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.97036005
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4241918534
Short name T673
Test name
Test status
Simulation time 475807760 ps
CPU time 1.56 seconds
Started Jul 07 06:33:43 PM PDT 24
Finished Jul 07 06:33:44 PM PDT 24
Peak memory 217392 kb
Host smart-dd2ac69a-0332-46c9-992e-8d53e3d098af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241918534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4241918534
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2004720928
Short name T373
Test name
Test status
Simulation time 35750020 ps
CPU time 0.9 seconds
Started Jul 07 06:33:44 PM PDT 24
Finished Jul 07 06:33:45 PM PDT 24
Peak memory 207968 kb
Host smart-5f059108-ae99-4825-947f-552683a94f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004720928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2004720928
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.661800553
Short name T749
Test name
Test status
Simulation time 205947725 ps
CPU time 4.26 seconds
Started Jul 07 06:33:45 PM PDT 24
Finished Jul 07 06:33:50 PM PDT 24
Peak memory 225496 kb
Host smart-7a2168a3-0e67-4e85-9ab9-2300a2faedf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661800553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.661800553
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3593261127
Short name T412
Test name
Test status
Simulation time 13283851 ps
CPU time 0.73 seconds
Started Jul 07 06:33:59 PM PDT 24
Finished Jul 07 06:34:01 PM PDT 24
Peak memory 205828 kb
Host smart-45b33180-dd8b-4e2c-8762-4e32b57e28d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593261127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3593261127
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3450141300
Short name T583
Test name
Test status
Simulation time 71643530 ps
CPU time 2.67 seconds
Started Jul 07 06:33:51 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 233792 kb
Host smart-490efe24-9062-49db-a8be-f11283b17ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450141300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3450141300
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3035802535
Short name T593
Test name
Test status
Simulation time 39956099 ps
CPU time 0.77 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:33:51 PM PDT 24
Peak memory 207520 kb
Host smart-eb64379b-53b6-4ea9-9d9b-496fe1470b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035802535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3035802535
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1655478948
Short name T84
Test name
Test status
Simulation time 9713904492 ps
CPU time 48.27 seconds
Started Jul 07 06:33:55 PM PDT 24
Finished Jul 07 06:34:44 PM PDT 24
Peak memory 253468 kb
Host smart-237f3e5b-cd3b-4133-b7aa-ef260cd291f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655478948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1655478948
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2566044320
Short name T1005
Test name
Test status
Simulation time 88399417226 ps
CPU time 142.92 seconds
Started Jul 07 06:33:54 PM PDT 24
Finished Jul 07 06:36:17 PM PDT 24
Peak memory 250408 kb
Host smart-be8e0579-01ac-4809-9c86-c583794f9e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566044320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2566044320
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.31081765
Short name T11
Test name
Test status
Simulation time 6558332766 ps
CPU time 28.43 seconds
Started Jul 07 06:33:52 PM PDT 24
Finished Jul 07 06:34:20 PM PDT 24
Peak memory 225692 kb
Host smart-85be916e-c5e2-452b-b906-26fe59d08275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31081765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.31081765
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.509330906
Short name T195
Test name
Test status
Simulation time 12102973101 ps
CPU time 91.2 seconds
Started Jul 07 06:33:55 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 250256 kb
Host smart-d00ca212-9911-4596-a703-a5612b885faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509330906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.509330906
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1018130549
Short name T492
Test name
Test status
Simulation time 411863426 ps
CPU time 2.51 seconds
Started Jul 07 06:33:52 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 225544 kb
Host smart-216df256-ef21-44cc-ae42-ab8ca243f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018130549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1018130549
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3375739969
Short name T280
Test name
Test status
Simulation time 453679706 ps
CPU time 7.02 seconds
Started Jul 07 06:34:01 PM PDT 24
Finished Jul 07 06:34:10 PM PDT 24
Peak memory 225548 kb
Host smart-53483432-2ac9-461b-b910-6126438c02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375739969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3375739969
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.189509224
Short name T601
Test name
Test status
Simulation time 9946037800 ps
CPU time 30.11 seconds
Started Jul 07 06:33:59 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 233904 kb
Host smart-e483a4ef-0e18-4ce8-9d3e-50b846240c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189509224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.189509224
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3386705426
Short name T662
Test name
Test status
Simulation time 2747493725 ps
CPU time 4.62 seconds
Started Jul 07 06:34:01 PM PDT 24
Finished Jul 07 06:34:08 PM PDT 24
Peak memory 233920 kb
Host smart-5afefc14-9af9-427c-bbf4-952f522fc6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386705426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3386705426
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3708237565
Short name T768
Test name
Test status
Simulation time 103510507 ps
CPU time 3.09 seconds
Started Jul 07 06:33:55 PM PDT 24
Finished Jul 07 06:33:59 PM PDT 24
Peak memory 220364 kb
Host smart-fc3f68fe-b9b9-4a07-a439-1976a93cb23e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3708237565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3708237565
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4080610136
Short name T325
Test name
Test status
Simulation time 14456816092 ps
CPU time 69.38 seconds
Started Jul 07 06:33:58 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 258496 kb
Host smart-59564aac-4c29-4ee9-9271-9753437942ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080610136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4080610136
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3711684291
Short name T425
Test name
Test status
Simulation time 2763118709 ps
CPU time 16.82 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:34:07 PM PDT 24
Peak memory 217472 kb
Host smart-159b8dd9-689f-488f-8196-cfcba8859598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711684291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3711684291
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.270730381
Short name T961
Test name
Test status
Simulation time 2291999314 ps
CPU time 6.24 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:33:56 PM PDT 24
Peak memory 217416 kb
Host smart-4de42d02-d7b1-419b-946a-6252cecece24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270730381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.270730381
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1494640277
Short name T455
Test name
Test status
Simulation time 451199816 ps
CPU time 4.05 seconds
Started Jul 07 06:33:50 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 217296 kb
Host smart-c42a3b84-cdec-442a-8d47-c7cdd5624dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494640277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1494640277
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1024116015
Short name T431
Test name
Test status
Simulation time 65789072 ps
CPU time 0.88 seconds
Started Jul 07 06:33:53 PM PDT 24
Finished Jul 07 06:33:54 PM PDT 24
Peak memory 206960 kb
Host smart-376c659f-c10d-4f92-879a-b4820d6405b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024116015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1024116015
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2684722815
Short name T792
Test name
Test status
Simulation time 67915696725 ps
CPU time 23.91 seconds
Started Jul 07 06:33:55 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 233940 kb
Host smart-3097d097-1853-4379-a37c-2ab172dc03c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684722815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2684722815
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3458304772
Short name T138
Test name
Test status
Simulation time 12397031 ps
CPU time 0.72 seconds
Started Jul 07 06:34:02 PM PDT 24
Finished Jul 07 06:34:04 PM PDT 24
Peak memory 205796 kb
Host smart-749e97ef-7fba-42aa-baba-035d83499474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458304772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3458304772
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.341871765
Short name T846
Test name
Test status
Simulation time 2261608604 ps
CPU time 11.67 seconds
Started Jul 07 06:34:04 PM PDT 24
Finished Jul 07 06:34:16 PM PDT 24
Peak memory 225692 kb
Host smart-3639b9bd-ab4e-4c5b-82c5-2091dcc67b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341871765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.341871765
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2499059691
Short name T498
Test name
Test status
Simulation time 42227928 ps
CPU time 0.78 seconds
Started Jul 07 06:33:56 PM PDT 24
Finished Jul 07 06:33:57 PM PDT 24
Peak memory 207552 kb
Host smart-030c673f-9511-465b-855e-34fc01db787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499059691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2499059691
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1756906115
Short name T251
Test name
Test status
Simulation time 76912315881 ps
CPU time 127.44 seconds
Started Jul 07 06:34:04 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 238692 kb
Host smart-6c19c781-9664-4892-a63c-2071abc286d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756906115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1756906115
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1001186583
Short name T32
Test name
Test status
Simulation time 56499319 ps
CPU time 0.97 seconds
Started Jul 07 06:34:02 PM PDT 24
Finished Jul 07 06:34:05 PM PDT 24
Peak memory 219136 kb
Host smart-d57b5e59-f15a-4e34-85a2-25b615e81ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001186583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1001186583
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4165989948
Short name T340
Test name
Test status
Simulation time 12580701618 ps
CPU time 59.15 seconds
Started Jul 07 06:33:56 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 234052 kb
Host smart-6be71888-7da7-41ac-b1cc-34823cd72048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165989948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4165989948
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.786407954
Short name T4
Test name
Test status
Simulation time 349961618 ps
CPU time 3.48 seconds
Started Jul 07 06:34:01 PM PDT 24
Finished Jul 07 06:34:07 PM PDT 24
Peak memory 234664 kb
Host smart-f3f1ffc5-ab30-4b94-8c92-dfd46f24bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786407954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.786407954
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2135122028
Short name T307
Test name
Test status
Simulation time 7056842113 ps
CPU time 94.85 seconds
Started Jul 07 06:33:58 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 256552 kb
Host smart-e819366e-1173-4dd2-9489-7d1e51cef825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135122028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2135122028
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1594459337
Short name T294
Test name
Test status
Simulation time 478929685 ps
CPU time 9.6 seconds
Started Jul 07 06:33:56 PM PDT 24
Finished Jul 07 06:34:06 PM PDT 24
Peak memory 225544 kb
Host smart-711cefc5-001a-4bcb-ad8e-2e1f27848328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594459337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1594459337
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1261037865
Short name T505
Test name
Test status
Simulation time 1976085102 ps
CPU time 15.54 seconds
Started Jul 07 06:33:54 PM PDT 24
Finished Jul 07 06:34:10 PM PDT 24
Peak memory 234056 kb
Host smart-7b108eaa-499b-4a0a-884a-47c628f11c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261037865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1261037865
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.925289436
Short name T235
Test name
Test status
Simulation time 3245080623 ps
CPU time 5.88 seconds
Started Jul 07 06:33:53 PM PDT 24
Finished Jul 07 06:33:59 PM PDT 24
Peak memory 233908 kb
Host smart-f49a8c0d-7337-4f5a-a545-880a29358525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925289436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.925289436
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.607650469
Short name T264
Test name
Test status
Simulation time 4092074507 ps
CPU time 7.35 seconds
Started Jul 07 06:33:59 PM PDT 24
Finished Jul 07 06:34:08 PM PDT 24
Peak memory 225716 kb
Host smart-625a0e24-9a18-49c8-8f90-1af781dd5862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607650469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.607650469
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2131238299
Short name T599
Test name
Test status
Simulation time 9076492791 ps
CPU time 10.88 seconds
Started Jul 07 06:34:00 PM PDT 24
Finished Jul 07 06:34:12 PM PDT 24
Peak memory 222760 kb
Host smart-ab35e5bd-eb38-48a0-9b35-485f4e6f9b8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131238299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2131238299
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2481951688
Short name T936
Test name
Test status
Simulation time 365800530 ps
CPU time 1.16 seconds
Started Jul 07 06:34:00 PM PDT 24
Finished Jul 07 06:34:04 PM PDT 24
Peak memory 207940 kb
Host smart-53b86092-922f-456d-b6ca-97090eef51e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481951688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2481951688
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3841472713
Short name T527
Test name
Test status
Simulation time 3220315677 ps
CPU time 8.14 seconds
Started Jul 07 06:33:54 PM PDT 24
Finished Jul 07 06:34:02 PM PDT 24
Peak memory 220840 kb
Host smart-de3c3b25-ad8f-4243-8792-72f427e80fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841472713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3841472713
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3077921886
Short name T91
Test name
Test status
Simulation time 708100146 ps
CPU time 1.79 seconds
Started Jul 07 06:33:59 PM PDT 24
Finished Jul 07 06:34:03 PM PDT 24
Peak memory 208944 kb
Host smart-9fedac0e-c3d2-45b7-bf61-201e491ff1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077921886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3077921886
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3585796130
Short name T422
Test name
Test status
Simulation time 104473244 ps
CPU time 3.05 seconds
Started Jul 07 06:33:55 PM PDT 24
Finished Jul 07 06:33:58 PM PDT 24
Peak memory 217304 kb
Host smart-514d691f-0ffb-40fe-a66f-f02d2493e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585796130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3585796130
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2309743326
Short name T565
Test name
Test status
Simulation time 142961612 ps
CPU time 0.76 seconds
Started Jul 07 06:34:02 PM PDT 24
Finished Jul 07 06:34:04 PM PDT 24
Peak memory 206956 kb
Host smart-13dfdd6c-4e50-4356-8c1a-d5afa4f0309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309743326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2309743326
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2968656861
Short name T218
Test name
Test status
Simulation time 3517206106 ps
CPU time 7.86 seconds
Started Jul 07 06:33:58 PM PDT 24
Finished Jul 07 06:34:07 PM PDT 24
Peak memory 225620 kb
Host smart-506860c0-a828-4c23-82c5-06caacf1bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968656861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2968656861
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3097712766
Short name T839
Test name
Test status
Simulation time 32920113 ps
CPU time 0.74 seconds
Started Jul 07 06:34:14 PM PDT 24
Finished Jul 07 06:34:17 PM PDT 24
Peak memory 206344 kb
Host smart-14e99489-9378-4314-b37e-6f11f7c800d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097712766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3097712766
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3964348858
Short name T929
Test name
Test status
Simulation time 854513546 ps
CPU time 10.44 seconds
Started Jul 07 06:34:04 PM PDT 24
Finished Jul 07 06:34:15 PM PDT 24
Peak memory 225820 kb
Host smart-0146397a-7a72-45a3-a9fc-293641bdfb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964348858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3964348858
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3992623847
Short name T718
Test name
Test status
Simulation time 15611257 ps
CPU time 0.77 seconds
Started Jul 07 06:34:03 PM PDT 24
Finished Jul 07 06:34:05 PM PDT 24
Peak memory 207536 kb
Host smart-8f253675-f299-450a-99fa-1c62c6793072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992623847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3992623847
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2294428727
Short name T532
Test name
Test status
Simulation time 49836890 ps
CPU time 0.76 seconds
Started Jul 07 06:34:08 PM PDT 24
Finished Jul 07 06:34:09 PM PDT 24
Peak memory 216876 kb
Host smart-decc7d98-a0e2-4fe6-bf37-a5b56f6ee8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294428727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2294428727
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2462581753
Short name T1002
Test name
Test status
Simulation time 214272718005 ps
CPU time 555.3 seconds
Started Jul 07 06:34:13 PM PDT 24
Finished Jul 07 06:43:31 PM PDT 24
Peak memory 267800 kb
Host smart-93b6e29a-c9cd-4b61-a281-8622005db23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462581753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2462581753
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.493622437
Short name T941
Test name
Test status
Simulation time 149010991127 ps
CPU time 109.91 seconds
Started Jul 07 06:34:15 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 250236 kb
Host smart-9fb16d22-ae64-4d6f-971b-6bd82065db6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493622437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.493622437
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4223422500
Short name T73
Test name
Test status
Simulation time 1256222163 ps
CPU time 21.47 seconds
Started Jul 07 06:34:07 PM PDT 24
Finished Jul 07 06:34:29 PM PDT 24
Peak memory 236208 kb
Host smart-58fc9c99-e729-41af-bcf4-d7da767c743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223422500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4223422500
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2724361845
Short name T464
Test name
Test status
Simulation time 10686615422 ps
CPU time 75.66 seconds
Started Jul 07 06:34:12 PM PDT 24
Finished Jul 07 06:35:30 PM PDT 24
Peak memory 250304 kb
Host smart-7124817a-47cd-4300-aeeb-ea8ab9bd826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724361845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2724361845
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4016767118
Short name T550
Test name
Test status
Simulation time 5265407790 ps
CPU time 46.01 seconds
Started Jul 07 06:34:04 PM PDT 24
Finished Jul 07 06:34:51 PM PDT 24
Peak memory 233844 kb
Host smart-8db0980e-5746-4a2e-962f-bff62f4bae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016767118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4016767118
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.562266393
Short name T252
Test name
Test status
Simulation time 2035487577 ps
CPU time 24.59 seconds
Started Jul 07 06:34:05 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 233784 kb
Host smart-930ecf24-d0c7-4f8e-82df-4585667b9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562266393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.562266393
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.769190440
Short name T568
Test name
Test status
Simulation time 12284633570 ps
CPU time 14.2 seconds
Started Jul 07 06:34:05 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 233868 kb
Host smart-7df3964f-4bb6-486c-85bd-4cf22c0f803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769190440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.769190440
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2145622476
Short name T182
Test name
Test status
Simulation time 6780543226 ps
CPU time 8.6 seconds
Started Jul 07 06:34:09 PM PDT 24
Finished Jul 07 06:34:18 PM PDT 24
Peak memory 225720 kb
Host smart-365a7624-e2c1-4b6b-bd37-eb87fd8240b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145622476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2145622476
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1466837885
Short name T674
Test name
Test status
Simulation time 1268592003 ps
CPU time 3.72 seconds
Started Jul 07 06:34:09 PM PDT 24
Finished Jul 07 06:34:13 PM PDT 24
Peak memory 220008 kb
Host smart-54d6692d-ef0d-40d0-a18a-61c0b17d19d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1466837885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1466837885
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1084199911
Short name T555
Test name
Test status
Simulation time 2601368774 ps
CPU time 60.22 seconds
Started Jul 07 06:34:09 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 253192 kb
Host smart-f7fd9c9c-aa81-4903-8938-6a59cd44d739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084199911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1084199911
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3809359414
Short name T343
Test name
Test status
Simulation time 2950201371 ps
CPU time 23.29 seconds
Started Jul 07 06:34:02 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 217736 kb
Host smart-772f738d-2d24-4ccb-9cee-021861a3e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809359414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3809359414
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3193315186
Short name T618
Test name
Test status
Simulation time 17560365499 ps
CPU time 14.23 seconds
Started Jul 07 06:34:01 PM PDT 24
Finished Jul 07 06:34:18 PM PDT 24
Peak memory 217516 kb
Host smart-3fcd9ecf-554c-4973-8a93-0f87144e73f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193315186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3193315186
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3670912710
Short name T635
Test name
Test status
Simulation time 212809563 ps
CPU time 1.53 seconds
Started Jul 07 06:34:06 PM PDT 24
Finished Jul 07 06:34:08 PM PDT 24
Peak memory 217380 kb
Host smart-5d266b3a-d771-4df4-8442-efd33e77c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670912710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3670912710
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.55322127
Short name T972
Test name
Test status
Simulation time 102370471 ps
CPU time 0.87 seconds
Started Jul 07 06:33:59 PM PDT 24
Finished Jul 07 06:34:02 PM PDT 24
Peak memory 206980 kb
Host smart-94949baa-26d0-455a-a1ee-d4b9953fd1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55322127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.55322127
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3504393423
Short name T277
Test name
Test status
Simulation time 433739164 ps
CPU time 8.74 seconds
Started Jul 07 06:34:04 PM PDT 24
Finished Jul 07 06:34:13 PM PDT 24
Peak memory 240992 kb
Host smart-ba37616c-7b36-451e-b426-8c5270a1187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504393423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3504393423
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.529472742
Short name T437
Test name
Test status
Simulation time 58491929 ps
CPU time 0.72 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 206376 kb
Host smart-7e9badd4-a554-4d1f-b2af-2b9fe38b7c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529472742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.529472742
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3001067273
Short name T840
Test name
Test status
Simulation time 115513596 ps
CPU time 2.16 seconds
Started Jul 07 06:34:16 PM PDT 24
Finished Jul 07 06:34:21 PM PDT 24
Peak memory 225556 kb
Host smart-0a2fe647-265b-4538-984e-d23bee7645af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001067273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3001067273
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3316147877
Short name T947
Test name
Test status
Simulation time 183395046 ps
CPU time 0.81 seconds
Started Jul 07 06:34:15 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 207532 kb
Host smart-1808adc3-1bd3-47f4-82b0-c20e4b7b8999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316147877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3316147877
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1054379852
Short name T258
Test name
Test status
Simulation time 26068635024 ps
CPU time 155.24 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:36:48 PM PDT 24
Peak memory 254224 kb
Host smart-742e3fef-32a3-4120-9ca2-9ca2d5fd864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054379852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1054379852
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4236775652
Short name T912
Test name
Test status
Simulation time 4085291902 ps
CPU time 99.91 seconds
Started Jul 07 06:34:13 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 258600 kb
Host smart-bbacfb27-9aa1-4e14-8df4-d3b6882d78a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236775652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4236775652
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.734162283
Short name T926
Test name
Test status
Simulation time 1725004166 ps
CPU time 11.96 seconds
Started Jul 07 06:34:13 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 233740 kb
Host smart-732c7cc6-8a19-4281-906c-6aa39570a481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734162283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.734162283
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1809904299
Short name T901
Test name
Test status
Simulation time 67830546357 ps
CPU time 153.07 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:36:45 PM PDT 24
Peak memory 252636 kb
Host smart-9bcf4147-8815-4a73-8bf1-2ee50151be57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809904299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1809904299
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.889583702
Short name T185
Test name
Test status
Simulation time 1412384790 ps
CPU time 18.32 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 225596 kb
Host smart-76ef394f-de12-4523-8690-a2839e5a165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889583702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.889583702
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1724894224
Short name T799
Test name
Test status
Simulation time 2287496851 ps
CPU time 10.25 seconds
Started Jul 07 06:34:08 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 241912 kb
Host smart-7ccd58fd-e03a-43d7-939b-c6c399796978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724894224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1724894224
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2250458412
Short name T788
Test name
Test status
Simulation time 616184691 ps
CPU time 6.37 seconds
Started Jul 07 06:34:16 PM PDT 24
Finished Jul 07 06:34:25 PM PDT 24
Peak memory 225568 kb
Host smart-fea5ca8d-d339-4c2c-8d61-050e8e920fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250458412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2250458412
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.311531765
Short name T951
Test name
Test status
Simulation time 5499682353 ps
CPU time 6.23 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:34:18 PM PDT 24
Peak memory 225672 kb
Host smart-7ea001b2-f211-4a24-902d-7eaee6cfc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311531765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.311531765
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.455771423
Short name T1024
Test name
Test status
Simulation time 336835226 ps
CPU time 4.17 seconds
Started Jul 07 06:34:13 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 224008 kb
Host smart-8a954389-d282-4148-9e2c-cb2021f6be11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=455771423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.455771423
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.922703709
Short name T889
Test name
Test status
Simulation time 52024019 ps
CPU time 1.15 seconds
Started Jul 07 06:34:12 PM PDT 24
Finished Jul 07 06:34:15 PM PDT 24
Peak memory 208224 kb
Host smart-aab3497b-4b8a-4952-9c19-521f1b4479b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922703709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.922703709
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1160644946
Short name T874
Test name
Test status
Simulation time 1706902893 ps
CPU time 15.15 seconds
Started Jul 07 06:34:11 PM PDT 24
Finished Jul 07 06:34:26 PM PDT 24
Peak memory 217400 kb
Host smart-b244053d-5146-455a-8dd4-365442b0e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160644946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1160644946
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3415860202
Short name T379
Test name
Test status
Simulation time 550118475 ps
CPU time 3.54 seconds
Started Jul 07 06:34:09 PM PDT 24
Finished Jul 07 06:34:13 PM PDT 24
Peak memory 217384 kb
Host smart-d64cbe4c-eb21-4164-a7ac-e0672c44686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415860202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3415860202
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.786614582
Short name T1023
Test name
Test status
Simulation time 35171689 ps
CPU time 1.38 seconds
Started Jul 07 06:34:18 PM PDT 24
Finished Jul 07 06:34:20 PM PDT 24
Peak memory 217356 kb
Host smart-46e2ad79-9f3d-4524-8dcd-c35f5f1512a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786614582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.786614582
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1306887324
Short name T397
Test name
Test status
Simulation time 122356771 ps
CPU time 0.85 seconds
Started Jul 07 06:34:13 PM PDT 24
Finished Jul 07 06:34:16 PM PDT 24
Peak memory 207964 kb
Host smart-6dbec9f4-5d81-44df-bb9e-e9ecbce20f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306887324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1306887324
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4212403966
Short name T765
Test name
Test status
Simulation time 6959769026 ps
CPU time 11.18 seconds
Started Jul 07 06:34:10 PM PDT 24
Finished Jul 07 06:34:22 PM PDT 24
Peak memory 233908 kb
Host smart-88a9d457-c9e0-41de-9a10-b8120d9f31af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212403966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4212403966
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.384261778
Short name T825
Test name
Test status
Simulation time 31972692 ps
CPU time 0.7 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 206328 kb
Host smart-13e1fe32-753f-4833-ad4d-b25ef8ce9c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384261778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.384261778
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3309672037
Short name T838
Test name
Test status
Simulation time 576791092 ps
CPU time 6.14 seconds
Started Jul 07 06:34:19 PM PDT 24
Finished Jul 07 06:34:26 PM PDT 24
Peak memory 225600 kb
Host smart-f35f870c-c7e3-4451-80fe-0ce59956bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309672037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3309672037
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2670711733
Short name T480
Test name
Test status
Simulation time 25529691 ps
CPU time 0.8 seconds
Started Jul 07 06:34:18 PM PDT 24
Finished Jul 07 06:34:20 PM PDT 24
Peak memory 207804 kb
Host smart-375b3cef-900f-48da-ae8f-f8ac098a1513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670711733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2670711733
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2772743113
Short name T671
Test name
Test status
Simulation time 1698088882 ps
CPU time 40.22 seconds
Started Jul 07 06:34:20 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 250168 kb
Host smart-37a17daa-b2fb-4d70-8f18-145be52d3a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772743113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2772743113
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4008119490
Short name T1030
Test name
Test status
Simulation time 6373666013 ps
CPU time 75.39 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:35:41 PM PDT 24
Peak memory 266764 kb
Host smart-0adeb332-9a11-4687-9926-1af73e95a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008119490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4008119490
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1605650271
Short name T327
Test name
Test status
Simulation time 77653735878 ps
CPU time 216.5 seconds
Started Jul 07 06:34:21 PM PDT 24
Finished Jul 07 06:37:58 PM PDT 24
Peak memory 265060 kb
Host smart-0dd4d9b5-0d2e-4fd3-bc73-05805a6761c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605650271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1605650271
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1377606724
Short name T257
Test name
Test status
Simulation time 80569945 ps
CPU time 3.89 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 241964 kb
Host smart-1b67bce2-f203-4533-8458-b011f55d9215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377606724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1377606724
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.607944546
Short name T999
Test name
Test status
Simulation time 8314684503 ps
CPU time 83.06 seconds
Started Jul 07 06:34:17 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 256664 kb
Host smart-3912a331-706a-46c1-a19c-144183458a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607944546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.607944546
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1820369119
Short name T895
Test name
Test status
Simulation time 160917220 ps
CPU time 2.43 seconds
Started Jul 07 06:34:17 PM PDT 24
Finished Jul 07 06:34:21 PM PDT 24
Peak memory 233544 kb
Host smart-2c321739-9720-4286-97a9-90cfc2e73b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820369119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1820369119
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.616058620
Short name T646
Test name
Test status
Simulation time 6895041678 ps
CPU time 22.68 seconds
Started Jul 07 06:34:17 PM PDT 24
Finished Jul 07 06:34:41 PM PDT 24
Peak memory 241832 kb
Host smart-3a2f2aed-41d7-46dd-9334-d7b7af8b458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616058620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.616058620
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1960524057
Short name T354
Test name
Test status
Simulation time 304706162 ps
CPU time 2.47 seconds
Started Jul 07 06:34:16 PM PDT 24
Finished Jul 07 06:34:21 PM PDT 24
Peak memory 233480 kb
Host smart-2c893fca-c686-41ef-aeb3-d96f5dccdee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960524057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1960524057
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.275795177
Short name T882
Test name
Test status
Simulation time 5316914241 ps
CPU time 14.85 seconds
Started Jul 07 06:34:18 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 233844 kb
Host smart-3a667231-c9d4-41a4-b1a6-d79619fe0504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275795177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.275795177
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2139138092
Short name T639
Test name
Test status
Simulation time 1856074687 ps
CPU time 21.26 seconds
Started Jul 07 06:34:21 PM PDT 24
Finished Jul 07 06:34:43 PM PDT 24
Peak memory 222820 kb
Host smart-73984579-b280-430c-a18a-a857ad2e9f04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139138092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2139138092
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4247493135
Short name T167
Test name
Test status
Simulation time 23126141411 ps
CPU time 63.96 seconds
Started Jul 07 06:34:22 PM PDT 24
Finished Jul 07 06:35:26 PM PDT 24
Peak memory 253288 kb
Host smart-e5491ae6-16af-490d-9452-b373499b2926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247493135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4247493135
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4652069
Short name T860
Test name
Test status
Simulation time 1998174068 ps
CPU time 4.13 seconds
Started Jul 07 06:34:18 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 217500 kb
Host smart-30b41734-d6cd-4abf-8785-e4bee92b4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4652069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4652069
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1625492220
Short name T963
Test name
Test status
Simulation time 1222639042 ps
CPU time 4.95 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:31 PM PDT 24
Peak memory 217380 kb
Host smart-ca1dbbee-7ade-4a36-9b8f-85f1385a494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625492220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1625492220
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.374816554
Short name T778
Test name
Test status
Simulation time 45935525 ps
CPU time 1.29 seconds
Started Jul 07 06:34:16 PM PDT 24
Finished Jul 07 06:34:20 PM PDT 24
Peak memory 217348 kb
Host smart-d5c4f0a6-a869-4610-9a8c-037fffd3bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374816554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.374816554
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1045582263
Short name T521
Test name
Test status
Simulation time 50028741 ps
CPU time 0.73 seconds
Started Jul 07 06:34:17 PM PDT 24
Finished Jul 07 06:34:19 PM PDT 24
Peak memory 206960 kb
Host smart-3caf467f-3063-4645-8495-33f8115ff6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045582263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1045582263
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.644787197
Short name T231
Test name
Test status
Simulation time 10185758290 ps
CPU time 22.12 seconds
Started Jul 07 06:34:19 PM PDT 24
Finished Jul 07 06:34:41 PM PDT 24
Peak memory 233868 kb
Host smart-6713da70-baa5-4214-97ea-c7736171319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644787197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.644787197
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1909048294
Short name T861
Test name
Test status
Simulation time 10446203 ps
CPU time 0.7 seconds
Started Jul 07 06:34:24 PM PDT 24
Finished Jul 07 06:34:25 PM PDT 24
Peak memory 205776 kb
Host smart-d4d00bc7-dbcc-4ef6-b327-650014818f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909048294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1909048294
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.367169036
Short name T687
Test name
Test status
Simulation time 111404795 ps
CPU time 3.05 seconds
Started Jul 07 06:34:24 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 225628 kb
Host smart-b1be7f91-8913-4492-9401-dd9145712650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367169036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.367169036
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3491498482
Short name T619
Test name
Test status
Simulation time 16336017 ps
CPU time 0.79 seconds
Started Jul 07 06:34:21 PM PDT 24
Finished Jul 07 06:34:22 PM PDT 24
Peak memory 207492 kb
Host smart-b12b0afd-9744-4684-a355-df40dcede5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491498482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3491498482
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4257885322
Short name T986
Test name
Test status
Simulation time 166761991912 ps
CPU time 280.37 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:39:07 PM PDT 24
Peak memory 251360 kb
Host smart-c80f44c4-e00c-46eb-9349-3b556aaac5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257885322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4257885322
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.542955394
Short name T52
Test name
Test status
Simulation time 11408701538 ps
CPU time 53.08 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:35:19 PM PDT 24
Peak memory 237320 kb
Host smart-e0c13865-3457-4b93-ba77-b1307120c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542955394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.542955394
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4199169391
Short name T295
Test name
Test status
Simulation time 34133729353 ps
CPU time 286.78 seconds
Started Jul 07 06:34:26 PM PDT 24
Finished Jul 07 06:39:14 PM PDT 24
Peak memory 250388 kb
Host smart-92101046-8049-4af5-aa1d-4a4cefc9b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199169391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4199169391
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1411077734
Short name T946
Test name
Test status
Simulation time 7577555364 ps
CPU time 33.25 seconds
Started Jul 07 06:34:24 PM PDT 24
Finished Jul 07 06:34:57 PM PDT 24
Peak memory 225692 kb
Host smart-da08cd5d-c075-4ddb-8282-3a3602d79cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411077734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1411077734
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.950703233
Short name T282
Test name
Test status
Simulation time 13125878871 ps
CPU time 77.3 seconds
Started Jul 07 06:34:26 PM PDT 24
Finished Jul 07 06:35:44 PM PDT 24
Peak memory 252860 kb
Host smart-33bf6119-bd51-4d30-8d9a-33b0dfa1cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950703233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.950703233
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3065847713
Short name T203
Test name
Test status
Simulation time 334463303 ps
CPU time 2.51 seconds
Started Jul 07 06:34:20 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 225536 kb
Host smart-803a6068-32de-4b48-bea5-2dcf2eb2594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065847713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3065847713
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1749058538
Short name T176
Test name
Test status
Simulation time 219228068 ps
CPU time 3.28 seconds
Started Jul 07 06:34:20 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 225492 kb
Host smart-2fffd9f6-51b6-458f-bcbf-bba2ca9aabd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749058538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1749058538
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.996942964
Short name T292
Test name
Test status
Simulation time 1975221916 ps
CPU time 4.74 seconds
Started Jul 07 06:34:21 PM PDT 24
Finished Jul 07 06:34:26 PM PDT 24
Peak memory 233720 kb
Host smart-d0393a99-2300-4052-9481-a5579c7a3e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996942964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.996942964
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.412935792
Short name T61
Test name
Test status
Simulation time 1935228346 ps
CPU time 2.96 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:29 PM PDT 24
Peak memory 225536 kb
Host smart-88b64950-6056-44d2-a5dd-282bba09db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412935792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.412935792
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1418468850
Short name T669
Test name
Test status
Simulation time 334897854 ps
CPU time 3.5 seconds
Started Jul 07 06:34:26 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 224108 kb
Host smart-29cbef4b-d403-4bf5-8963-5685c919ed25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1418468850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1418468850
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1669358615
Short name T56
Test name
Test status
Simulation time 147832285507 ps
CPU time 767.84 seconds
Started Jul 07 06:34:26 PM PDT 24
Finished Jul 07 06:47:15 PM PDT 24
Peak memory 299704 kb
Host smart-198c9c19-3558-4e1e-9658-890396bf6ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669358615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1669358615
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3527193025
Short name T518
Test name
Test status
Simulation time 23073946538 ps
CPU time 12.28 seconds
Started Jul 07 06:34:21 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 217668 kb
Host smart-48afafb3-9167-4e99-ac53-0155411870b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527193025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3527193025
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1359497899
Short name T664
Test name
Test status
Simulation time 496605293 ps
CPU time 4.05 seconds
Started Jul 07 06:34:23 PM PDT 24
Finished Jul 07 06:34:27 PM PDT 24
Peak memory 217340 kb
Host smart-d5898653-2d98-46bf-a717-5c8ca5af17c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359497899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1359497899
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4023224127
Short name T548
Test name
Test status
Simulation time 114378001 ps
CPU time 1.61 seconds
Started Jul 07 06:34:19 PM PDT 24
Finished Jul 07 06:34:21 PM PDT 24
Peak memory 217432 kb
Host smart-9794e3be-7849-4770-9b09-8a281dd15c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023224127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4023224127
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2558185515
Short name T709
Test name
Test status
Simulation time 120696360 ps
CPU time 0.93 seconds
Started Jul 07 06:34:22 PM PDT 24
Finished Jul 07 06:34:23 PM PDT 24
Peak memory 206972 kb
Host smart-bfd9805b-749d-4c32-9a61-75dbe9dc1a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558185515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2558185515
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.50817302
Short name T1010
Test name
Test status
Simulation time 5494871692 ps
CPU time 7.83 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 225660 kb
Host smart-ce15286f-ee91-4128-8e0f-685efcee819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50817302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.50817302
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4016800225
Short name T491
Test name
Test status
Simulation time 42417083 ps
CPU time 0.68 seconds
Started Jul 07 06:34:33 PM PDT 24
Finished Jul 07 06:34:34 PM PDT 24
Peak memory 205668 kb
Host smart-af5f858c-fc90-49c8-aca8-414a73f9c720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016800225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4016800225
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.251696621
Short name T1012
Test name
Test status
Simulation time 140476064 ps
CPU time 3.43 seconds
Started Jul 07 06:34:30 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 233708 kb
Host smart-362916d7-5ab4-4da7-a7a6-853b0c02960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251696621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.251696621
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4037494229
Short name T739
Test name
Test status
Simulation time 20624127 ps
CPU time 0.81 seconds
Started Jul 07 06:34:26 PM PDT 24
Finished Jul 07 06:34:28 PM PDT 24
Peak memory 207864 kb
Host smart-f17a0435-e7dc-4fc5-8e22-76922c1bf86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037494229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4037494229
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3447132246
Short name T696
Test name
Test status
Simulation time 52552420043 ps
CPU time 197.25 seconds
Started Jul 07 06:34:34 PM PDT 24
Finished Jul 07 06:37:52 PM PDT 24
Peak memory 253972 kb
Host smart-44289092-222d-4b18-940c-0abc8134bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447132246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3447132246
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2836832031
Short name T992
Test name
Test status
Simulation time 10906002673 ps
CPU time 77.79 seconds
Started Jul 07 06:34:34 PM PDT 24
Finished Jul 07 06:35:52 PM PDT 24
Peak memory 250412 kb
Host smart-9ccda90a-0d9b-4c16-88a7-bf688c90efe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836832031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2836832031
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3334325086
Short name T260
Test name
Test status
Simulation time 50061301499 ps
CPU time 271.16 seconds
Started Jul 07 06:34:32 PM PDT 24
Finished Jul 07 06:39:03 PM PDT 24
Peak memory 254680 kb
Host smart-8cca9b85-60ee-46f6-9d6a-ffed518df64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334325086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3334325086
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3603342859
Short name T742
Test name
Test status
Simulation time 4182512283 ps
CPU time 35.07 seconds
Started Jul 07 06:34:28 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 233864 kb
Host smart-8ffa6572-80b8-4654-91ad-6860f4c6ec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603342859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3603342859
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.348276910
Short name T387
Test name
Test status
Simulation time 82767323 ps
CPU time 0.79 seconds
Started Jul 07 06:34:27 PM PDT 24
Finished Jul 07 06:34:28 PM PDT 24
Peak memory 217136 kb
Host smart-759b7465-454f-48e8-be92-fb757613f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348276910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.348276910
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3173037400
Short name T752
Test name
Test status
Simulation time 3835231672 ps
CPU time 11.01 seconds
Started Jul 07 06:34:27 PM PDT 24
Finished Jul 07 06:34:38 PM PDT 24
Peak memory 225696 kb
Host smart-7df811eb-d60d-434e-915b-f963707b1e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173037400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3173037400
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2454168488
Short name T826
Test name
Test status
Simulation time 200190076 ps
CPU time 3.68 seconds
Started Jul 07 06:34:29 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 225580 kb
Host smart-7f4f79a3-16b4-4aec-af5d-c5904249dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454168488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2454168488
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4076817223
Short name T585
Test name
Test status
Simulation time 592101018 ps
CPU time 2.98 seconds
Started Jul 07 06:34:27 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 233668 kb
Host smart-275aefbf-3713-4e40-9daf-9e0ce52104a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076817223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4076817223
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1120875708
Short name T996
Test name
Test status
Simulation time 784762036 ps
CPU time 4.28 seconds
Started Jul 07 06:34:31 PM PDT 24
Finished Jul 07 06:34:36 PM PDT 24
Peak memory 225604 kb
Host smart-71dc94b1-0668-4585-97a6-b6c52460fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120875708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1120875708
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3850294443
Short name T151
Test name
Test status
Simulation time 780819568 ps
CPU time 6.13 seconds
Started Jul 07 06:34:31 PM PDT 24
Finished Jul 07 06:34:37 PM PDT 24
Peak memory 221304 kb
Host smart-e0f1d6fb-aefb-4ebe-be95-05541afac1a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3850294443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3850294443
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2743082412
Short name T262
Test name
Test status
Simulation time 4174472207 ps
CPU time 62.21 seconds
Started Jul 07 06:34:33 PM PDT 24
Finished Jul 07 06:35:35 PM PDT 24
Peak memory 254004 kb
Host smart-534a6126-5b4b-4bf8-a670-67d80105b589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743082412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2743082412
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4248114744
Short name T953
Test name
Test status
Simulation time 5105953820 ps
CPU time 14.81 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:40 PM PDT 24
Peak memory 221388 kb
Host smart-a29ba04f-2359-48e6-8dae-fcf8d3ab15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248114744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4248114744
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3008735368
Short name T350
Test name
Test status
Simulation time 1613119686 ps
CPU time 2.02 seconds
Started Jul 07 06:34:25 PM PDT 24
Finished Jul 07 06:34:28 PM PDT 24
Peak memory 208944 kb
Host smart-5b686080-9103-4b52-baef-f61f36440a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008735368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3008735368
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.903032993
Short name T493
Test name
Test status
Simulation time 39374787 ps
CPU time 1.29 seconds
Started Jul 07 06:34:30 PM PDT 24
Finished Jul 07 06:34:32 PM PDT 24
Peak memory 209144 kb
Host smart-9e1cd2ef-20e6-410c-9ff0-91460456dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903032993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.903032993
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.175236533
Short name T382
Test name
Test status
Simulation time 134290961 ps
CPU time 0.8 seconds
Started Jul 07 06:34:28 PM PDT 24
Finished Jul 07 06:34:29 PM PDT 24
Peak memory 206964 kb
Host smart-713fa8a6-56e1-4a9f-9bda-73e524190345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175236533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.175236533
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.40199008
Short name T777
Test name
Test status
Simulation time 2046607235 ps
CPU time 7.45 seconds
Started Jul 07 06:34:33 PM PDT 24
Finished Jul 07 06:34:41 PM PDT 24
Peak memory 233740 kb
Host smart-2d566014-a046-4325-b31c-675946829d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40199008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.40199008
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2900527636
Short name T374
Test name
Test status
Simulation time 10906110 ps
CPU time 0.72 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:34:38 PM PDT 24
Peak memory 206420 kb
Host smart-806b15d5-af47-45c4-a63d-3252b96c0352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900527636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2900527636
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1573029008
Short name T979
Test name
Test status
Simulation time 72333163 ps
CPU time 2.75 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:39 PM PDT 24
Peak memory 233736 kb
Host smart-3c0b0cc0-2cfb-4b31-8b0a-a3950e61ca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573029008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1573029008
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.554077767
Short name T964
Test name
Test status
Simulation time 38413837 ps
CPU time 0.79 seconds
Started Jul 07 06:34:32 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 207512 kb
Host smart-c9be8b5c-ca39-4c83-91eb-a6678f9689be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554077767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.554077767
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2117765046
Short name T219
Test name
Test status
Simulation time 21087639779 ps
CPU time 73.04 seconds
Started Jul 07 06:34:35 PM PDT 24
Finished Jul 07 06:35:49 PM PDT 24
Peak memory 253580 kb
Host smart-023f50a0-7c6e-4b51-9e4e-177012ef8bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117765046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2117765046
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2092027554
Short name T557
Test name
Test status
Simulation time 1874513234 ps
CPU time 20.03 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:56 PM PDT 24
Peak memory 218500 kb
Host smart-fdaf21fc-3a16-4063-bf1a-73f0621f0d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092027554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2092027554
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1224423024
Short name T312
Test name
Test status
Simulation time 83559862504 ps
CPU time 126.52 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:36:44 PM PDT 24
Peak memory 251488 kb
Host smart-ac60b656-c990-46e0-bcf3-2229907f05c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224423024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1224423024
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.561236756
Short name T650
Test name
Test status
Simulation time 1000045895 ps
CPU time 8.79 seconds
Started Jul 07 06:34:45 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 225480 kb
Host smart-50c3e058-ae77-4523-bb39-986a61d81b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561236756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.561236756
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1674831098
Short name T684
Test name
Test status
Simulation time 101992800 ps
CPU time 0.74 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:37 PM PDT 24
Peak memory 216896 kb
Host smart-b1c4796d-0882-4c72-9e17-472240d3d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674831098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1674831098
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1448503715
Short name T261
Test name
Test status
Simulation time 1414685316 ps
CPU time 3.95 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 233780 kb
Host smart-2d0a10a5-886a-41db-b3e0-d9f0ecb5d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448503715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1448503715
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1883207185
Short name T241
Test name
Test status
Simulation time 40152721766 ps
CPU time 62.91 seconds
Started Jul 07 06:34:33 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 233860 kb
Host smart-bfe2f831-b7e2-450a-b35d-a7c90940f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883207185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1883207185
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2004230857
Short name T48
Test name
Test status
Simulation time 8819500369 ps
CPU time 16.32 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:53 PM PDT 24
Peak memory 225708 kb
Host smart-bfbd2fd5-b86c-4010-9082-60338348b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004230857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2004230857
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.470841076
Short name T612
Test name
Test status
Simulation time 51092607588 ps
CPU time 15.4 seconds
Started Jul 07 06:34:33 PM PDT 24
Finished Jul 07 06:34:49 PM PDT 24
Peak memory 225664 kb
Host smart-6f448171-89e6-4ae4-ae74-e195f58b5b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470841076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.470841076
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2196981554
Short name T582
Test name
Test status
Simulation time 18865406020 ps
CPU time 20.64 seconds
Started Jul 07 06:34:39 PM PDT 24
Finished Jul 07 06:35:00 PM PDT 24
Peak memory 223252 kb
Host smart-3c5113e1-384d-434b-938a-1392b9e01ef2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2196981554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2196981554
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3720458610
Short name T18
Test name
Test status
Simulation time 149889518 ps
CPU time 0.99 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:38 PM PDT 24
Peak memory 206512 kb
Host smart-f45b3b2b-7074-481c-a4dc-2544e5a5f00a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720458610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3720458610
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1840937489
Short name T790
Test name
Test status
Simulation time 1373578744 ps
CPU time 16.07 seconds
Started Jul 07 06:34:34 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 217356 kb
Host smart-8a689a3e-853e-4f0f-bc9d-2494d47f4c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840937489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1840937489
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.570467356
Short name T916
Test name
Test status
Simulation time 4645737679 ps
CPU time 8.95 seconds
Started Jul 07 06:34:32 PM PDT 24
Finished Jul 07 06:34:41 PM PDT 24
Peak memory 217416 kb
Host smart-8144fbc1-361e-4e4c-b5b1-8a43af6e1559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570467356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.570467356
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.729271111
Short name T987
Test name
Test status
Simulation time 48625887 ps
CPU time 0.92 seconds
Started Jul 07 06:34:45 PM PDT 24
Finished Jul 07 06:34:47 PM PDT 24
Peak memory 206856 kb
Host smart-e68b9647-a7f7-43ca-884f-17f248f970d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729271111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.729271111
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3985002069
Short name T456
Test name
Test status
Simulation time 49293119 ps
CPU time 0.75 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:34:38 PM PDT 24
Peak memory 206968 kb
Host smart-abad8e9b-f9c8-4610-b2b9-b9f7c9bdb825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985002069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3985002069
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.138434286
Short name T222
Test name
Test status
Simulation time 4480705869 ps
CPU time 13.06 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 225656 kb
Host smart-b36a378c-2dff-4760-88a3-3ad34be32aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138434286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.138434286
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2900622754
Short name T501
Test name
Test status
Simulation time 14599990 ps
CPU time 0.76 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:34:43 PM PDT 24
Peak memory 206372 kb
Host smart-6a8351eb-b9fa-415a-b7bc-e71841f4e928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900622754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2900622754
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.952503717
Short name T699
Test name
Test status
Simulation time 86238022 ps
CPU time 3.27 seconds
Started Jul 07 06:34:39 PM PDT 24
Finished Jul 07 06:34:43 PM PDT 24
Peak memory 233736 kb
Host smart-902b4dcd-a721-440a-87c8-feb4aa657030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952503717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.952503717
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.460147570
Short name T858
Test name
Test status
Simulation time 23026822 ps
CPU time 0.79 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:34:37 PM PDT 24
Peak memory 207440 kb
Host smart-fc0b40f2-5c01-4a21-9c23-89e25d9eba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460147570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.460147570
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3013524969
Short name T822
Test name
Test status
Simulation time 5750699585 ps
CPU time 35.99 seconds
Started Jul 07 06:34:45 PM PDT 24
Finished Jul 07 06:35:22 PM PDT 24
Peak memory 254392 kb
Host smart-2e2263a3-37a8-46ac-bd79-a5c53034147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013524969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3013524969
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.624118044
Short name T338
Test name
Test status
Simulation time 32504185966 ps
CPU time 143.94 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:37:10 PM PDT 24
Peak memory 254476 kb
Host smart-b7472e52-1b00-413e-a603-0c3f2cf12e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624118044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.624118044
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.405517122
Short name T797
Test name
Test status
Simulation time 66641518157 ps
CPU time 170.51 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:37:31 PM PDT 24
Peak memory 255364 kb
Host smart-f275871c-315a-4468-a740-5402b85f7521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405517122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.405517122
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3602092922
Short name T520
Test name
Test status
Simulation time 916603168 ps
CPU time 10.65 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:34:53 PM PDT 24
Peak memory 225600 kb
Host smart-3967e881-8d7a-4f44-9873-ee9bf2d10e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602092922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3602092922
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1994007107
Short name T577
Test name
Test status
Simulation time 178673411366 ps
CPU time 308.56 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:39:49 PM PDT 24
Peak memory 257704 kb
Host smart-2e21f3ea-9b5a-4c35-b7de-d4a2a7e07d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994007107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1994007107
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3349755534
Short name T243
Test name
Test status
Simulation time 506336532 ps
CPU time 7.79 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:34:49 PM PDT 24
Peak memory 225536 kb
Host smart-0e69512c-23cc-41d9-ba51-642f2663be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349755534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3349755534
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4180695453
Short name T592
Test name
Test status
Simulation time 127836840 ps
CPU time 2.51 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:34:42 PM PDT 24
Peak memory 233544 kb
Host smart-d0d65a41-5aa3-44d1-959b-840ad4e5e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180695453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4180695453
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3700564586
Short name T506
Test name
Test status
Simulation time 1351195656 ps
CPU time 4.39 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:34:45 PM PDT 24
Peak memory 233820 kb
Host smart-1d221b1a-0ae1-44d4-bb74-78efc9676b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700564586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3700564586
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.79714679
Short name T184
Test name
Test status
Simulation time 2600676731 ps
CPU time 10.98 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:34:57 PM PDT 24
Peak memory 225640 kb
Host smart-924735a6-0702-4a00-815e-b2bc0646666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79714679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.79714679
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.509256772
Short name T43
Test name
Test status
Simulation time 760938965 ps
CPU time 6.68 seconds
Started Jul 07 06:34:38 PM PDT 24
Finished Jul 07 06:34:45 PM PDT 24
Peak memory 221276 kb
Host smart-65c935df-1ddd-44fa-be0b-f5528dbfa143
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=509256772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.509256772
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1787783559
Short name T921
Test name
Test status
Simulation time 10221484530 ps
CPU time 54.49 seconds
Started Jul 07 06:34:36 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 217644 kb
Host smart-b193ab86-8076-4c8c-98c6-7014235ae20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787783559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1787783559
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.280548642
Short name T413
Test name
Test status
Simulation time 1881363380 ps
CPU time 4.5 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:34:42 PM PDT 24
Peak memory 217352 kb
Host smart-942ba45b-ac50-4a75-b47a-6bb6aab008d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280548642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.280548642
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1806072679
Short name T852
Test name
Test status
Simulation time 135886571 ps
CPU time 1.06 seconds
Started Jul 07 06:34:37 PM PDT 24
Finished Jul 07 06:34:39 PM PDT 24
Peak memory 208224 kb
Host smart-daf7f4d2-0b1c-43d4-9ca7-8236c999d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806072679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1806072679
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3995903897
Short name T173
Test name
Test status
Simulation time 285807335 ps
CPU time 0.77 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:34:47 PM PDT 24
Peak memory 206944 kb
Host smart-0a470d3e-90ea-462e-b59a-1788f57341c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995903897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3995903897
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2076589149
Short name T966
Test name
Test status
Simulation time 331639622 ps
CPU time 6.05 seconds
Started Jul 07 06:34:40 PM PDT 24
Finished Jul 07 06:34:47 PM PDT 24
Peak memory 225572 kb
Host smart-40785396-76d0-4ad3-9efe-2e5f48e6afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076589149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2076589149
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1473528215
Short name T67
Test name
Test status
Simulation time 12631433 ps
CPU time 0.7 seconds
Started Jul 07 06:29:47 PM PDT 24
Finished Jul 07 06:29:48 PM PDT 24
Peak memory 206348 kb
Host smart-eebf3ade-e0d8-4171-bce1-d7b0cd9bdf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473528215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
473528215
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3483217580
Short name T762
Test name
Test status
Simulation time 855875227 ps
CPU time 4.84 seconds
Started Jul 07 06:29:38 PM PDT 24
Finished Jul 07 06:29:43 PM PDT 24
Peak memory 233752 kb
Host smart-54cead20-e08c-4283-9e12-a5c5a3f8afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483217580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3483217580
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3454946463
Short name T904
Test name
Test status
Simulation time 32818503 ps
CPU time 0.77 seconds
Started Jul 07 06:29:36 PM PDT 24
Finished Jul 07 06:29:37 PM PDT 24
Peak memory 207508 kb
Host smart-12fb9d74-7bf6-4972-bc9a-d785c11884e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454946463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3454946463
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4035657880
Short name T934
Test name
Test status
Simulation time 156724516708 ps
CPU time 191.11 seconds
Started Jul 07 06:29:37 PM PDT 24
Finished Jul 07 06:32:48 PM PDT 24
Peak memory 250472 kb
Host smart-616258f1-56eb-4a08-a2e0-b500306ee8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035657880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4035657880
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.117307981
Short name T750
Test name
Test status
Simulation time 787192875 ps
CPU time 4.31 seconds
Started Jul 07 06:29:37 PM PDT 24
Finished Jul 07 06:29:42 PM PDT 24
Peak memory 225588 kb
Host smart-bd2eeb8c-5877-44c5-aea4-9da9aa328ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117307981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.117307981
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2590320394
Short name T995
Test name
Test status
Simulation time 44575494861 ps
CPU time 116.65 seconds
Started Jul 07 06:29:38 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 253768 kb
Host smart-305cb105-c884-42d3-837c-24c67185d6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590320394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2590320394
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2284298230
Short name T420
Test name
Test status
Simulation time 145211176 ps
CPU time 3.66 seconds
Started Jul 07 06:29:34 PM PDT 24
Finished Jul 07 06:29:38 PM PDT 24
Peak memory 233776 kb
Host smart-73f536b7-ad2e-44a9-a9f6-fbf67d5f9bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284298230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2284298230
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2353797286
Short name T579
Test name
Test status
Simulation time 55404042 ps
CPU time 2.5 seconds
Started Jul 07 06:29:34 PM PDT 24
Finished Jul 07 06:29:37 PM PDT 24
Peak memory 233508 kb
Host smart-43d5ff56-48d0-4d32-9457-9ccbc451be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353797286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2353797286
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3943629172
Short name T782
Test name
Test status
Simulation time 17128338 ps
CPU time 1.06 seconds
Started Jul 07 06:29:32 PM PDT 24
Finished Jul 07 06:29:33 PM PDT 24
Peak memory 217652 kb
Host smart-545ed8dc-f4a1-47ec-ad8c-e8d78b58630b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943629172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3943629172
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3665257186
Short name T736
Test name
Test status
Simulation time 859499825 ps
CPU time 3.11 seconds
Started Jul 07 06:29:39 PM PDT 24
Finished Jul 07 06:29:42 PM PDT 24
Peak memory 233720 kb
Host smart-43322f34-af7b-4114-983d-cf73cc5ef1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665257186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3665257186
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3764822614
Short name T278
Test name
Test status
Simulation time 274228443 ps
CPU time 2.95 seconds
Started Jul 07 06:29:35 PM PDT 24
Finished Jul 07 06:29:38 PM PDT 24
Peak memory 233792 kb
Host smart-10950cca-5d04-4f6e-9ed0-c9b6894c84d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764822614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3764822614
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2028977140
Short name T472
Test name
Test status
Simulation time 833537827 ps
CPU time 5.09 seconds
Started Jul 07 06:29:40 PM PDT 24
Finished Jul 07 06:29:45 PM PDT 24
Peak memory 222940 kb
Host smart-a7a09dcf-3a43-4935-ac34-151dd66b6ef8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028977140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2028977140
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.387892481
Short name T163
Test name
Test status
Simulation time 16528828176 ps
CPU time 129.77 seconds
Started Jul 07 06:29:48 PM PDT 24
Finished Jul 07 06:31:59 PM PDT 24
Peak memory 225812 kb
Host smart-b186a9c6-8c4f-4aaf-80f4-8a46cf3d0338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387892481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.387892481
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.437797986
Short name T785
Test name
Test status
Simulation time 3880601724 ps
CPU time 23.42 seconds
Started Jul 07 06:29:37 PM PDT 24
Finished Jul 07 06:30:00 PM PDT 24
Peak memory 217668 kb
Host smart-b4eb2f5b-2058-4e85-99d4-28ef492cabcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437797986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.437797986
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3935665402
Short name T475
Test name
Test status
Simulation time 28084709 ps
CPU time 0.74 seconds
Started Jul 07 06:29:30 PM PDT 24
Finished Jul 07 06:29:31 PM PDT 24
Peak memory 206620 kb
Host smart-ec65696b-5290-43b2-9f9b-9ef1f61e848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935665402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3935665402
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2725546642
Short name T870
Test name
Test status
Simulation time 346406983 ps
CPU time 1.79 seconds
Started Jul 07 06:29:37 PM PDT 24
Finished Jul 07 06:29:39 PM PDT 24
Peak memory 217360 kb
Host smart-0ccc75ca-6154-4e67-85ab-f763f6d04b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725546642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2725546642
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.170166774
Short name T600
Test name
Test status
Simulation time 56954235 ps
CPU time 0.93 seconds
Started Jul 07 06:29:34 PM PDT 24
Finished Jul 07 06:29:35 PM PDT 24
Peak memory 207192 kb
Host smart-b5c6f8fd-1569-4693-8f8a-c81c886a2541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170166774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.170166774
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2993340688
Short name T695
Test name
Test status
Simulation time 965688292 ps
CPU time 8.61 seconds
Started Jul 07 06:29:40 PM PDT 24
Finished Jul 07 06:29:49 PM PDT 24
Peak memory 241940 kb
Host smart-2899ff07-337e-4669-9aac-a2edbcb098fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993340688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2993340688
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3604470006
Short name T644
Test name
Test status
Simulation time 45437776 ps
CPU time 0.77 seconds
Started Jul 07 06:29:48 PM PDT 24
Finished Jul 07 06:29:49 PM PDT 24
Peak memory 206404 kb
Host smart-32e028ef-abd8-4ec8-904c-4f81867e7c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604470006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
604470006
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2007182614
Short name T937
Test name
Test status
Simulation time 162900453 ps
CPU time 2.48 seconds
Started Jul 07 06:29:46 PM PDT 24
Finished Jul 07 06:29:49 PM PDT 24
Peak memory 225508 kb
Host smart-1bb2b0d3-b20e-4a23-ad82-b6ff6544858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007182614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2007182614
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.98535362
Short name T385
Test name
Test status
Simulation time 20005864 ps
CPU time 0.84 seconds
Started Jul 07 06:29:48 PM PDT 24
Finished Jul 07 06:29:49 PM PDT 24
Peak memory 207472 kb
Host smart-1290c5e2-bcae-4a59-96fa-21782537b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98535362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.98535362
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3417021928
Short name T212
Test name
Test status
Simulation time 23846401315 ps
CPU time 90.97 seconds
Started Jul 07 06:29:50 PM PDT 24
Finished Jul 07 06:31:22 PM PDT 24
Peak memory 250280 kb
Host smart-6bcba625-f242-4a77-a65b-013eb03c1e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417021928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3417021928
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3994049973
Short name T809
Test name
Test status
Simulation time 29055193156 ps
CPU time 233.13 seconds
Started Jul 07 06:29:49 PM PDT 24
Finished Jul 07 06:33:42 PM PDT 24
Peak memory 270412 kb
Host smart-73815231-1438-403a-b9a7-26b6185cf0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994049973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3994049973
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1793871499
Short name T334
Test name
Test status
Simulation time 8373947453 ps
CPU time 21.59 seconds
Started Jul 07 06:29:48 PM PDT 24
Finished Jul 07 06:30:09 PM PDT 24
Peak memory 233864 kb
Host smart-13d69073-5c79-4b9c-a019-d50cf8a767f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793871499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1793871499
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2975581437
Short name T720
Test name
Test status
Simulation time 181724033 ps
CPU time 4.14 seconds
Started Jul 07 06:29:46 PM PDT 24
Finished Jul 07 06:29:50 PM PDT 24
Peak memory 225500 kb
Host smart-c9256a65-ac02-432a-be72-1785f386b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975581437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2975581437
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.592915814
Short name T806
Test name
Test status
Simulation time 6809546573 ps
CPU time 40.59 seconds
Started Jul 07 06:29:47 PM PDT 24
Finished Jul 07 06:30:28 PM PDT 24
Peak memory 239284 kb
Host smart-34fcfb06-25db-45f1-bf2e-203efa9cb1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592915814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.592915814
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.544883268
Short name T549
Test name
Test status
Simulation time 16767719 ps
CPU time 1.03 seconds
Started Jul 07 06:29:47 PM PDT 24
Finished Jul 07 06:29:49 PM PDT 24
Peak memory 218884 kb
Host smart-28a6d094-3a37-4d79-8908-0f5692cd8922
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544883268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.544883268
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2565105559
Short name T769
Test name
Test status
Simulation time 294145001 ps
CPU time 2.05 seconds
Started Jul 07 06:29:46 PM PDT 24
Finished Jul 07 06:29:48 PM PDT 24
Peak memory 225516 kb
Host smart-3f03243d-23ff-47cf-9587-4bf8a0c0d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565105559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2565105559
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2816333095
Short name T948
Test name
Test status
Simulation time 542566872 ps
CPU time 5.88 seconds
Started Jul 07 06:29:46 PM PDT 24
Finished Jul 07 06:29:52 PM PDT 24
Peak memory 233640 kb
Host smart-7610a8fe-360f-499b-bf93-04942e94940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816333095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2816333095
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3137579012
Short name T691
Test name
Test status
Simulation time 4787094506 ps
CPU time 10.79 seconds
Started Jul 07 06:29:52 PM PDT 24
Finished Jul 07 06:30:03 PM PDT 24
Peak memory 222424 kb
Host smart-0f39e1dd-cc05-42e4-af9a-1c507b8f0280
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3137579012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3137579012
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3090698458
Short name T168
Test name
Test status
Simulation time 35694296050 ps
CPU time 106.45 seconds
Started Jul 07 06:29:49 PM PDT 24
Finished Jul 07 06:31:36 PM PDT 24
Peak memory 250876 kb
Host smart-e84824e4-7c65-4ccd-9fca-4d4dbc53e253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090698458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3090698458
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.374860108
Short name T341
Test name
Test status
Simulation time 3747984938 ps
CPU time 10.39 seconds
Started Jul 07 06:29:49 PM PDT 24
Finished Jul 07 06:29:59 PM PDT 24
Peak memory 217456 kb
Host smart-7d34cdd2-2c13-4882-9445-5fe093964ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374860108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.374860108
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.471393627
Short name T732
Test name
Test status
Simulation time 1089089821 ps
CPU time 2.68 seconds
Started Jul 07 06:29:49 PM PDT 24
Finished Jul 07 06:29:52 PM PDT 24
Peak memory 217380 kb
Host smart-e09113fe-0337-49b1-b5ac-14a09d4589e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471393627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.471393627
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.34563096
Short name T707
Test name
Test status
Simulation time 72019257 ps
CPU time 1.57 seconds
Started Jul 07 06:29:44 PM PDT 24
Finished Jul 07 06:29:46 PM PDT 24
Peak memory 217340 kb
Host smart-ba060bfc-16ba-4cc0-b36c-98a8463a72e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34563096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.34563096
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1369806558
Short name T884
Test name
Test status
Simulation time 22386078 ps
CPU time 0.7 seconds
Started Jul 07 06:29:47 PM PDT 24
Finished Jul 07 06:29:48 PM PDT 24
Peak memory 206552 kb
Host smart-9d34ae5f-984f-46c1-ae91-ee3443f18e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369806558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1369806558
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1986067575
Short name T830
Test name
Test status
Simulation time 834421524 ps
CPU time 5.56 seconds
Started Jul 07 06:29:47 PM PDT 24
Finished Jul 07 06:29:53 PM PDT 24
Peak memory 225516 kb
Host smart-38919253-2e39-401b-afad-a85e86bb6262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986067575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1986067575
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2178393816
Short name T471
Test name
Test status
Simulation time 53144000 ps
CPU time 0.71 seconds
Started Jul 07 06:29:58 PM PDT 24
Finished Jul 07 06:30:00 PM PDT 24
Peak memory 206420 kb
Host smart-64b93fc7-0b07-4f39-a81e-286a40322ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178393816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
178393816
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2409800139
Short name T685
Test name
Test status
Simulation time 2825058842 ps
CPU time 17.86 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:30:12 PM PDT 24
Peak memory 232552 kb
Host smart-841ab2db-d378-442e-98fc-2f8555960058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409800139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2409800139
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3430639894
Short name T170
Test name
Test status
Simulation time 36923667 ps
CPU time 0.79 seconds
Started Jul 07 06:29:50 PM PDT 24
Finished Jul 07 06:29:51 PM PDT 24
Peak memory 207516 kb
Host smart-adac8823-e332-4cdb-af84-bef61367f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430639894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3430639894
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4187573112
Short name T183
Test name
Test status
Simulation time 17765101507 ps
CPU time 88.42 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:31:21 PM PDT 24
Peak memory 254640 kb
Host smart-a20925b2-c698-4e05-8e78-13bb20331092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187573112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4187573112
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.447025408
Short name T930
Test name
Test status
Simulation time 34137332902 ps
CPU time 298.56 seconds
Started Jul 07 06:29:52 PM PDT 24
Finished Jul 07 06:34:51 PM PDT 24
Peak memory 266800 kb
Host smart-12578e6c-3088-4b32-ae6e-6862d92cf7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447025408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.447025408
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2024717790
Short name T287
Test name
Test status
Simulation time 28060366686 ps
CPU time 273.98 seconds
Started Jul 07 06:29:56 PM PDT 24
Finished Jul 07 06:34:30 PM PDT 24
Peak memory 251444 kb
Host smart-b71c7254-da74-4e75-bc55-affe53a85abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024717790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2024717790
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2864428770
Short name T589
Test name
Test status
Simulation time 10345486359 ps
CPU time 26.61 seconds
Started Jul 07 06:29:51 PM PDT 24
Finished Jul 07 06:30:18 PM PDT 24
Peak memory 242076 kb
Host smart-c4ffec87-6ac7-4cce-9e0f-b3beb743e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864428770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2864428770
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1904376543
Short name T925
Test name
Test status
Simulation time 23653977845 ps
CPU time 70.14 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:31:04 PM PDT 24
Peak memory 253980 kb
Host smart-f7434e13-5c03-4b22-81f8-69c70c341b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904376543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1904376543
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1858778886
Short name T676
Test name
Test status
Simulation time 3238399688 ps
CPU time 20 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:30:14 PM PDT 24
Peak memory 233920 kb
Host smart-0c6c1eac-1def-4939-b83f-ba24f64066f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858778886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1858778886
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.146884674
Short name T894
Test name
Test status
Simulation time 13624648540 ps
CPU time 15.81 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:30:09 PM PDT 24
Peak memory 241672 kb
Host smart-5ded9c2e-ddca-4cbd-ac50-1def889fe233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146884674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.146884674
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3041232199
Short name T760
Test name
Test status
Simulation time 16592851 ps
CPU time 1.06 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:29:54 PM PDT 24
Peak memory 217620 kb
Host smart-64e8cbb0-34eb-4be4-8d0e-53c861571c3d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041232199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3041232199
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3310058384
Short name T310
Test name
Test status
Simulation time 688481073 ps
CPU time 7.49 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:30:02 PM PDT 24
Peak memory 241524 kb
Host smart-6b57da7a-8965-463e-a61c-96c5936b395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310058384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3310058384
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3560542305
Short name T266
Test name
Test status
Simulation time 554414646 ps
CPU time 3.78 seconds
Started Jul 07 06:29:52 PM PDT 24
Finished Jul 07 06:29:56 PM PDT 24
Peak memory 233784 kb
Host smart-8295b172-d0bd-4a45-89f7-0d5f3274b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560542305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3560542305
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3588036679
Short name T436
Test name
Test status
Simulation time 4756551447 ps
CPU time 13.15 seconds
Started Jul 07 06:29:53 PM PDT 24
Finished Jul 07 06:30:06 PM PDT 24
Peak memory 222240 kb
Host smart-5b3a44c5-9f8d-48f6-96e9-882058aeaa10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588036679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3588036679
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.590454576
Short name T497
Test name
Test status
Simulation time 1122753628 ps
CPU time 20.34 seconds
Started Jul 07 06:29:55 PM PDT 24
Finished Jul 07 06:30:16 PM PDT 24
Peak memory 225628 kb
Host smart-19dd9a9b-4fff-4dd0-809d-8125890b8d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590454576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.590454576
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3789268563
Short name T638
Test name
Test status
Simulation time 22028264110 ps
CPU time 33.96 seconds
Started Jul 07 06:29:52 PM PDT 24
Finished Jul 07 06:30:26 PM PDT 24
Peak memory 217432 kb
Host smart-1eea1490-ad1b-4727-858f-eac63fc7a717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789268563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3789268563
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1888994752
Short name T478
Test name
Test status
Simulation time 38576967 ps
CPU time 0.69 seconds
Started Jul 07 06:29:51 PM PDT 24
Finished Jul 07 06:29:52 PM PDT 24
Peak memory 206644 kb
Host smart-4eaca0ff-4cbc-4293-a22e-7a3d99211d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888994752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1888994752
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3612427610
Short name T981
Test name
Test status
Simulation time 2489923312 ps
CPU time 2.1 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:29:57 PM PDT 24
Peak memory 217504 kb
Host smart-b4930af0-ad8c-41f1-a6ba-962674c4ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612427610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3612427610
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.224432836
Short name T495
Test name
Test status
Simulation time 71149918 ps
CPU time 0.77 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:29:55 PM PDT 24
Peak memory 206996 kb
Host smart-1655a2d4-d8bd-4f83-b128-c9fb6e9b55ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224432836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.224432836
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.549204214
Short name T463
Test name
Test status
Simulation time 4050190586 ps
CPU time 3.13 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:29:58 PM PDT 24
Peak memory 233896 kb
Host smart-1b4d73f0-b9c4-4cd6-ba0b-d7681361028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549204214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.549204214
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1544984338
Short name T841
Test name
Test status
Simulation time 16011630 ps
CPU time 0.75 seconds
Started Jul 07 06:30:05 PM PDT 24
Finished Jul 07 06:30:06 PM PDT 24
Peak memory 206740 kb
Host smart-b59fd276-67d3-4020-9493-256154497a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544984338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
544984338
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2934658478
Short name T2
Test name
Test status
Simulation time 1890708155 ps
CPU time 8.74 seconds
Started Jul 07 06:30:01 PM PDT 24
Finished Jul 07 06:30:10 PM PDT 24
Peak memory 233776 kb
Host smart-1330ed74-da51-4b0c-87c4-2d92a80c359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934658478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2934658478
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1645733014
Short name T469
Test name
Test status
Simulation time 16084713 ps
CPU time 0.78 seconds
Started Jul 07 06:29:58 PM PDT 24
Finished Jul 07 06:30:00 PM PDT 24
Peak memory 207840 kb
Host smart-da7f5a68-2ece-468e-b2ff-d40d488179d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645733014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1645733014
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1253507594
Short name T315
Test name
Test status
Simulation time 311229286524 ps
CPU time 545.61 seconds
Started Jul 07 06:30:05 PM PDT 24
Finished Jul 07 06:39:11 PM PDT 24
Peak memory 262276 kb
Host smart-14f27e32-9d63-4991-a36d-6d468c0c9293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253507594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1253507594
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2041702926
Short name T323
Test name
Test status
Simulation time 3959178976 ps
CPU time 47.39 seconds
Started Jul 07 06:30:03 PM PDT 24
Finished Jul 07 06:30:51 PM PDT 24
Peak memory 256224 kb
Host smart-6febc0df-6da5-4c42-a4c6-e9379511c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041702926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2041702926
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.859907257
Short name T316
Test name
Test status
Simulation time 10461771851 ps
CPU time 110.32 seconds
Started Jul 07 06:30:02 PM PDT 24
Finished Jul 07 06:31:53 PM PDT 24
Peak memory 255084 kb
Host smart-1325a4c6-c71d-4df3-bb21-943c3a4dd326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859907257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
859907257
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3189868449
Short name T915
Test name
Test status
Simulation time 769998429 ps
CPU time 6.01 seconds
Started Jul 07 06:29:59 PM PDT 24
Finished Jul 07 06:30:06 PM PDT 24
Peak memory 233776 kb
Host smart-1259c1a9-a720-465a-8b4b-3147bb94fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189868449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3189868449
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3115983785
Short name T141
Test name
Test status
Simulation time 17720015605 ps
CPU time 88.37 seconds
Started Jul 07 06:30:07 PM PDT 24
Finished Jul 07 06:31:35 PM PDT 24
Peak memory 258432 kb
Host smart-3b268241-6d57-42b8-b3a1-b1d047635b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115983785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3115983785
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.597485542
Short name T372
Test name
Test status
Simulation time 2219612525 ps
CPU time 7.13 seconds
Started Jul 07 06:30:00 PM PDT 24
Finished Jul 07 06:30:07 PM PDT 24
Peak memory 233924 kb
Host smart-05c29410-7a1b-45fc-b97b-bb4addef3a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597485542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.597485542
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3027840371
Short name T655
Test name
Test status
Simulation time 537746073 ps
CPU time 11 seconds
Started Jul 07 06:30:02 PM PDT 24
Finished Jul 07 06:30:13 PM PDT 24
Peak memory 236820 kb
Host smart-58bd7c5e-72f1-4329-990c-070688c15dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027840371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3027840371
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3830475411
Short name T458
Test name
Test status
Simulation time 25212995 ps
CPU time 1.06 seconds
Started Jul 07 06:29:56 PM PDT 24
Finished Jul 07 06:29:57 PM PDT 24
Peak memory 217664 kb
Host smart-6200fefa-ce33-4f6c-a918-f6dc83a782e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830475411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3830475411
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.814617599
Short name T528
Test name
Test status
Simulation time 11112659770 ps
CPU time 18.81 seconds
Started Jul 07 06:29:59 PM PDT 24
Finished Jul 07 06:30:18 PM PDT 24
Peak memory 250080 kb
Host smart-8a5a2be1-f3ff-4a54-b47b-60c98a7dd253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814617599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
814617599
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1059639877
Short name T398
Test name
Test status
Simulation time 1344173114 ps
CPU time 5.98 seconds
Started Jul 07 06:30:02 PM PDT 24
Finished Jul 07 06:30:09 PM PDT 24
Peak memory 233824 kb
Host smart-8f36af23-7bd1-4fd2-bde4-ffc820132d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059639877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1059639877
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1175692560
Short name T508
Test name
Test status
Simulation time 3178474965 ps
CPU time 9.72 seconds
Started Jul 07 06:30:06 PM PDT 24
Finished Jul 07 06:30:16 PM PDT 24
Peak memory 220392 kb
Host smart-b3d8d941-b94d-43d5-a351-1de50140a154
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175692560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1175692560
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1695676251
Short name T165
Test name
Test status
Simulation time 292726058 ps
CPU time 1.17 seconds
Started Jul 07 06:30:02 PM PDT 24
Finished Jul 07 06:30:04 PM PDT 24
Peak memory 216804 kb
Host smart-1fca2221-6133-44ae-83cc-a7914d13cde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695676251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1695676251
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2019727267
Short name T857
Test name
Test status
Simulation time 1731782222 ps
CPU time 27.84 seconds
Started Jul 07 06:29:56 PM PDT 24
Finished Jul 07 06:30:24 PM PDT 24
Peak memory 217332 kb
Host smart-2ea28ae0-3c32-452f-b341-bb4be8b5f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019727267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2019727267
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1016566883
Short name T428
Test name
Test status
Simulation time 1550504278 ps
CPU time 4.74 seconds
Started Jul 07 06:29:54 PM PDT 24
Finished Jul 07 06:29:59 PM PDT 24
Peak memory 217348 kb
Host smart-207b78d4-3fcd-42ac-86ae-3bea0f6f51a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016566883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1016566883
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.614796575
Short name T903
Test name
Test status
Simulation time 43638038 ps
CPU time 0.69 seconds
Started Jul 07 06:29:59 PM PDT 24
Finished Jul 07 06:30:01 PM PDT 24
Peak memory 206556 kb
Host smart-9f8223f4-e608-4b56-b257-523fc086cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614796575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.614796575
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2750284700
Short name T405
Test name
Test status
Simulation time 85219134 ps
CPU time 0.77 seconds
Started Jul 07 06:29:57 PM PDT 24
Finished Jul 07 06:29:58 PM PDT 24
Peak memory 206956 kb
Host smart-e5ae519c-509a-41ed-af31-412e8e70792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750284700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2750284700
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2486223380
Short name T16
Test name
Test status
Simulation time 21359092169 ps
CPU time 15.85 seconds
Started Jul 07 06:29:59 PM PDT 24
Finished Jul 07 06:30:15 PM PDT 24
Peak memory 237488 kb
Host smart-dff644ee-fb75-475f-afe3-72a33e97551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486223380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2486223380
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.979247436
Short name T74
Test name
Test status
Simulation time 106077100 ps
CPU time 0.77 seconds
Started Jul 07 06:30:17 PM PDT 24
Finished Jul 07 06:30:18 PM PDT 24
Peak memory 206728 kb
Host smart-02d80747-a315-43f3-80d1-83ac610beec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979247436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.979247436
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3360627854
Short name T441
Test name
Test status
Simulation time 29806138 ps
CPU time 2.32 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:17 PM PDT 24
Peak memory 225504 kb
Host smart-4a1c07f9-6009-4456-8e02-597be46c40cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360627854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3360627854
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3692768776
Short name T433
Test name
Test status
Simulation time 59961043 ps
CPU time 0.93 seconds
Started Jul 07 06:30:01 PM PDT 24
Finished Jul 07 06:30:02 PM PDT 24
Peak memory 207492 kb
Host smart-8621bede-0847-481d-a870-64c483628ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692768776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3692768776
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.543096712
Short name T208
Test name
Test status
Simulation time 14692417919 ps
CPU time 51.14 seconds
Started Jul 07 06:30:14 PM PDT 24
Finished Jul 07 06:31:05 PM PDT 24
Peak memory 250212 kb
Host smart-c9df3331-343d-4179-8f93-c9221ab8a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543096712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.543096712
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3346872929
Short name T324
Test name
Test status
Simulation time 68069885742 ps
CPU time 305.59 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:35:21 PM PDT 24
Peak memory 267120 kb
Host smart-49294e0e-7a82-480e-99fe-08a7b3d9a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346872929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3346872929
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.846952522
Short name T211
Test name
Test status
Simulation time 63380935752 ps
CPU time 144.97 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:32:40 PM PDT 24
Peak memory 250436 kb
Host smart-986ff695-09c5-4ad6-a17a-7b760c14f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846952522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
846952522
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3365549205
Short name T888
Test name
Test status
Simulation time 676045791 ps
CPU time 9.32 seconds
Started Jul 07 06:30:11 PM PDT 24
Finished Jul 07 06:30:20 PM PDT 24
Peak memory 219848 kb
Host smart-9f8a0145-3679-4a31-994e-523af80735c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365549205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3365549205
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3132560220
Short name T225
Test name
Test status
Simulation time 34438083830 ps
CPU time 262.36 seconds
Started Jul 07 06:30:11 PM PDT 24
Finished Jul 07 06:34:33 PM PDT 24
Peak memory 265172 kb
Host smart-91bdecab-0fd6-4bc6-b0fc-89c04a7c7e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132560220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3132560220
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2982953825
Short name T735
Test name
Test status
Simulation time 1690328875 ps
CPU time 7.31 seconds
Started Jul 07 06:30:06 PM PDT 24
Finished Jul 07 06:30:14 PM PDT 24
Peak memory 233784 kb
Host smart-f4238572-890c-4953-a59f-3a31295b159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982953825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2982953825
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4221187297
Short name T267
Test name
Test status
Simulation time 18857006640 ps
CPU time 85.85 seconds
Started Jul 07 06:30:07 PM PDT 24
Finished Jul 07 06:31:33 PM PDT 24
Peak memory 249964 kb
Host smart-0d359d70-c2ac-454e-83da-56935d300b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221187297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4221187297
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.225477537
Short name T651
Test name
Test status
Simulation time 89348094 ps
CPU time 1.09 seconds
Started Jul 07 06:30:02 PM PDT 24
Finished Jul 07 06:30:04 PM PDT 24
Peak memory 217620 kb
Host smart-0ebcdb0b-6f99-4fcd-b3eb-8fdd712ac08a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225477537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.225477537
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.642010981
Short name T290
Test name
Test status
Simulation time 10302409562 ps
CPU time 15.61 seconds
Started Jul 07 06:30:07 PM PDT 24
Finished Jul 07 06:30:23 PM PDT 24
Peak memory 233852 kb
Host smart-12bf8066-d34c-44df-918d-603677071080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642010981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
642010981
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2159937445
Short name T120
Test name
Test status
Simulation time 781041509 ps
CPU time 3.18 seconds
Started Jul 07 06:30:06 PM PDT 24
Finished Jul 07 06:30:09 PM PDT 24
Peak memory 233704 kb
Host smart-e87d8620-a415-43c1-9b44-b381f46c84ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159937445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2159937445
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1779632677
Short name T836
Test name
Test status
Simulation time 301122583 ps
CPU time 3.64 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:30:19 PM PDT 24
Peak memory 223976 kb
Host smart-74bac0a9-d034-4762-a7ff-e00a72cd62b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1779632677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1779632677
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1764471680
Short name T552
Test name
Test status
Simulation time 24863750451 ps
CPU time 283.06 seconds
Started Jul 07 06:30:15 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 267580 kb
Host smart-6c99dc36-64cf-4bca-9915-4e06b9076488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764471680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1764471680
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.876716221
Short name T605
Test name
Test status
Simulation time 15586849920 ps
CPU time 46.52 seconds
Started Jul 07 06:30:09 PM PDT 24
Finished Jul 07 06:30:56 PM PDT 24
Peak memory 217540 kb
Host smart-ed7285fd-dc42-4b9d-a22c-b2daa8d42fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876716221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.876716221
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.519109296
Short name T109
Test name
Test status
Simulation time 381221384 ps
CPU time 1.66 seconds
Started Jul 07 06:30:08 PM PDT 24
Finished Jul 07 06:30:10 PM PDT 24
Peak memory 208920 kb
Host smart-9645beed-8027-4e0d-9624-94faab83adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519109296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.519109296
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2022333210
Short name T349
Test name
Test status
Simulation time 54075311 ps
CPU time 1.5 seconds
Started Jul 07 06:30:08 PM PDT 24
Finished Jul 07 06:30:09 PM PDT 24
Peak memory 217364 kb
Host smart-b24e3ab5-0832-451b-9042-a52f251d00bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022333210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2022333210
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2360398288
Short name T892
Test name
Test status
Simulation time 239898054 ps
CPU time 0.97 seconds
Started Jul 07 06:30:07 PM PDT 24
Finished Jul 07 06:30:08 PM PDT 24
Peak memory 207996 kb
Host smart-32736993-dcb6-4839-a757-e779e4ff754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360398288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2360398288
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1123574403
Short name T958
Test name
Test status
Simulation time 1490663754 ps
CPU time 5.35 seconds
Started Jul 07 06:30:12 PM PDT 24
Finished Jul 07 06:30:17 PM PDT 24
Peak memory 233748 kb
Host smart-a8cf5d18-452b-4cda-addc-a929ae0a7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123574403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1123574403
Directory /workspace/9.spi_device_upload/latest
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