Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2617344	1			T1	1		T2	27		T3	6213
all_values[1]	2617344	1			T1	1		T2	27		T3	6213
all_values[2]	2617344	1			T1	1		T2	27		T3	6213
all_values[3]	2617344	1			T1	1		T2	27		T3	6213
all_values[4]	2617344	1			T1	1		T2	27		T3	6213
all_values[5]	2617344	1			T1	1		T2	27		T3	6213
all_values[6]	2617344	1			T1	1		T2	27		T3	6213
all_values[7]	2617344	1			T1	1		T2	27		T3	6213

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19914176

1

T1

8

T2

113

T3

49704

auto[1]

1024576

1

T2

103

T50

40

T15

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20911390

1

T1

8

T2

132

T3

49418

auto[1]

27362

1

T2

84

T3

286

T8

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2452353	1			T1	1		T2	8		T3	6051
all_values[0]	auto[0]	auto[1]	12537	1			T2	8		T3	162		T8	14
all_values[0]	auto[1]	auto[0]	151628	1			T2	8		T50	1		T15	3
all_values[0]	auto[1]	auto[1]	826	1			T2	3		T15	4		T17	4
all_values[1]	auto[0]	auto[0]	2483078	1			T1	1		T2	1		T3	6108
all_values[1]	auto[0]	auto[1]	8026	1			T2	5		T3	105		T23	68
all_values[1]	auto[1]	auto[0]	125804	1			T2	14		T50	2		T15	4
all_values[1]	auto[1]	auto[1]	436	1			T2	7		T18	4		T19	11
all_values[2]	auto[0]	auto[0]	2536371	1			T1	1		T2	11		T3	6194
all_values[2]	auto[0]	auto[1]	3209	1			T2	4		T3	19		T23	39
all_values[2]	auto[1]	auto[0]	77458	1			T2	6		T50	6		T15	3
all_values[2]	auto[1]	auto[1]	306	1			T2	6		T50	1		T15	3
all_values[3]	auto[0]	auto[0]	2456623	1			T1	1		T2	10		T3	6213
all_values[3]	auto[0]	auto[1]	198	1			T2	5		T15	3		T17	5
all_values[3]	auto[1]	auto[0]	160307	1			T2	8		T50	4		T15	6
all_values[3]	auto[1]	auto[1]	216	1			T2	4		T50	6		T15	3
all_values[4]	auto[0]	auto[0]	2536863	1			T1	1		T2	12		T3	6213
all_values[4]	auto[0]	auto[1]	196	1			T2	4		T50	3		T17	7
all_values[4]	auto[1]	auto[0]	80062	1			T2	5		T50	6		T15	3
all_values[4]	auto[1]	auto[1]	223	1			T2	6		T50	3		T15	5
all_values[5]	auto[0]	auto[0]	2516692	1			T1	1		T2	11		T3	6213
all_values[5]	auto[0]	auto[1]	180	1			T2	3		T50	3		T15	4
all_values[5]	auto[1]	auto[0]	100285	1			T2	9		T50	4		T15	2
all_values[5]	auto[1]	auto[1]	187	1			T2	4		T15	1		T17	2
all_values[6]	auto[0]	auto[0]	2466061	1			T1	1		T2	10		T3	6213
all_values[6]	auto[0]	auto[1]	199	1			T2	7		T50	3		T15	4
all_values[6]	auto[1]	auto[0]	150866	1			T2	4		T50	2		T17	3
all_values[6]	auto[1]	auto[1]	218	1			T2	6		T50	2		T15	3
all_values[7]	auto[0]	auto[0]	2441386	1			T1	1		T2	6		T3	6213
all_values[7]	auto[0]	auto[1]	204	1			T2	8		T50	6		T15	2
all_values[7]	auto[1]	auto[0]	175553	1			T2	9		T50	1		T15	5
all_values[7]	auto[1]	auto[1]	201	1			T2	4		T50	2		T15	3