Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38018	1			T3	227		T4	2		T5	113
auto[SpiFlashAddrCfg]	8051	1			T3	50		T5	30		T7	4
auto[SpiFlashAddr3b]	9742	1			T3	45		T5	19		T8	15
auto[SpiFlashAddr4b]	8055	1			T3	38		T5	20		T8	11

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35596

1

T3

161

T4

2

T5

61

auto[1]

28270

1

T3

199

T5

121

T8

28

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33366

1

T3

174

T4

2

T5

109

auto[1]

30500

1

T3

186

T5

73

T7

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42868	1			T3	250		T4	2		T5	130
values[1]	1181	1			T3	7		T5	1		T8	1
values[2]	1562	1			T3	14		T8	1		T9	4
values[3]	1528	1			T3	10		T5	6		T30	2
values[4]	1583	1			T3	9		T5	2		T8	2
values[5]	1614	1			T3	6		T5	3		T8	1
values[6]	1563	1			T3	13		T5	3		T8	1
values[7]	1479	1			T3	5		T5	6		T8	5
values[8]	10488	1			T3	46		T5	31		T7	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35488

1

T3

360

T4

2

T7

10

auto[1]

28378

1

T5

182

T8

65

T12

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60461

1

T3

340

T4

2

T5

169

write

3405

1

T3

20

T5

13

T8

5

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20091

1

T3

101

T4

2

T5

36

valids[0x1]

43775

1

T3

259

T5

146

T7

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1614	1			T3	5		T5	4		T7	2
internal_process_ops[0x5a]	1579	1			T3	13		T5	6		T8	3
internal_process_ops[0x05]	23494	1			T3	148		T5	88		T8	9
internal_process_ops[0x35]	1618	1			T3	11		T5	5		T7	2
internal_process_ops[0x15]	1713	1			T3	6		T5	3		T8	2
internal_process_ops[0x03]	1140	1			T3	7		T5	1		T7	4
internal_process_ops[0x0b]	1224	1			T3	8		T12	1		T30	11
internal_process_ops[0x3b]	1097	1			T3	2		T5	2		T11	2
internal_process_ops[0x6b]	1138	1			T3	4		T5	2		T30	2
internal_process_ops[0xbb]	1107	1			T3	6		T5	2		T8	1
internal_process_ops[0xeb]	1137	1			T3	16		T30	7		T23	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62161

1

T3

352

T4

2

T5

178

auto[1]

1705

1

T3

8

T5

4

T8

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61363

1

T3

344

T4

2

T5

174

auto[1]

2503

1

T3

16

T5

8

T8

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11218

1

T3

93

T4

2

T7

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8483

1

T3

126

T10

4

T30

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2378

1

T3

22

T7

4

T30

15

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2024

1

T3

24

T10

2

T30

15

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2769

1

T3

23

T9

10

T11

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2483

1

T3

17

T30

26

T23

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2270

1

T3

14

T9

2

T11

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2082

1

T3

21

T30

12

T23

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

149

1

T3

4

T30

2

T35

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T45

1

T38

2

T48

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T3

1

T38

2

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

124

1

T3

3

T30

1

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

119

1

T3

2

T38

1

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T3

1

T30

2

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

92

1

T3

1

T30

1

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

123

1

T30

2

T38

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T3

1

T9

4

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T3

1

T38

2

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T3

2

T45

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

136

1

T3

1

T35

1

T23

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

136

1

T23

1

T48

1

T49

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T30

2

T23

1

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

108

1

T3

1

T23

2

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T3

2

T23

1

T46

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10555

1

T5

17

T8

12

T36

7

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6943

1

T5

96

T8

10

T25

79

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1473

1

T5

15

T8

6

T36

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1330

1

T5

7

T8

6

T36

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1802

1

T5

12

T8

5

T36

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1807

1

T5

5

T8

10

T36

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1442

1

T5

8

T8

9

T12

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1402

1

T5

9

T8

2

T36

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

102

1

T36

1

T25

2

T37

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

89

1

T8

1

T37

2

T15

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T37

1

T51

6

T15

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T25

3

T15

1

T170

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

93

1

T5

6

T8

2

T51

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T5

1

T8

2

T51

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

106

1

T5

1

T25

1

T37

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

117

1

T25

2

T37

3

T51

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T25

3

T51

1

T15

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

123

1

T5

1

T25

7

T37

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

105

1

T36

1

T125

1

T19

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T5

1

T15

2

T76

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T5

1

T37

1

T170

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

85

1

T37

1

T15

3

T170

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T5

1

T25

2

T15

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

113

1

T5

1

T25

1

T170

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4234	1			T3	45		T4	2		T9	4
auto[0]	values[0]	valids[0x1]	18676	1			T3	205		T7	4		T9	6
auto[0]	values[1]	valids[0x1]	674	1			T3	7		T30	12		T23	4
auto[0]	values[2]	valids[0x0]	617	1			T3	9		T30	9		T23	6
auto[0]	values[2]	valids[0x1]	343	1			T3	5		T9	4		T23	9
auto[0]	values[3]	valids[0x0]	592	1			T3	5		T30	2		T23	3
auto[0]	values[3]	valids[0x1]	298	1			T3	5		T42	2		T23	6
auto[0]	values[4]	valids[0x0]	605	1			T3	5		T11	2		T35	4
auto[0]	values[4]	valids[0x1]	365	1			T3	4		T23	4		T45	3
auto[0]	values[5]	valids[0x0]	592	1			T3	4		T30	5		T23	5
auto[0]	values[5]	valids[0x1]	348	1			T3	2		T30	3		T23	2
auto[0]	values[6]	valids[0x0]	608	1			T3	5		T30	5		T35	4
auto[0]	values[6]	valids[0x1]	358	1			T3	8		T9	2		T30	9
auto[0]	values[7]	valids[0x0]	579	1			T3	3		T30	7		T23	3
auto[0]	values[7]	valids[0x1]	350	1			T3	2		T30	4		T23	5
auto[0]	values[8]	valids[0x0]	3861	1			T3	25		T9	2		T11	4
auto[0]	values[8]	valids[0x1]	2388	1			T3	21		T7	6		T9	4
auto[1]	values[0]	valids[0x0]	3784	1			T5	10		T8	15		T36	3
auto[1]	values[0]	valids[0x1]	16174	1			T5	120		T8	22		T12	1
auto[1]	values[1]	valids[0x1]	507	1			T5	1		T8	1		T25	4
auto[1]	values[2]	valids[0x0]	345	1			T8	1		T25	7		T37	1
auto[1]	values[2]	valids[0x1]	257	1			T25	2		T37	3		T51	4
auto[1]	values[3]	valids[0x0]	371	1			T5	3		T25	3		T51	2
auto[1]	values[3]	valids[0x1]	267	1			T5	3		T36	1		T25	2
auto[1]	values[4]	valids[0x0]	375	1			T5	2		T25	7		T37	3
auto[1]	values[4]	valids[0x1]	238	1			T8	2		T37	2		T51	3
auto[1]	values[5]	valids[0x0]	397	1			T5	3		T25	7		T37	3
auto[1]	values[5]	valids[0x1]	277	1			T8	1		T25	2		T37	2
auto[1]	values[6]	valids[0x0]	328	1			T5	2		T36	2		T25	4
auto[1]	values[6]	valids[0x1]	269	1			T5	1		T8	1		T25	2
auto[1]	values[7]	valids[0x0]	333	1			T5	3		T8	3		T36	1
auto[1]	values[7]	valids[0x1]	217	1			T5	3		T8	2		T25	2
auto[1]	values[8]	valids[0x0]	2470	1			T5	13		T8	13		T12	3
auto[1]	values[8]	valids[0x1]	1769	1			T5	18		T8	4		T25	12