Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3616130

1

T1

2027

T3

21065

T4

1575

auto[1]

32276

1

T3

140

T5

82

T8

5

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

959107

1

T1

2027

T3

80

T4

1575

auto[1]

2689299

1

T3

21125

T5

7739

T8

2386

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	645035	1			T3	2583		T4	463		T5	532
auto[524288:1048575]	426133	1			T1	294		T3	131		T4	224
auto[1048576:1572863]	454042	1			T3	527		T4	110		T5	780
auto[1572864:2097151]	403718	1			T1	589		T3	2767		T11	3
auto[2097152:2621439]	403152	1			T3	4272		T4	678		T5	297
auto[2621440:3145727]	458174	1			T3	3070		T5	3289		T11	59
auto[3145728:3670015]	417993	1			T1	6		T3	2828		T4	100
auto[3670016:4194303]	440159	1			T1	1138		T3	5027		T5	15

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2723249

1

T1

6

T3

21202

T4

25

auto[1]

925157

1

T1

2021

T3

3

T4

1550

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3206587

1

T1

2027

T3

18463

T4

1575

auto[1]

441819

1

T3

2742

T5

1

T8

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	167939	1			T3	5		T4	463		T5	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	426792	1			T3	2575		T5	516		T8	1356
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	105147	1			T1	294		T3	3		T4	224
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	271233	1			T3	128		T5	2335		T30	259
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	123136	1			T3	6		T4	110		T5	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	287644	1			T3	513		T5	769		T30	7396
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101982	1			T1	589		T3	11		T11	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	235146	1			T3	1037		T30	1892		T23	655
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	88625	1			T3	9		T4	678		T5	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	253875	1			T3	3473		T5	258		T8	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118210	1			T3	5		T5	5		T11	59
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	271474	1			T3	3058		T5	3273		T30	1557
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	127196	1			T1	6		T3	5		T4	100
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	226945	1			T3	2551		T5	512		T8	1024
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	109756	1			T1	1138		T3	11		T5	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	263824	1			T3	4942		T5	2		T8	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	1524	1			T8	2		T23	1		T25	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	44646	1			T25	512		T37	3389		T38	6
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2169	1			T30	9		T23	3		T37	22
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44419	1			T23	2		T25	256		T37	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	540	1			T37	11		T51	4		T38	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	39013	1			T25	2		T51	256		T38	2963
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1432	1			T3	1		T25	1		T37	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	60386	1			T3	1699		T25	512		T51	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	660	1			T3	6		T30	17		T23	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	55772	1			T3	769		T23	133		T25	1853
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	3924	1			T3	1		T30	19		T51	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60590	1			T30	2829		T15	1858		T96	2278
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	475	1			T3	1		T5	1		T25	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	57941	1			T3	256		T25	256		T45	389
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2446	1			T51	2		T45	3		T38	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61269	1			T51	256		T45	256		T38	2471
auto[1]	auto[0]	auto[0:524287]	auto[0]	515	1			T3	1		T5	2		T30	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	3141	1			T3	2		T5	9		T30	188
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	389	1			T5	1		T35	3		T23	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2370	1			T5	6		T23	25		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	426	1			T3	1		T5	1		T30	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2606	1			T3	7		T5	6		T23	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	376	1			T3	3		T23	2		T25	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3641	1			T3	16		T23	11		T25	33
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	397	1			T3	2		T5	2		T8	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3139	1			T3	4		T5	32		T8	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	465	1			T3	2		T5	1		T30	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2979	1			T3	4		T5	10		T23	32
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	403	1			T3	2		T30	11		T45	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4386	1			T3	13		T45	5		T38	33
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	327	1			T3	4		T5	1		T8	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2103	1			T3	70		T5	11		T25	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	90	1			T37	3		T50	3		T170	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	388	1			T37	134		T50	10		T170	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	86	1			T23	2		T47	2		T48	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	320	1			T23	11		T47	2		T48	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	49	1			T38	1		T15	1		T170	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	628	1			T38	6		T15	8		T170	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	100	1			T45	1		T15	2		T97	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	655	1			T45	9		T15	80		T82	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	112	1			T3	1		T30	9		T25	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	572	1			T3	8		T25	2		T45	42
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	67	1			T15	2		T96	5		T16	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	465	1			T15	53		T16	52		T21	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T45	1		T38	2		T125	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	578	1			T45	27		T38	32		T125	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T49	1		T16	4		T82	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	359	1			T49	13		T16	56		T82	25

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2263103	1			T1	6		T3	18331		T4	25
auto[0]	auto[0]	auto[1]	915821	1			T1	2021		T3	1		T4	1550
auto[0]	auto[1]	auto[0]	428539	1			T3	2733		T5	1		T8	2
auto[0]	auto[1]	auto[1]	8667	1			T45	1		T38	3		T124	1154
auto[1]	auto[0]	auto[0]	27085	1			T3	129		T5	75		T8	5
auto[1]	auto[0]	auto[1]	578	1			T3	2		T5	7		T30	4
auto[1]	auto[1]	auto[0]	4522	1			T3	9		T30	9		T23	13
auto[1]	auto[1]	auto[1]	91	1			T37	1		T45	2		T38	2