Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2617344	1			T1	1		T2	27		T3	6213
all_pins[1]	2617344	1			T1	1		T2	27		T3	6213
all_pins[2]	2617344	1			T1	1		T2	27		T3	6213
all_pins[3]	2617344	1			T1	1		T2	27		T3	6213
all_pins[4]	2617344	1			T1	1		T2	27		T3	6213
all_pins[5]	2617344	1			T1	1		T2	27		T3	6213
all_pins[6]	2617344	1			T1	1		T2	27		T3	6213
all_pins[7]	2617344	1			T1	1		T2	27		T3	6213

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20783808	1			T1	8		T2	176		T3	49704
values[0x1]	154944	1			T2	40		T50	14		T15	22
transitions[0x0=>0x1]	152888	1			T2	30		T50	10		T15	21
transitions[0x1=>0x0]	152902	1			T2	30		T50	10		T15	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2616432	1			T1	1		T2	24		T3	6213
all_pins[0]	values[0x1]	912	1			T2	3		T15	4		T17	4
all_pins[0]	transitions[0x0=>0x1]	607	1			T2	1		T15	4		T17	4
all_pins[0]	transitions[0x1=>0x0]	164	1			T2	5		T18	6		T19	3
all_pins[1]	values[0x0]	2616875	1			T1	1		T2	20		T3	6213
all_pins[1]	values[0x1]	469	1			T2	7		T18	6		T19	12
all_pins[1]	transitions[0x0=>0x1]	384	1			T2	5		T18	5		T19	11
all_pins[1]	transitions[0x1=>0x0]	235	1			T2	4		T50	1		T15	3
all_pins[2]	values[0x0]	2617024	1			T1	1		T2	21		T3	6213
all_pins[2]	values[0x1]	320	1			T2	6		T50	1		T15	3
all_pins[2]	transitions[0x0=>0x1]	252	1			T2	4		T50	1		T15	3
all_pins[2]	transitions[0x1=>0x0]	148	1			T2	2		T50	6		T15	3
all_pins[3]	values[0x0]	2617128	1			T1	1		T2	23		T3	6213
all_pins[3]	values[0x1]	216	1			T2	4		T50	6		T15	3
all_pins[3]	transitions[0x0=>0x1]	153	1			T2	1		T50	3		T15	2
all_pins[3]	transitions[0x1=>0x0]	160	1			T2	3		T15	4		T17	1
all_pins[4]	values[0x0]	2617121	1			T1	1		T2	21		T3	6213
all_pins[4]	values[0x1]	223	1			T2	6		T50	3		T15	5
all_pins[4]	transitions[0x0=>0x1]	178	1			T2	5		T50	3		T15	5
all_pins[4]	transitions[0x1=>0x0]	2033	1			T2	3		T15	1		T17	2
all_pins[5]	values[0x0]	2615266	1			T1	1		T2	23		T3	6213
all_pins[5]	values[0x1]	2078	1			T2	4		T15	1		T17	2
all_pins[5]	transitions[0x0=>0x1]	708	1			T2	4		T15	1		T17	1
all_pins[5]	transitions[0x1=>0x0]	149155	1			T2	6		T50	2		T15	3
all_pins[6]	values[0x0]	2466819	1			T1	1		T2	21		T3	6213
all_pins[6]	values[0x1]	150525	1			T2	6		T50	2		T15	3
all_pins[6]	transitions[0x0=>0x1]	150462	1			T2	6		T50	1		T15	3
all_pins[6]	transitions[0x1=>0x0]	138	1			T2	4		T50	1		T15	3
all_pins[7]	values[0x0]	2617143	1			T1	1		T2	23		T3	6213
all_pins[7]	values[0x1]	201	1			T2	4		T50	2		T15	3
all_pins[7]	transitions[0x0=>0x1]	144	1			T2	4		T50	2		T15	3
all_pins[7]	transitions[0x1=>0x0]	869	1			T2	3		T15	4		T17	3