Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19538

1

T3

161

T4

2

T7

10

auto[1]

15950

1

T3

199

T10

6

T30

84

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3932	1			T3	29		T23	80		T45	50
values[1]	4328	1			T3	123		T30	20		T45	20
values[2]	5132	1			T3	97		T11	8		T45	94
values[3]	4638	1			T3	70		T42	10		T23	20
values[4]	4612	1			T30	20		T45	91		T215	10
values[5]	3715	1			T30	20		T35	20		T23	70
values[6]	4359	1			T3	41		T4	2		T30	40
values[7]	4772	1			T7	10		T9	22		T10	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4392	1			T3	94		T23	100		T45	20
values[1]	5088	1			T3	63		T9	22		T23	109
values[2]	4318	1			T3	20		T42	10		T23	71
values[3]	4124	1			T3	20		T45	20		T46	10
values[4]	4732	1			T3	58		T10	6		T30	40
values[5]	3901	1			T3	77		T7	10		T11	8
values[6]	4626	1			T4	2		T30	80		T221	4
values[7]	4307	1			T3	28		T30	40		T35	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	310	1			T3	9		T96	12		T21	14
auto[0]	values[0]	values[1]	409	1			T23	31		T45	23		T50	26
auto[0]	values[0]	values[2]	291	1			T23	16		T50	10		T186	24
auto[0]	values[0]	values[3]	246	1			T45	14		T17	7		T191	25
auto[0]	values[0]	values[4]	277	1			T204	14		T124	6		T17	12
auto[0]	values[0]	values[5]	180	1			T175	13		T192	8		T222	9
auto[0]	values[0]	values[6]	320	1			T50	16		T183	16		T17	18
auto[0]	values[0]	values[7]	163	1			T18	12		T199	7		T218	11
auto[0]	values[1]	values[0]	320	1			T3	10		T38	8		T96	11
auto[0]	values[1]	values[1]	287	1			T3	23		T47	24		T205	8
auto[0]	values[1]	values[2]	330	1			T45	9		T47	22		T16	10
auto[0]	values[1]	values[3]	246	1			T38	16		T223	20		T16	16
auto[0]	values[1]	values[4]	242	1			T30	13		T97	13		T175	8
auto[0]	values[1]	values[5]	319	1			T49	12		T15	9		T224	14
auto[0]	values[1]	values[6]	383	1			T47	12		T96	15		T225	8
auto[0]	values[1]	values[7]	315	1			T3	10		T49	43		T16	11
auto[0]	values[2]	values[0]	239	1			T96	22		T226	2		T17	17
auto[0]	values[2]	values[1]	449	1			T45	13		T38	9		T15	13
auto[0]	values[2]	values[2]	361	1			T96	13		T199	38		T184	11
auto[0]	values[2]	values[3]	507	1			T3	16		T38	12		T50	13
auto[0]	values[2]	values[4]	371	1			T38	14		T17	56		T18	10
auto[0]	values[2]	values[5]	218	1			T3	9		T11	8		T48	11
auto[0]	values[2]	values[6]	293	1			T45	12		T38	12		T22	18
auto[0]	values[2]	values[7]	221	1			T18	20		T212	11		T199	19
auto[0]	values[3]	values[0]	471	1			T3	28		T47	14		T49	157
auto[0]	values[3]	values[1]	367	1			T227	6		T175	16		T228	12
auto[0]	values[3]	values[2]	279	1			T42	10		T38	26		T17	9
auto[0]	values[3]	values[3]	210	1			T22	10		T79	10		T191	10
auto[0]	values[3]	values[4]	340	1			T3	30		T48	13		T16	145
auto[0]	values[3]	values[5]	200	1			T173	17		T229	22		T230	73
auto[0]	values[3]	values[6]	237	1			T49	10		T96	10		T22	11
auto[0]	values[3]	values[7]	424	1			T23	9		T49	76		T97	13
auto[0]	values[4]	values[0]	213	1			T45	18		T97	11		T16	15
auto[0]	values[4]	values[1]	446	1			T45	9		T16	9		T17	15
auto[0]	values[4]	values[2]	403	1			T48	11		T97	9		T18	10
auto[0]	values[4]	values[3]	238	1			T38	13		T50	14		T97	12
auto[0]	values[4]	values[4]	318	1			T47	15		T48	9		T16	29
auto[0]	values[4]	values[5]	365	1			T215	10		T97	11		T16	15
auto[0]	values[4]	values[6]	254	1			T30	11		T45	12		T48	14
auto[0]	values[4]	values[7]	204	1			T50	14		T212	13		T206	8
auto[0]	values[5]	values[0]	228	1			T23	14		T48	10		T15	11
auto[0]	values[5]	values[1]	146	1			T23	10		T17	12		T199	14
auto[0]	values[5]	values[2]	177	1			T50	27		T17	11		T229	10
auto[0]	values[5]	values[3]	327	1			T47	18		T16	11		T22	14
auto[0]	values[5]	values[4]	358	1			T19	8		T22	12		T231	2
auto[0]	values[5]	values[5]	131	1			T16	12		T19	13		T184	11
auto[0]	values[5]	values[6]	290	1			T30	9		T221	4		T38	9
auto[0]	values[5]	values[7]	413	1			T35	18		T45	6		T38	7
auto[0]	values[6]	values[0]	207	1			T47	11		T96	9		T178	9
auto[0]	values[6]	values[1]	343	1			T15	12		T212	17		T232	86
auto[0]	values[6]	values[2]	183	1			T3	10		T97	10		T186	15
auto[0]	values[6]	values[3]	368	1			T38	4		T216	6		T96	12
auto[0]	values[6]	values[4]	456	1			T3	16		T30	13		T45	33
auto[0]	values[6]	values[5]	289	1			T38	10		T48	7		T50	16
auto[0]	values[6]	values[6]	328	1			T4	2		T45	35		T50	22
auto[0]	values[6]	values[7]	282	1			T30	16		T106	16		T47	13
auto[0]	values[7]	values[0]	239	1			T23	21		T16	7		T199	9
auto[0]	values[7]	values[1]	306	1			T9	22		T212	8		T233	2
auto[0]	values[7]	values[2]	511	1			T23	39		T45	48		T48	17
auto[0]	values[7]	values[3]	152	1			T19	16		T234	6		T230	10
auto[0]	values[7]	values[4]	315	1			T50	8		T235	14		T236	16
auto[0]	values[7]	values[5]	470	1			T7	10		T30	10		T95	14
auto[0]	values[7]	values[6]	427	1			T30	13		T82	11		T237	4
auto[0]	values[7]	values[7]	326	1			T30	11		T38	9		T49	21
auto[1]	values[0]	values[0]	378	1			T3	20		T96	8		T21	28
auto[1]	values[0]	values[1]	272	1			T23	29		T45	7		T50	9
auto[1]	values[0]	values[2]	211	1			T23	4		T50	10		T186	17
auto[1]	values[0]	values[3]	227	1			T45	6		T17	13		T191	4
auto[1]	values[0]	values[4]	194	1			T17	8		T192	9		T140	7
auto[1]	values[0]	values[5]	224	1			T175	7		T192	12		T222	11
auto[1]	values[0]	values[6]	124	1			T50	7		T183	4		T17	8
auto[1]	values[0]	values[7]	106	1			T18	8		T199	13		T218	11
auto[1]	values[1]	values[0]	306	1			T3	22		T38	12		T96	9
auto[1]	values[1]	values[1]	267	1			T3	40		T47	22		T178	7
auto[1]	values[1]	values[2]	135	1			T45	11		T47	21		T16	10
auto[1]	values[1]	values[3]	122	1			T46	10		T38	4		T16	8
auto[1]	values[1]	values[4]	343	1			T30	7		T97	7		T175	12
auto[1]	values[1]	values[5]	168	1			T49	8		T15	31		T192	5
auto[1]	values[1]	values[6]	208	1			T47	14		T96	5		T238	6
auto[1]	values[1]	values[7]	337	1			T3	18		T49	9		T16	66
auto[1]	values[2]	values[0]	348	1			T96	18		T17	7		T212	31
auto[1]	values[2]	values[1]	543	1			T45	61		T38	11		T15	28
auto[1]	values[2]	values[2]	333	1			T96	7		T199	6		T184	11
auto[1]	values[2]	values[3]	297	1			T3	4		T38	36		T50	7
auto[1]	values[2]	values[4]	267	1			T38	62		T17	20		T18	25
auto[1]	values[2]	values[5]	260	1			T3	68		T48	16		T15	3
auto[1]	values[2]	values[6]	243	1			T45	8		T38	15		T22	10
auto[1]	values[2]	values[7]	182	1			T18	31		T212	14		T199	37
auto[1]	values[3]	values[0]	265	1			T3	5		T47	6		T49	26
auto[1]	values[3]	values[1]	266	1			T175	4		T211	14		T222	8
auto[1]	values[3]	values[2]	216	1			T38	8		T17	11		T77	5
auto[1]	values[3]	values[3]	180	1			T22	10		T79	12		T191	10
auto[1]	values[3]	values[4]	239	1			T3	7		T48	10		T16	52
auto[1]	values[3]	values[5]	116	1			T239	8		T173	3		T229	8
auto[1]	values[3]	values[6]	394	1			T49	10		T96	10		T22	19
auto[1]	values[3]	values[7]	434	1			T23	11		T49	9		T97	7
auto[1]	values[4]	values[0]	248	1			T45	2		T97	9		T16	5
auto[1]	values[4]	values[1]	176	1			T45	12		T16	11		T17	5
auto[1]	values[4]	values[2]	347	1			T48	9		T97	11		T18	10
auto[1]	values[4]	values[3]	311	1			T38	7		T50	25		T97	8
auto[1]	values[4]	values[4]	268	1			T47	5		T48	15		T16	19
auto[1]	values[4]	values[5]	318	1			T97	9		T16	26		T82	91
auto[1]	values[4]	values[6]	308	1			T30	9		T45	38		T48	9
auto[1]	values[4]	values[7]	195	1			T50	55		T212	8		T184	22
auto[1]	values[5]	values[0]	211	1			T23	7		T48	10		T15	13
auto[1]	values[5]	values[1]	228	1			T23	39		T17	8		T199	6
auto[1]	values[5]	values[2]	146	1			T50	13		T17	9		T240	8
auto[1]	values[5]	values[3]	244	1			T44	16		T47	2		T16	75
auto[1]	values[5]	values[4]	320	1			T19	14		T22	8		T219	8
auto[1]	values[5]	values[5]	108	1			T16	8		T19	9		T184	11
auto[1]	values[5]	values[6]	166	1			T30	11		T38	16		T47	20
auto[1]	values[5]	values[7]	222	1			T35	2		T45	14		T38	13
auto[1]	values[6]	values[0]	107	1			T47	16		T96	11		T178	11
auto[1]	values[6]	values[1]	293	1			T15	8		T212	3		T21	7
auto[1]	values[6]	values[2]	182	1			T3	10		T97	10		T186	7
auto[1]	values[6]	values[3]	251	1			T38	16		T96	8		T18	4
auto[1]	values[6]	values[4]	249	1			T3	5		T30	7		T45	9
auto[1]	values[6]	values[5]	182	1			T38	31		T48	13		T50	8
auto[1]	values[6]	values[6]	318	1			T45	10		T50	32		T16	12
auto[1]	values[6]	values[7]	321	1			T30	4		T47	10		T97	12
auto[1]	values[7]	values[0]	302	1			T23	58		T16	74		T199	15
auto[1]	values[7]	values[1]	290	1			T212	12		T191	11		T219	25
auto[1]	values[7]	values[2]	213	1			T23	12		T45	2		T48	8
auto[1]	values[7]	values[3]	198	1			T19	5		T230	19		T176	11
auto[1]	values[7]	values[4]	175	1			T10	6		T50	12		T241	10
auto[1]	values[7]	values[5]	353	1			T30	10		T45	24		T38	7
auto[1]	values[7]	values[6]	333	1			T30	27		T82	58		T191	81
auto[1]	values[7]	values[7]	162	1			T30	9		T38	17		T49	9