Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	457	1			T3	5		T30	6		T23	2
auto[ReadAddrCrossIntoMailbox]	330	1			T3	4		T30	3		T35	1
auto[ReadAddrCrossOutOfMailbox]	323	1			T3	5		T30	2		T23	3
auto[ReadAddrCrossAllMailbox]	254	1			T3	2		T30	2		T23	2
auto[ReadAddrOutsideMailbox]	3907	1			T3	27		T7	4		T11	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2550

1

T3

24

T7

2

T11

3

auto[1]

2721

1

T3

19

T7

2

T11

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	880	1			T3	7		T7	4		T30	4
read_ops[0x0b]	930	1			T3	8		T30	11		T42	2
read_ops[0x3b]	842	1			T3	2		T11	2		T30	8
read_ops[0x6b]	852	1			T3	4		T30	2		T23	3
read_ops[0xbb]	865	1			T3	6		T11	4		T30	6
read_ops[0xeb]	902	1			T3	16		T30	7		T23	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T30	1		T216	1		T49	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T45	1		T38	1		T216	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T3	1		T227	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T227	1		T48	1		T97	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T47	1		T49	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T23	1		T38	1		T97	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T3	1		T45	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T48	1		T186	1		T178	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T3	2		T7	2		T30	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T3	3		T7	2		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T106	1		T215	1		T16	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T30	2		T106	1		T45	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T45	1		T15	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T3	1		T30	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T23	1		T15	1		T82	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T3	1		T48	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T106	1		T15	2		T16	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T23	1		T106	1		T45	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	347	1			T3	6		T30	1		T42	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T30	7		T42	1		T23	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T23	2		T106	1		T96	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T106	1		T96	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T3	1		T47	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T30	1		T35	1		T16	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T23	1		T45	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T30	1		T47	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T30	1		T47	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T3	1		T209	1		T175	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T11	1		T30	1		T23	6
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T11	1		T30	4		T23	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T3	1		T106	2		T48	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T106	2		T50	1		T15	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T45	1		T183	1		T97	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T45	1		T48	1		T97	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T47	1		T205	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T45	2		T47	1		T97	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T106	1		T227	1		T50	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T30	1		T106	1		T45	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T3	2		T106	1		T45	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T3	1		T30	1		T23	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T3	2		T30	2		T215	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T3	2		T30	1		T215	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T79	1		T81	1		T173	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T3	1		T50	1		T15	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T45	1		T49	1		T82	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T3	1		T48	2		T183	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T15	1		T16	1		T82	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	35	1			T50	1		T18	1		T209	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T11	2		T30	1		T23	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T11	2		T30	2		T23	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T48	1		T96	1		T21	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T47	2		T96	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T106	1		T16	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T30	1		T106	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T30	1		T48	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T3	3		T47	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T23	1		T82	1		T21	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T96	1		T97	2		T18	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T3	8		T30	3		T23	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	360	1			T3	5		T30	2		T23	3