Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4215	1			T30	40		T23	20		T45	40
values[1]	4762	1			T10	6		T95	14		T215	10
values[2]	4260	1			T3	143		T30	40		T23	80
values[3]	4408	1			T3	34		T4	2		T11	8
values[4]	4852	1			T3	90		T30	40		T221	4
values[5]	5273	1			T3	20		T35	20		T44	16
values[6]	3900	1			T3	32		T7	10		T30	20
values[7]	3818	1			T3	41		T9	22		T30	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3931	1			T3	58		T10	6		T30	40
values[1]	4961	1			T3	53		T30	20		T45	116
values[2]	4205	1			T3	53		T7	10		T9	22
values[3]	5553	1			T11	8		T30	20		T35	20
values[4]	3454	1			T3	28		T4	2		T30	40
values[5]	4933	1			T3	131		T30	40		T23	41
values[6]	4051	1			T3	37		T30	20		T42	10
values[7]	4400	1			T23	69		T95	14		T45	127

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34614

1

T3

352

T4

2

T7

10

auto[1]

874

1

T3

8

T30

7

T35

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	369	1			T30	19		T233	2		T229	32
auto[0]	values[0]	values[1]	554	1			T49	51		T96	20		T199	21
auto[0]	values[0]	values[2]	295	1			T200	18		T147	18		T242	82
auto[0]	values[0]	values[3]	607	1			T45	20		T96	20		T16	21
auto[0]	values[0]	values[4]	565	1			T23	20		T45	20		T96	19
auto[0]	values[0]	values[5]	436	1			T198	24		T97	20		T16	20
auto[0]	values[0]	values[6]	672	1			T30	19		T38	26		T15	40
auto[0]	values[0]	values[7]	608	1			T38	20		T15	20		T191	37
auto[0]	values[1]	values[0]	472	1			T10	6		T47	42		T97	20
auto[0]	values[1]	values[1]	750	1			T183	20		T16	20		T209	6
auto[0]	values[1]	values[2]	1012	1			T38	20		T50	20		T16	218
auto[0]	values[1]	values[3]	769	1			T47	27		T16	20		T184	24
auto[0]	values[1]	values[4]	479	1			T50	28		T79	20		T240	8
auto[0]	values[1]	values[5]	446	1			T215	10		T50	20		T97	20
auto[0]	values[1]	values[6]	534	1			T49	145		T50	39		T82	33
auto[0]	values[1]	values[7]	200	1			T95	14		T47	23		T226	2
auto[0]	values[2]	values[0]	376	1			T3	29		T46	6		T186	21
auto[0]	values[2]	values[1]	536	1			T17	49		T21	40		T218	21
auto[0]	values[2]	values[2]	442	1			T47	18		T96	20		T205	8
auto[0]	values[2]	values[3]	744	1			T30	19		T43	8		T45	20
auto[0]	values[2]	values[4]	381	1			T49	27		T17	20		T184	20
auto[0]	values[2]	values[5]	698	1			T3	76		T30	20		T23	40
auto[0]	values[2]	values[6]	530	1			T3	36		T23	39		T38	25
auto[0]	values[2]	values[7]	442	1			T45	21		T38	73		T16	20
auto[0]	values[3]	values[0]	608	1			T47	20		T212	21		T82	148
auto[0]	values[3]	values[1]	475	1			T45	41		T15	23		T22	25
auto[0]	values[3]	values[2]	585	1			T49	84		T50	23		T97	20
auto[0]	values[3]	values[3]	723	1			T11	8		T38	20		T49	20
auto[0]	values[3]	values[4]	518	1			T4	2		T48	19		T16	32
auto[0]	values[3]	values[5]	506	1			T3	33		T30	20		T48	20
auto[0]	values[3]	values[6]	377	1			T227	6		T48	21		T18	31
auto[0]	values[3]	values[7]	497	1			T23	68		T82	51		T199	35
auto[0]	values[4]	values[0]	642	1			T3	28		T30	20		T47	20
auto[0]	values[4]	values[1]	589	1			T3	32		T47	24		T48	23
auto[0]	values[4]	values[2]	355	1			T221	4		T38	50		T47	24
auto[0]	values[4]	values[3]	832	1			T45	50		T48	48		T178	72
auto[0]	values[4]	values[4]	685	1			T3	27		T30	19		T50	20
auto[0]	values[4]	values[5]	691	1			T38	27		T15	41		T17	26
auto[0]	values[4]	values[6]	324	1			T190	12		T184	21		T186	20
auto[0]	values[4]	values[7]	613	1			T45	85		T47	43		T49	29
auto[0]	values[5]	values[0]	557	1			T124	6		T96	20		T16	27
auto[0]	values[5]	values[1]	640	1			T3	18		T48	27		T19	20
auto[0]	values[5]	values[2]	583	1			T49	34		T15	43		T243	8
auto[0]	values[5]	values[3]	890	1			T35	19		T44	16		T19	22
auto[0]	values[5]	values[4]	302	1			T17	20		T206	8		T184	35
auto[0]	values[5]	values[5]	820	1			T218	26		T178	82		T77	20
auto[0]	values[5]	values[6]	580	1			T47	23		T50	69		T16	20
auto[0]	values[5]	values[7]	781	1			T38	46		T48	24		T15	20
auto[0]	values[6]	values[0]	473	1			T23	50		T47	20		T184	20
auto[0]	values[6]	values[1]	669	1			T38	40		T204	14		T22	18
auto[0]	values[6]	values[2]	488	1			T3	32		T7	10		T45	43
auto[0]	values[6]	values[3]	420	1			T23	19		T48	36		T82	52
auto[0]	values[6]	values[4]	240	1			T30	18		T212	29		T199	20
auto[0]	values[6]	values[5]	599	1			T193	16		T82	95		T21	66
auto[0]	values[6]	values[6]	285	1			T23	39		T38	19		T47	20
auto[0]	values[6]	values[7]	625	1			T45	20		T48	21		T18	33
auto[0]	values[7]	values[0]	315	1			T23	20		T106	16		T38	20
auto[0]	values[7]	values[1]	634	1			T30	19		T45	74		T50	20
auto[0]	values[7]	values[2]	333	1			T3	21		T9	22		T97	20
auto[0]	values[7]	values[3]	451	1			T96	20		T175	18		T191	40
auto[0]	values[7]	values[4]	195	1			T96	37		T230	19		T244	14
auto[0]	values[7]	values[5]	627	1			T3	20		T38	20		T97	20
auto[0]	values[7]	values[6]	652	1			T42	10		T45	20		T50	39
auto[0]	values[7]	values[7]	518	1			T96	20		T16	19		T18	20
auto[1]	values[0]	values[0]	11	1			T30	1		T229	1		T150	2
auto[1]	values[0]	values[1]	8	1			T49	1		T199	1		T192	2
auto[1]	values[0]	values[2]	11	1			T200	2		T147	2		T242	1
auto[1]	values[0]	values[3]	19	1			T178	4		T229	1		T211	1
auto[1]	values[0]	values[4]	16	1			T96	1		T19	1		T22	2
auto[1]	values[0]	values[5]	14	1			T245	2		T246	1		T247	4
auto[1]	values[0]	values[6]	17	1			T30	1		T192	2		T200	1
auto[1]	values[0]	values[7]	13	1			T191	2		T238	1		T248	2
auto[1]	values[1]	values[0]	19	1			T16	2		T173	3		T249	2
auto[1]	values[1]	values[1]	18	1			T229	2		T250	2		T251	1
auto[1]	values[1]	values[2]	16	1			T16	9		T178	1		T173	1
auto[1]	values[1]	values[3]	14	1			T184	1		T79	2		T250	1
auto[1]	values[1]	values[4]	16	1			T50	6		T222	2		T252	2
auto[1]	values[1]	values[5]	6	1			T212	1		T219	1		T201	1
auto[1]	values[1]	values[6]	7	1			T49	4		T186	1		T200	1
auto[1]	values[1]	values[7]	4	1			T79	1		T253	1		T254	2
auto[1]	values[2]	values[0]	15	1			T46	4		T186	1		T235	1
auto[1]	values[2]	values[1]	20	1			T21	2		T218	2		T140	3
auto[1]	values[2]	values[2]	8	1			T47	2		T255	2		T256	4
auto[1]	values[2]	values[3]	12	1			T30	1		T178	1		T238	1
auto[1]	values[2]	values[4]	17	1			T49	1		T184	1		T79	3
auto[1]	values[2]	values[5]	15	1			T3	1		T23	1		T45	2
auto[1]	values[2]	values[6]	16	1			T3	1		T178	2		T211	3
auto[1]	values[2]	values[7]	8	1			T38	3		T212	1		T257	2
auto[1]	values[3]	values[0]	18	1			T82	1		T229	1		T211	3
auto[1]	values[3]	values[1]	15	1			T45	1		T15	1		T22	3
auto[1]	values[3]	values[2]	22	1			T49	1		T50	1		T16	3
auto[1]	values[3]	values[3]	15	1			T184	1		T258	1		T259	1
auto[1]	values[3]	values[4]	7	1			T48	1		T21	1		T238	2
auto[1]	values[3]	values[5]	15	1			T3	1		T49	2		T17	2
auto[1]	values[3]	values[6]	15	1			T48	4		T260	3		T252	1
auto[1]	values[3]	values[7]	12	1			T23	1		T82	1		T199	1
auto[1]	values[4]	values[0]	19	1			T3	1		T47	2		T96	1
auto[1]	values[4]	values[1]	11	1			T3	1		T47	2		T208	1
auto[1]	values[4]	values[2]	27	1			T38	4		T47	2		T97	1
auto[1]	values[4]	values[3]	15	1			T178	1		T192	1		T229	2
auto[1]	values[4]	values[4]	13	1			T3	1		T30	1		T184	2
auto[1]	values[4]	values[5]	10	1			T184	1		T236	1		T201	1
auto[1]	values[4]	values[6]	10	1			T190	2		T219	1		T202	4
auto[1]	values[4]	values[7]	16	1			T45	1		T49	1		T50	2
auto[1]	values[5]	values[0]	23	1			T199	3		T184	1		T175	1
auto[1]	values[5]	values[1]	10	1			T3	2		T236	1		T261	1
auto[1]	values[5]	values[2]	6	1			T219	1		T229	1		T202	1
auto[1]	values[5]	values[3]	10	1			T35	1		T248	3		T176	1
auto[1]	values[5]	values[4]	9	1			T184	2		T191	1		T54	3
auto[1]	values[5]	values[5]	27	1			T192	2		T262	8		T249	2
auto[1]	values[5]	values[6]	14	1			T21	2		T238	4		T176	2
auto[1]	values[5]	values[7]	21	1			T38	2		T48	2		T17	3
auto[1]	values[6]	values[0]	9	1			T23	1		T188	1		T263	1
auto[1]	values[6]	values[1]	16	1			T38	1		T22	2		T238	2
auto[1]	values[6]	values[2]	7	1			T45	2		T242	2		T151	1
auto[1]	values[6]	values[3]	12	1			T23	1		T48	4		T264	3
auto[1]	values[6]	values[4]	6	1			T30	2		T141	4		-	-
auto[1]	values[6]	values[5]	13	1			T82	3		T253	3		T200	3
auto[1]	values[6]	values[6]	7	1			T23	1		T38	1		T265	2
auto[1]	values[6]	values[7]	31	1			T48	2		T18	2		T212	3
auto[1]	values[7]	values[0]	5	1			T175	1		T176	2		T266	2
auto[1]	values[7]	values[1]	16	1			T30	1		T222	1		T210	1
auto[1]	values[7]	values[2]	15	1			T200	2		T267	8		T265	1
auto[1]	values[7]	values[3]	20	1			T175	2		T191	2		T268	4
auto[1]	values[7]	values[4]	5	1			T96	3		T230	1		T156	1
auto[1]	values[7]	values[5]	10	1			T16	1		T186	1		T219	2
auto[1]	values[7]	values[6]	11	1			T50	1		T96	2		T16	3
auto[1]	values[7]	values[7]	11	1			T16	1		T188	1		T201	1