Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	836	1			T2	21		T50	10		T15	11
all_values[1]	836	1			T2	21		T50	10		T15	11
all_values[2]	836	1			T2	21		T50	10		T15	11
all_values[3]	836	1			T2	21		T50	10		T15	11
all_values[4]	836	1			T2	21		T50	10		T15	11
all_values[5]	836	1			T2	21		T50	10		T15	11
all_values[6]	836	1			T2	21		T50	10		T15	11
all_values[7]	836	1			T2	21		T50	10		T15	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3478

1

T2

83

T50

53

T15

48

auto[1]

3210

1

T2

85

T50

27

T15

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2585

1

T2

59

T50

29

T15

37

auto[1]

4103

1

T2

109

T50

51

T15

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3755

1

T2

84

T50

46

T15

55

auto[1]

2933

1

T2

84

T50

34

T15

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	187	1			T2	3		T50	5		T15	2
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T2	2		T15	1		T17	1
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T2	2		T15	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T15	2		T17	1		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	190	1			T2	6		T50	4		T15	3
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T2	8		T50	1		T15	2
all_values[1]	auto[0]	auto[0]	auto[0]	155	1			T2	1		T50	4		T15	5
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T2	1		T50	2		T15	1
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T2	7		T50	1		T15	2
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T2	1		T18	3		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	190	1			T2	2		T50	2		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	177	1			T2	9		T50	1		T15	1
all_values[2]	auto[0]	auto[0]	auto[0]	150	1			T2	5		T50	3		T15	2
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T2	2		T50	2		T15	3
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T2	4		T50	1		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	107	1			T2	1		T15	1		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	211	1			T2	4		T50	3		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	171	1			T2	5		T50	1		T15	4
all_values[3]	auto[0]	auto[0]	auto[0]	152	1			T2	5		T50	1		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T2	2		T15	1		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	144	1			T2	5		T50	1		T15	4
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T2	2		T50	3		T15	2
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T2	3		T50	2		T15	2
all_values[3]	auto[1]	auto[1]	auto[1]	168	1			T2	4		T50	3		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T2	3		T50	2		T15	3
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T2	1		T50	2		T17	2
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T2	2		T50	1		T15	2
all_values[4]	auto[0]	auto[1]	auto[1]	98	1			T2	3		T50	2		T15	2
all_values[4]	auto[1]	auto[0]	auto[1]	195	1			T2	6		T50	1		T17	6
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T2	6		T50	2		T15	4
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T2	6		T50	4		T15	4
all_values[5]	auto[0]	auto[1]	auto[0]	238	1			T2	8		T50	3		T15	2
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T2	3		T50	2		T15	3
all_values[5]	auto[1]	auto[1]	auto[1]	176	1			T2	4		T50	1		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T2	2		T50	2		T15	3
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T2	2		T50	2		T15	1
all_values[6]	auto[0]	auto[1]	auto[0]	120	1			T2	1		T17	1		T18	1
all_values[6]	auto[0]	auto[1]	auto[1]	99	1			T2	1		T15	2		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T2	11		T50	3		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	182	1			T2	4		T50	3		T15	2
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T2	2		T15	5		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T2	4		T50	3		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T2	3		T50	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T2	3		T50	1		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	179	1			T2	7		T50	4		T15	1
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T2	2		T50	1		T15	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal