Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T3

2

T8

11

T14

4

auto[1]

1644

1

T3

2

T8

10

T14

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T3

3

T8

18

T23

6

auto[1]

1481

1

T3

1

T8

3

T14

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2591

1

T3

4

T8

14

T14

6

auto[1]

670

1

T8

7

T23

4

T25

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	631	1			T3	1		T8	7		T23	1
valid[1]	651	1			T3	1		T8	9		T14	1
valid[2]	667	1			T3	1		T8	2		T23	3
valid[3]	675	1			T8	2		T14	3		T23	1
valid[4]	637	1			T3	1		T8	1		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	94	1			T8	2		T26	1		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	126	1			T8	1		T23	1		T28	2
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T3	1		T8	3		T47	1
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T14	1		T27	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T8	1		T23	2		T25	1
auto[0]	auto[0]	valid[2]	auto[1]	138	1			T8	1		T23	1		T27	2
auto[0]	auto[0]	valid[3]	auto[0]	122	1			T45	1		T53	1		T38	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T14	2		T27	2		T28	1
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T3	1		T47	1		T50	1
auto[0]	auto[0]	valid[4]	auto[1]	156	1			T14	1		T23	1		T28	2
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T3	1		T8	1		T53	1
auto[0]	auto[1]	valid[0]	auto[1]	152	1			T8	1		T29	1		T87	1
auto[0]	auto[1]	valid[1]	auto[0]	112	1			T8	3		T25	1		T53	1
auto[0]	auto[1]	valid[1]	auto[1]	131	1			T29	3		T87	3		T88	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T45	1		T53	2		T47	2
auto[0]	auto[1]	valid[2]	auto[1]	161	1			T3	1		T28	2		T87	4
auto[0]	auto[1]	valid[3]	auto[0]	105	1			T25	1		T26	1		T52	2
auto[0]	auto[1]	valid[3]	auto[1]	155	1			T14	1		T27	1		T87	1
auto[0]	auto[1]	valid[4]	auto[0]	106	1			T8	1		T26	3		T52	2
auto[0]	auto[1]	valid[4]	auto[1]	148	1			T14	1		T23	1		T27	2
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T25	1		T47	1		T282	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T8	1		T25	1		T47	1
auto[1]	auto[0]	valid[2]	auto[0]	58	1			T53	1		T17	1		T281	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T8	2		T26	1		T277	1
auto[1]	auto[0]	valid[4]	auto[0]	63	1			T23	1		T48	3		T170	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T8	2		T38	1		T170	2
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T8	2		T23	1		T86	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T51	1		T47	1		T86	1
auto[1]	auto[1]	valid[3]	auto[0]	62	1			T23	1		T38	1		T125	1
auto[1]	auto[1]	valid[4]	auto[0]	55	1			T23	1		T38	1		T48	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal