Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47179

1

T3

164

T8

400

T23

272

auto[1]

14680

1

T3

26

T8

82

T14

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44751

1

T3

128

T8

344

T14

6

auto[1]

17108

1

T3

62

T8

138

T23

110

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31612	1			T3	100		T8	259		T14	6
others[1]	5247	1			T3	15		T8	42		T23	25
others[2]	5245	1			T3	18		T8	37		T23	25
others[3]	6018	1			T3	23		T8	46		T23	35
interest[1]	3458	1			T3	9		T8	28		T23	20
interest[4]	20776	1			T3	63		T8	169		T14	6
interest[64]	10279	1			T3	25		T8	70		T23	60

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15251	1			T3	51		T8	145		T23	83
auto[0]	auto[0]	others[1]	2678	1			T3	7		T8	20		T23	12
auto[0]	auto[0]	others[2]	2601	1			T3	12		T8	17		T23	16
auto[0]	auto[0]	others[3]	2902	1			T3	13		T8	22		T23	18
auto[0]	auto[0]	interest[1]	1688	1			T3	4		T8	17		T23	6
auto[0]	auto[0]	interest[4]	9913	1			T3	32		T8	95		T23	50
auto[0]	auto[0]	interest[64]	4951	1			T3	15		T8	41		T23	27
auto[0]	auto[1]	others[0]	7693	1			T3	16		T8	47		T14	6
auto[0]	auto[1]	others[1]	1164	1			T8	11		T23	4		T52	2
auto[0]	auto[1]	others[2]	1188	1			T3	1		T8	4		T23	2
auto[0]	auto[1]	others[3]	1411	1			T3	4		T8	5		T23	3
auto[0]	auto[1]	interest[1]	809	1			T3	2		T8	5		T23	7
auto[0]	auto[1]	interest[4]	5222	1			T3	8		T8	28		T14	6
auto[0]	auto[1]	interest[64]	2415	1			T3	3		T8	10		T23	16
auto[1]	auto[0]	others[0]	8668	1			T3	33		T8	67		T23	56
auto[1]	auto[0]	others[1]	1405	1			T3	8		T8	11		T23	9
auto[1]	auto[0]	others[2]	1456	1			T3	5		T8	16		T23	7
auto[1]	auto[0]	others[3]	1705	1			T3	6		T8	19		T23	14
auto[1]	auto[0]	interest[1]	961	1			T3	3		T8	6		T23	7
auto[1]	auto[0]	interest[4]	5641	1			T3	23		T8	46		T23	39
auto[1]	auto[0]	interest[64]	2913	1			T3	7		T8	19		T23	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal