Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T84 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2920522917 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:32 PM PDT 24 27181898 ps
T1040 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2457164563 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:51 PM PDT 24 14316181 ps
T101 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2748665384 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:46 PM PDT 24 1219380066 ps
T103 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1383430155 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:50 PM PDT 24 435465624 ps
T118 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4266127240 Jul 09 05:04:47 PM PDT 24 Jul 09 05:05:13 PM PDT 24 850715459 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2131888958 Jul 09 05:04:45 PM PDT 24 Jul 09 05:04:51 PM PDT 24 201435060 ps
T122 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2186367435 Jul 09 05:04:46 PM PDT 24 Jul 09 05:05:03 PM PDT 24 216402960 ps
T1041 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1052787522 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:41 PM PDT 24 154718691 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.563622374 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:38 PM PDT 24 565339698 ps
T136 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4207297631 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:40 PM PDT 24 2424346607 ps
T121 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1277659791 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:44 PM PDT 24 107060763 ps
T1042 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1356005802 Jul 09 05:04:45 PM PDT 24 Jul 09 05:04:50 PM PDT 24 60345120 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1916425677 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:31 PM PDT 24 11466340 ps
T164 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4213758316 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:45 PM PDT 24 185857839 ps
T104 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1468322584 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:36 PM PDT 24 683949682 ps
T128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2645598942 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:40 PM PDT 24 36279495 ps
T105 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1350011485 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:30 PM PDT 24 43373695 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.39144014 Jul 09 05:04:44 PM PDT 24 Jul 09 05:04:48 PM PDT 24 13479359 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3680467616 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:42 PM PDT 24 936345171 ps
T1045 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2129682798 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:45 PM PDT 24 156923939 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1636367194 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:33 PM PDT 24 88909900 ps
T1046 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3363851693 Jul 09 05:04:47 PM PDT 24 Jul 09 05:04:52 PM PDT 24 45268607 ps
T1047 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.688210755 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:54 PM PDT 24 14677395 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.623352883 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:47 PM PDT 24 1816023454 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2848586786 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:30 PM PDT 24 223029000 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1010820330 Jul 09 05:04:34 PM PDT 24 Jul 09 05:04:36 PM PDT 24 85790209 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1642344662 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:42 PM PDT 24 3088103417 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2226529607 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:39 PM PDT 24 204346716 ps
T1051 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3330658239 Jul 09 05:04:48 PM PDT 24 Jul 09 05:04:53 PM PDT 24 18216539 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3187539458 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:33 PM PDT 24 16156575 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3286761656 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:30 PM PDT 24 53064500 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2109891964 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:39 PM PDT 24 135048369 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.984194170 Jul 09 05:04:27 PM PDT 24 Jul 09 05:04:29 PM PDT 24 29001798 ps
T131 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.714108782 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:44 PM PDT 24 3133498819 ps
T132 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2011987493 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:40 PM PDT 24 984143039 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2516953378 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:39 PM PDT 24 183981923 ps
T1054 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.272078730 Jul 09 05:04:44 PM PDT 24 Jul 09 05:04:52 PM PDT 24 205838314 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.534581182 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:42 PM PDT 24 218596022 ps
T1056 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.866693515 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:46 PM PDT 24 43457677 ps
T165 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2920983612 Jul 09 05:04:42 PM PDT 24 Jul 09 05:05:02 PM PDT 24 726333811 ps
T108 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3291375699 Jul 09 05:04:45 PM PDT 24 Jul 09 05:04:52 PM PDT 24 490583410 ps
T172 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1271285378 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:50 PM PDT 24 266110400 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1854565422 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:44 PM PDT 24 65381389 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1833733619 Jul 09 05:04:40 PM PDT 24 Jul 09 05:05:05 PM PDT 24 1358632533 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.422635955 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:37 PM PDT 24 37614272 ps
T1060 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2877060259 Jul 09 05:04:45 PM PDT 24 Jul 09 05:04:50 PM PDT 24 47814606 ps
T134 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.750964403 Jul 09 05:04:38 PM PDT 24 Jul 09 05:04:41 PM PDT 24 63176608 ps
T1061 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.867333452 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:47 PM PDT 24 47772989 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2247387367 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:32 PM PDT 24 73194521 ps
T1063 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3451589379 Jul 09 05:04:38 PM PDT 24 Jul 09 05:04:41 PM PDT 24 137786214 ps
T135 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2089986217 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:46 PM PDT 24 242419854 ps
T1064 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.521588704 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:47 PM PDT 24 51810946 ps
T1065 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.648153556 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:48 PM PDT 24 36243037 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3022130381 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:27 PM PDT 24 156608314 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3734144138 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:59 PM PDT 24 4959711467 ps
T1067 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1970052609 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:33 PM PDT 24 11376505 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2291448452 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:39 PM PDT 24 59311378 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.121758902 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:29 PM PDT 24 23988126 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1872152285 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:33 PM PDT 24 25263423 ps
T1071 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2848325100 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:39 PM PDT 24 55924256 ps
T1072 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3175880624 Jul 09 05:04:39 PM PDT 24 Jul 09 05:04:45 PM PDT 24 417666100 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2686133234 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:52 PM PDT 24 52158220 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4076363615 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:47 PM PDT 24 30438622 ps
T1074 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4133823960 Jul 09 05:04:43 PM PDT 24 Jul 09 05:05:04 PM PDT 24 5664945604 ps
T116 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1185081049 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:37 PM PDT 24 204884481 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2007598135 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:32 PM PDT 24 27889061 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.176294131 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:35 PM PDT 24 152260150 ps
T1077 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2908434379 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:42 PM PDT 24 16559992 ps
T1078 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.758786544 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:45 PM PDT 24 36372010 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3034756424 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:29 PM PDT 24 55035764 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.950132411 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:48 PM PDT 24 717905419 ps
T1081 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2175973956 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:55 PM PDT 24 11790975 ps
T1082 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4212477364 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:54 PM PDT 24 13743592 ps
T138 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.262934529 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:34 PM PDT 24 197895300 ps
T1083 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.309879473 Jul 09 05:04:31 PM PDT 24 Jul 09 05:04:33 PM PDT 24 12433705 ps
T1084 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1232816487 Jul 09 05:04:38 PM PDT 24 Jul 09 05:04:41 PM PDT 24 78839552 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3812538720 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:36 PM PDT 24 149658765 ps
T1085 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3794866527 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:54 PM PDT 24 200102364 ps
T114 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2895875840 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:47 PM PDT 24 1243949655 ps
T139 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.630596936 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:32 PM PDT 24 51827458 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2920781476 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:45 PM PDT 24 46475192 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.658021578 Jul 09 05:04:38 PM PDT 24 Jul 09 05:05:01 PM PDT 24 3595585013 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2049310656 Jul 09 05:04:33 PM PDT 24 Jul 09 05:04:34 PM PDT 24 14179657 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1824581494 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:31 PM PDT 24 43258929 ps
T1090 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1888755353 Jul 09 05:04:44 PM PDT 24 Jul 09 05:04:48 PM PDT 24 53046283 ps
T85 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2853136141 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:32 PM PDT 24 135726709 ps
T1091 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1696121226 Jul 09 05:04:44 PM PDT 24 Jul 09 05:04:48 PM PDT 24 39156435 ps
T1092 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2114078537 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:54 PM PDT 24 44585769 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2299220013 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:28 PM PDT 24 263055926 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.335945259 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:27 PM PDT 24 13063623 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.264998161 Jul 09 05:04:29 PM PDT 24 Jul 09 05:04:33 PM PDT 24 717137200 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3375131768 Jul 09 05:04:22 PM PDT 24 Jul 09 05:04:25 PM PDT 24 41761594 ps
T1096 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1704323288 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:43 PM PDT 24 413612469 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.45983071 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:39 PM PDT 24 48010307 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3904322607 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:54 PM PDT 24 7074725391 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.185587572 Jul 09 05:04:42 PM PDT 24 Jul 09 05:04:59 PM PDT 24 832374352 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1459713714 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:47 PM PDT 24 1427809072 ps
T1101 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2461409725 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:42 PM PDT 24 72144044 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.349799 Jul 09 05:04:38 PM PDT 24 Jul 09 05:04:41 PM PDT 24 103814971 ps
T1103 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.481856737 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:43 PM PDT 24 14154545 ps
T1104 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3803944322 Jul 09 05:04:31 PM PDT 24 Jul 09 05:04:36 PM PDT 24 138606188 ps
T1105 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.458421185 Jul 09 05:04:27 PM PDT 24 Jul 09 05:04:30 PM PDT 24 61041331 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2151423377 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:37 PM PDT 24 226757965 ps
T1107 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.100412404 Jul 09 05:04:34 PM PDT 24 Jul 09 05:04:38 PM PDT 24 236375002 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2727752696 Jul 09 05:04:30 PM PDT 24 Jul 09 05:04:32 PM PDT 24 26782091 ps
T1109 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2046623732 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:47 PM PDT 24 298919728 ps
T1110 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.815508500 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:48 PM PDT 24 13897211 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.910091985 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:41 PM PDT 24 46159447 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3254828658 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:34 PM PDT 24 18509462 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3686627284 Jul 09 05:04:39 PM PDT 24 Jul 09 05:04:41 PM PDT 24 57293933 ps
T1114 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2003199141 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:54 PM PDT 24 66963203 ps
T1115 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2035038530 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:45 PM PDT 24 694308111 ps
T113 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3202737152 Jul 09 05:04:33 PM PDT 24 Jul 09 05:04:49 PM PDT 24 2287184113 ps
T1116 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2227956411 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:54 PM PDT 24 104547131 ps
T112 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.41470124 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:53 PM PDT 24 39762383 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2145902343 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:46 PM PDT 24 1244932593 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2450703429 Jul 09 05:04:34 PM PDT 24 Jul 09 05:04:39 PM PDT 24 108263701 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2619644956 Jul 09 05:04:23 PM PDT 24 Jul 09 05:04:25 PM PDT 24 205613490 ps
T1120 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3166419201 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:55 PM PDT 24 27436769 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2234931476 Jul 09 05:04:42 PM PDT 24 Jul 09 05:04:46 PM PDT 24 66844008 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3830678304 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:43 PM PDT 24 17254401 ps
T1123 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1885663434 Jul 09 05:04:37 PM PDT 24 Jul 09 05:04:43 PM PDT 24 304314564 ps
T1124 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.46335669 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:43 PM PDT 24 144916147 ps
T1125 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3846739803 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:36 PM PDT 24 132364269 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3356016520 Jul 09 05:04:25 PM PDT 24 Jul 09 05:04:33 PM PDT 24 109503205 ps
T1127 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2985918291 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:49 PM PDT 24 191836348 ps
T1128 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.466178401 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:41 PM PDT 24 53185578 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1523492989 Jul 09 05:04:40 PM PDT 24 Jul 09 05:04:43 PM PDT 24 62604646 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1779863494 Jul 09 05:04:28 PM PDT 24 Jul 09 05:04:32 PM PDT 24 562275999 ps
T1131 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2651662452 Jul 09 05:04:42 PM PDT 24 Jul 09 05:04:45 PM PDT 24 43537835 ps
T1132 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.408742193 Jul 09 05:04:26 PM PDT 24 Jul 09 05:04:30 PM PDT 24 426518046 ps
T1133 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.86352273 Jul 09 05:04:42 PM PDT 24 Jul 09 05:04:45 PM PDT 24 39376490 ps
T1134 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1517694487 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 45341709 ps
T1135 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2222485418 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:47 PM PDT 24 109161674 ps
T1136 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3989184785 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:48 PM PDT 24 226804976 ps
T1137 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3707897972 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:44 PM PDT 24 24901391 ps
T1138 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2211570150 Jul 09 05:04:44 PM PDT 24 Jul 09 05:04:50 PM PDT 24 110882326 ps
T1139 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.138806069 Jul 09 05:04:24 PM PDT 24 Jul 09 05:04:27 PM PDT 24 205645455 ps
T1140 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1526236430 Jul 09 05:04:46 PM PDT 24 Jul 09 05:05:03 PM PDT 24 4327524958 ps
T1141 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1124339908 Jul 09 05:04:31 PM PDT 24 Jul 09 05:04:37 PM PDT 24 944386450 ps
T1142 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.974763115 Jul 09 05:04:31 PM PDT 24 Jul 09 05:04:39 PM PDT 24 850221105 ps
T1143 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.375402713 Jul 09 05:04:36 PM PDT 24 Jul 09 05:04:39 PM PDT 24 98126933 ps
T171 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.981287735 Jul 09 05:04:47 PM PDT 24 Jul 09 05:04:56 PM PDT 24 201815054 ps
T1144 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4019082363 Jul 09 05:04:41 PM PDT 24 Jul 09 05:04:48 PM PDT 24 191453549 ps
T1145 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3450001426 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:53 PM PDT 24 75649753 ps
T1146 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2705189526 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:54 PM PDT 24 13166667 ps
T1147 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.718098072 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:58 PM PDT 24 54503291 ps
T1148 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1494117155 Jul 09 05:04:43 PM PDT 24 Jul 09 05:04:48 PM PDT 24 29356393 ps
T1149 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.200584184 Jul 09 05:04:35 PM PDT 24 Jul 09 05:04:38 PM PDT 24 32114819 ps
T1150 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.451425034 Jul 09 05:04:31 PM PDT 24 Jul 09 05:04:34 PM PDT 24 281111809 ps
T1151 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1229794309 Jul 09 05:04:32 PM PDT 24 Jul 09 05:04:35 PM PDT 24 151432607 ps

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2438392536
Short name T3
Test name
Test status
Simulation time 81393006451 ps
CPU time 160.87 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:32:36 PM PDT 24
Peak memory 261336 kb
Host smart-f86c785f-368c-4b7c-9802-bf3523aae9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438392536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2438392536
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1452608158
Short name T17
Test name
Test status
Simulation time 49870575610 ps
CPU time 467.56 seconds
Started Jul 09 05:29:44 PM PDT 24
Finished Jul 09 05:37:33 PM PDT 24
Peak memory 280628 kb
Host smart-30d8bae1-fd3b-4438-b537-116ea3432809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452608158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1452608158
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2606471582
Short name T47
Test name
Test status
Simulation time 317796609096 ps
CPU time 742.82 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 267716 kb
Host smart-93db8a58-0c2c-40bd-bb1c-fa3af950cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606471582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2606471582
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1265179957
Short name T99
Test name
Test status
Simulation time 1249459825 ps
CPU time 24.1 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 215424 kb
Host smart-890e0299-a844-45db-8ea5-24c7a5095c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265179957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1265179957
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3487880707
Short name T15
Test name
Test status
Simulation time 38019733264 ps
CPU time 335.37 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:34:18 PM PDT 24
Peak memory 274744 kb
Host smart-43c2e182-dbbb-44f6-a757-494c40a9ddbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487880707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3487880707
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2382576372
Short name T68
Test name
Test status
Simulation time 23965303 ps
CPU time 0.79 seconds
Started Jul 09 05:28:07 PM PDT 24
Finished Jul 09 05:28:10 PM PDT 24
Peak memory 217064 kb
Host smart-b2ad5e50-32f8-4554-b79c-1198b479a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382576372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2382576372
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.425618530
Short name T16
Test name
Test status
Simulation time 15146860262 ps
CPU time 234.68 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:34:19 PM PDT 24
Peak memory 282888 kb
Host smart-4a51cc7d-eabb-4943-897d-686883f4aa3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425618530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.425618530
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1698714691
Short name T23
Test name
Test status
Simulation time 11485965884 ps
CPU time 83.19 seconds
Started Jul 09 05:29:12 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 264544 kb
Host smart-eb15994c-6847-4dc1-a856-5271c535540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698714691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1698714691
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2800987206
Short name T184
Test name
Test status
Simulation time 177502057804 ps
CPU time 505.83 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:38:34 PM PDT 24
Peak memory 283088 kb
Host smart-28c5189d-2d4a-4353-a307-e768ae865dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800987206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2800987206
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1350011485
Short name T105
Test name
Test status
Simulation time 43373695 ps
CPU time 2.7 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 215624 kb
Host smart-c4553cd0-e0a7-4ac4-b343-49ab720a9001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350011485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
350011485
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.501045859
Short name T69
Test name
Test status
Simulation time 460702771 ps
CPU time 1.02 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:11 PM PDT 24
Peak memory 236284 kb
Host smart-f0a38139-a098-491c-964b-444c8d337ab0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501045859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.501045859
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.429685505
Short name T158
Test name
Test status
Simulation time 20545760531 ps
CPU time 57.1 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:31:06 PM PDT 24
Peak memory 237180 kb
Host smart-b228dd43-a128-4abd-a05f-49e01b8523a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429685505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.429685505
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1051133753
Short name T48
Test name
Test status
Simulation time 559807950329 ps
CPU time 451.5 seconds
Started Jul 09 05:29:12 PM PDT 24
Finished Jul 09 05:36:45 PM PDT 24
Peak memory 266392 kb
Host smart-9143951e-c3a7-453c-bb72-88db62a9c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051133753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1051133753
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.898709385
Short name T30
Test name
Test status
Simulation time 3682508807 ps
CPU time 70.89 seconds
Started Jul 09 05:30:35 PM PDT 24
Finished Jul 09 05:31:47 PM PDT 24
Peak memory 252248 kb
Host smart-9ba6e0ce-3ee1-4b65-88f9-e2d589a8166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898709385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.898709385
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.714108782
Short name T131
Test name
Test status
Simulation time 3133498819 ps
CPU time 16.49 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:44 PM PDT 24
Peak memory 215468 kb
Host smart-0af1b3b4-2cb6-42ca-aa9e-9362f12605d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714108782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.714108782
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1285748729
Short name T222
Test name
Test status
Simulation time 60330790744 ps
CPU time 604.85 seconds
Started Jul 09 05:29:53 PM PDT 24
Finished Jul 09 05:39:59 PM PDT 24
Peak memory 268124 kb
Host smart-161cbd40-bba8-4a43-9597-f14ed7a4c9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285748729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1285748729
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1535361506
Short name T19
Test name
Test status
Simulation time 47039017976 ps
CPU time 417.21 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:35:57 PM PDT 24
Peak memory 252024 kb
Host smart-afa8e190-cceb-408d-a4a9-7c3bdfb920cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535361506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1535361506
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1507558315
Short name T212
Test name
Test status
Simulation time 4794285238 ps
CPU time 95.22 seconds
Started Jul 09 05:29:32 PM PDT 24
Finished Jul 09 05:31:08 PM PDT 24
Peak memory 256192 kb
Host smart-4238daca-e21a-4088-a6f4-3303bffcc70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507558315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1507558315
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3847089170
Short name T173
Test name
Test status
Simulation time 8365014840 ps
CPU time 81.38 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:31:03 PM PDT 24
Peak memory 263648 kb
Host smart-4edbf320-f9d2-4547-a246-fcbc4faac8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847089170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3847089170
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2780842026
Short name T32
Test name
Test status
Simulation time 88237448 ps
CPU time 1.01 seconds
Started Jul 09 05:28:04 PM PDT 24
Finished Jul 09 05:28:05 PM PDT 24
Peak memory 217540 kb
Host smart-465d4724-d0c8-4528-bf49-da8b48d05b64
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780842026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2780842026
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1073897513
Short name T49
Test name
Test status
Simulation time 6429522349 ps
CPU time 84.46 seconds
Started Jul 09 05:28:58 PM PDT 24
Finished Jul 09 05:30:23 PM PDT 24
Peak memory 265204 kb
Host smart-6b2bd3fd-8bad-4090-b4fd-d052c525b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073897513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1073897513
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1700716491
Short name T200
Test name
Test status
Simulation time 84050240480 ps
CPU time 217.73 seconds
Started Jul 09 05:30:05 PM PDT 24
Finished Jul 09 05:33:43 PM PDT 24
Peak memory 266884 kb
Host smart-b12437f2-a8f1-4168-be6d-ef262523fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700716491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1700716491
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1100776739
Short name T176
Test name
Test status
Simulation time 17676492931 ps
CPU time 73.59 seconds
Started Jul 09 05:30:26 PM PDT 24
Finished Jul 09 05:31:41 PM PDT 24
Peak memory 255216 kb
Host smart-5ed0125d-bf2f-4a9f-826e-2c0e26682dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100776739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1100776739
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1380870317
Short name T25
Test name
Test status
Simulation time 55619251354 ps
CPU time 136.53 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 250604 kb
Host smart-8cddf0d8-3067-47b7-b4b9-42001a3c479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380870317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1380870317
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3824595845
Short name T6
Test name
Test status
Simulation time 72459615 ps
CPU time 0.8 seconds
Started Jul 09 05:30:36 PM PDT 24
Finished Jul 09 05:30:37 PM PDT 24
Peak memory 205816 kb
Host smart-4216f4a6-a59d-4dd1-bd77-84b6140d0f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824595845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3824595845
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2156158160
Short name T38
Test name
Test status
Simulation time 375171467488 ps
CPU time 627.5 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:39:19 PM PDT 24
Peak memory 266804 kb
Host smart-ea5578cf-c8bf-488f-b016-7fc8bb1640d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156158160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2156158160
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2777181969
Short name T150
Test name
Test status
Simulation time 35055457894 ps
CPU time 340.27 seconds
Started Jul 09 05:29:32 PM PDT 24
Finished Jul 09 05:35:13 PM PDT 24
Peak memory 250352 kb
Host smart-fe96b1da-6a13-4f70-869f-bc9c615bfdb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777181969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2777181969
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3429498537
Short name T247
Test name
Test status
Simulation time 418638033443 ps
CPU time 322.55 seconds
Started Jul 09 05:29:28 PM PDT 24
Finished Jul 09 05:34:51 PM PDT 24
Peak memory 263744 kb
Host smart-e53ee9d6-e98c-4fb2-ae94-d111bb55e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429498537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3429498537
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1557665640
Short name T201
Test name
Test status
Simulation time 49151888152 ps
CPU time 499.52 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:38:02 PM PDT 24
Peak memory 266892 kb
Host smart-906c5952-a957-4944-90cf-f5351ac30db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557665640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1557665640
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1450603098
Short name T54
Test name
Test status
Simulation time 292944284854 ps
CPU time 318.37 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:35:29 PM PDT 24
Peak memory 274636 kb
Host smart-17e4bc35-caab-44dd-8352-bc3a4fad4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450603098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1450603098
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.249875494
Short name T92
Test name
Test status
Simulation time 23419022998 ps
CPU time 158.11 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:33:00 PM PDT 24
Peak memory 250284 kb
Host smart-84721a33-ea4c-4498-b5d9-eaac05e9fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249875494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.249875494
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3812538720
Short name T111
Test name
Test status
Simulation time 149658765 ps
CPU time 4.8 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:36 PM PDT 24
Peak memory 215624 kb
Host smart-a09af15d-edf9-445f-85cf-ed01f3196f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812538720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
812538720
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3376882849
Short name T159
Test name
Test status
Simulation time 1985553696 ps
CPU time 12.08 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:32 PM PDT 24
Peak memory 233784 kb
Host smart-f39a33b3-7b6c-46f5-87c4-f40e103c5337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376882849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3376882849
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3797230893
Short name T250
Test name
Test status
Simulation time 8287576886 ps
CPU time 99.74 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:31:19 PM PDT 24
Peak memory 268684 kb
Host smart-21f8a6b0-8356-4563-bbc8-bb01fede8998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797230893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3797230893
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2186367435
Short name T122
Test name
Test status
Simulation time 216402960 ps
CPU time 12.67 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 215324 kb
Host smart-6ef6bae9-7558-493b-8867-1981e31a661c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186367435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2186367435
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.677561730
Short name T794
Test name
Test status
Simulation time 56461738822 ps
CPU time 599.12 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:38:48 PM PDT 24
Peak memory 273276 kb
Host smart-7f86596d-eede-4217-99a6-5ed3daba1451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677561730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.677561730
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2993972241
Short name T178
Test name
Test status
Simulation time 10976577037 ps
CPU time 172.83 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:31:35 PM PDT 24
Peak memory 266704 kb
Host smart-e2f773c7-b30c-43e9-9dee-120c9887e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993972241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2993972241
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1271285378
Short name T172
Test name
Test status
Simulation time 266110400 ps
CPU time 13.08 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 215492 kb
Host smart-a5e5b610-b37a-46f4-b1f8-0e55a10ecf59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271285378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1271285378
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4161009713
Short name T96
Test name
Test status
Simulation time 58324252827 ps
CPU time 257.46 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:32:24 PM PDT 24
Peak memory 255624 kb
Host smart-099e2996-b018-49ef-9cc1-88595fe50b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161009713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4161009713
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1011325731
Short name T168
Test name
Test status
Simulation time 4024990142 ps
CPU time 100.12 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 251336 kb
Host smart-3a3fdf41-10b3-44c9-a35a-41a87686c1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011325731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1011325731
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.481643162
Short name T659
Test name
Test status
Simulation time 95485793413 ps
CPU time 520.26 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:37:23 PM PDT 24
Peak memory 283184 kb
Host smart-739f03b5-30c6-4b5c-9477-64739833d16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481643162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.481643162
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1804366800
Short name T79
Test name
Test status
Simulation time 3965064166 ps
CPU time 80.98 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:30:06 PM PDT 24
Peak memory 242684 kb
Host smart-5395a127-782b-4e64-aaa8-5a1257dab3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804366800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1804366800
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2715102027
Short name T269
Test name
Test status
Simulation time 1233966963 ps
CPU time 7.68 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 225540 kb
Host smart-7548cc02-0fb7-438f-b792-8098b6f77e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715102027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2715102027
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1870742812
Short name T729
Test name
Test status
Simulation time 68040477250 ps
CPU time 88.73 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 252752 kb
Host smart-af815792-8fd0-43c3-bf63-acbce51072b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870742812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1870742812
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3414701078
Short name T11
Test name
Test status
Simulation time 2387140093 ps
CPU time 5.2 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:29:32 PM PDT 24
Peak memory 225616 kb
Host smart-a34309fa-8e83-4a70-ac72-3112a6d342ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414701078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3414701078
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3375131768
Short name T1095
Test name
Test status
Simulation time 41761594 ps
CPU time 1.25 seconds
Started Jul 09 05:04:22 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 207156 kb
Host smart-de0d59fb-8c4a-4f72-9b2c-44a387bbafe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375131768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3375131768
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.264998161
Short name T115
Test name
Test status
Simulation time 717137200 ps
CPU time 2.41 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 215660 kb
Host smart-16fd08a2-08a5-4b49-8618-c004f1174212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264998161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.264998161
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3202737152
Short name T113
Test name
Test status
Simulation time 2287184113 ps
CPU time 15.35 seconds
Started Jul 09 05:04:33 PM PDT 24
Finished Jul 09 05:04:49 PM PDT 24
Peak memory 215452 kb
Host smart-132aab0d-af4e-41bc-8c57-4c444cb91d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202737152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3202737152
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.534581182
Short name T1055
Test name
Test status
Simulation time 218596022 ps
CPU time 14.75 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:42 PM PDT 24
Peak memory 207104 kb
Host smart-77d2bae0-3cff-414e-ab99-e78ee2a15e2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534581182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.534581182
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4207297631
Short name T136
Test name
Test status
Simulation time 2424346607 ps
CPU time 14.17 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:40 PM PDT 24
Peak memory 215352 kb
Host smart-9b70ee03-063e-4f1b-9bec-0193d38c498d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207297631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4207297631
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2299220013
Short name T1093
Test name
Test status
Simulation time 263055926 ps
CPU time 3.77 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 216588 kb
Host smart-67f1ad71-1970-4bc3-b93e-42a930e92844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299220013 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2299220013
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2619644956
Short name T1119
Test name
Test status
Simulation time 205613490 ps
CPU time 1.29 seconds
Started Jul 09 05:04:23 PM PDT 24
Finished Jul 09 05:04:25 PM PDT 24
Peak memory 215496 kb
Host smart-2187c656-e27e-4fb2-9147-30ca6d9b6149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619644956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
619644956
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1916425677
Short name T1043
Test name
Test status
Simulation time 11466340 ps
CPU time 0.77 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:31 PM PDT 24
Peak memory 203896 kb
Host smart-9417cd07-0281-455e-a1ff-a08d802443b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916425677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
916425677
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.630596936
Short name T139
Test name
Test status
Simulation time 51827458 ps
CPU time 1.23 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 215408 kb
Host smart-e66cc8af-a8e1-4274-bf9f-e3dcb1e7c741
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630596936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.630596936
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2902885974
Short name T1032
Test name
Test status
Simulation time 12146303 ps
CPU time 0.67 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 203724 kb
Host smart-20c6a9a6-2ac1-446d-8164-b636ad720c81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902885974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2902885974
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3034756424
Short name T1079
Test name
Test status
Simulation time 55035764 ps
CPU time 1.79 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:29 PM PDT 24
Peak memory 215244 kb
Host smart-b3df5638-8726-42b3-953f-4858abf263df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034756424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3034756424
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2748665384
Short name T101
Test name
Test status
Simulation time 1219380066 ps
CPU time 20.34 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 215384 kb
Host smart-a568358d-f0ee-4ce4-92ae-7b39d0cd854a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748665384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2748665384
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3680467616
Short name T129
Test name
Test status
Simulation time 936345171 ps
CPU time 14.47 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:42 PM PDT 24
Peak memory 207216 kb
Host smart-93277ce2-f971-4d25-9516-41936f6400b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680467616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3680467616
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1220944311
Short name T83
Test name
Test status
Simulation time 68842862 ps
CPU time 1.38 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:26 PM PDT 24
Peak memory 207112 kb
Host smart-26e5a574-4c84-43a0-a92d-dac79c3d9e60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220944311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1220944311
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3286761656
Short name T117
Test name
Test status
Simulation time 53064500 ps
CPU time 4.03 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 218440 kb
Host smart-f6520003-f5db-45bf-8bbd-8b4f036e55af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286761656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3286761656
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.138806069
Short name T1139
Test name
Test status
Simulation time 205645455 ps
CPU time 1.27 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 215408 kb
Host smart-2c1aaf89-cfc2-4a32-9012-9742dac28ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138806069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.138806069
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3318395292
Short name T1033
Test name
Test status
Simulation time 32708072 ps
CPU time 0.71 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 203860 kb
Host smart-1ae59f75-af32-487a-b16b-88ec160d79b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318395292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
318395292
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1636367194
Short name T130
Test name
Test status
Simulation time 88909900 ps
CPU time 2.21 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 215396 kb
Host smart-af99f72d-4c26-45ce-9718-4e8b243e7536
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636367194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1636367194
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.335945259
Short name T1094
Test name
Test status
Simulation time 13063623 ps
CPU time 0.7 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 204084 kb
Host smart-6f54ee40-ef55-4d86-897b-a3325892d03a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335945259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.335945259
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1779863494
Short name T1130
Test name
Test status
Simulation time 562275999 ps
CPU time 3.03 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 215392 kb
Host smart-e267af2c-bcf6-4042-8f5e-d1c470b6d2f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779863494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1779863494
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3022130381
Short name T110
Test name
Test status
Simulation time 156608314 ps
CPU time 2.34 seconds
Started Jul 09 05:04:24 PM PDT 24
Finished Jul 09 05:04:27 PM PDT 24
Peak memory 215632 kb
Host smart-e9e5dbbc-3b8a-4759-81a9-1d4b6e9d8d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022130381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
022130381
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3356016520
Short name T1126
Test name
Test status
Simulation time 109503205 ps
CPU time 6.67 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 215348 kb
Host smart-97a4c2dd-70d5-479b-8c66-3e8961b28ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356016520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3356016520
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.100412404
Short name T1107
Test name
Test status
Simulation time 236375002 ps
CPU time 2.7 seconds
Started Jul 09 05:04:34 PM PDT 24
Finished Jul 09 05:04:38 PM PDT 24
Peak memory 216436 kb
Host smart-8b4db678-7a17-48a8-aa93-761d90907e6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100412404 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.100412404
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2089986217
Short name T135
Test name
Test status
Simulation time 242419854 ps
CPU time 2.48 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 215416 kb
Host smart-6e1fa675-cfd6-404d-8573-8babc8f43e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089986217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2089986217
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.45983071
Short name T1097
Test name
Test status
Simulation time 48010307 ps
CPU time 0.76 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 203904 kb
Host smart-586e0560-771c-4e4f-8395-b906409d6228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45983071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.45983071
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1885663434
Short name T1123
Test name
Test status
Simulation time 304314564 ps
CPU time 4.47 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 215760 kb
Host smart-a9e986ef-d3c7-47c3-9f40-c4e5fff7fb62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885663434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1885663434
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.375402713
Short name T1143
Test name
Test status
Simulation time 98126933 ps
CPU time 2.73 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215568 kb
Host smart-42d5060d-964a-456f-b6c4-f885e87b945b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375402713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.375402713
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1383430155
Short name T103
Test name
Test status
Simulation time 435465624 ps
CPU time 3.44 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 217564 kb
Host smart-d46e9e27-acdd-4d06-b7a8-c6426d7af873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383430155 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1383430155
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.349799
Short name T1102
Test name
Test status
Simulation time 103814971 ps
CPU time 2.06 seconds
Started Jul 09 05:04:38 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 207580 kb
Host smart-3917fa5c-b641-4ac7-94f5-23ec6f0a3fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.349799
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.422635955
Short name T1059
Test name
Test status
Simulation time 37614272 ps
CPU time 0.76 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:37 PM PDT 24
Peak memory 203852 kb
Host smart-706803c2-ace3-401e-ad94-253169363c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422635955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.422635955
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2035038530
Short name T1115
Test name
Test status
Simulation time 694308111 ps
CPU time 3.78 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215416 kb
Host smart-bd54859c-4588-4a8a-a481-713d7df343c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035038530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2035038530
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3707897972
Short name T1137
Test name
Test status
Simulation time 24901391 ps
CPU time 1.64 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:44 PM PDT 24
Peak memory 215796 kb
Host smart-504aeae6-2ef9-474e-a39d-16db77244be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707897972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3707897972
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3734144138
Short name T1066
Test name
Test status
Simulation time 4959711467 ps
CPU time 20.4 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 215368 kb
Host smart-c1981939-9887-4fed-b2db-d4ba226bb036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734144138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3734144138
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2985918291
Short name T1127
Test name
Test status
Simulation time 191836348 ps
CPU time 1.84 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:49 PM PDT 24
Peak memory 215396 kb
Host smart-c53caa6a-9fbb-4c8d-848d-8bc495590d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985918291 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2985918291
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2234931476
Short name T1121
Test name
Test status
Simulation time 66844008 ps
CPU time 1.29 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 207092 kb
Host smart-0b43412b-746b-400a-ad29-42137fb545c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234931476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2234931476
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.466178401
Short name T1128
Test name
Test status
Simulation time 53185578 ps
CPU time 0.78 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 204196 kb
Host smart-b4343733-0bf9-45c5-bf9e-40c0dd45eddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466178401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.466178401
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3465454918
Short name T1031
Test name
Test status
Simulation time 49853645 ps
CPU time 1.71 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 215392 kb
Host smart-0771428f-ebd2-4757-b7ad-9d373d58268b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465454918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3465454918
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.981287735
Short name T171
Test name
Test status
Simulation time 201815054 ps
CPU time 5.16 seconds
Started Jul 09 05:04:47 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 215640 kb
Host smart-ee0f86a9-d6a4-425a-bc87-57aaca396d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981287735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.981287735
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.185587572
Short name T1099
Test name
Test status
Simulation time 832374352 ps
CPU time 13.61 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 215564 kb
Host smart-6259fdd2-e8c2-43c4-8899-6e8a42cc2bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185587572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.185587572
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1185081049
Short name T116
Test name
Test status
Simulation time 204884481 ps
CPU time 1.67 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:37 PM PDT 24
Peak memory 215216 kb
Host smart-e9579b53-87c7-4925-9f68-829793e61674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185081049 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1185081049
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1494117155
Short name T1148
Test name
Test status
Simulation time 29356393 ps
CPU time 1.82 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 207148 kb
Host smart-9ec038a5-a6ae-46c8-b6ce-bb43ea45b4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494117155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1494117155
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3830678304
Short name T1122
Test name
Test status
Simulation time 17254401 ps
CPU time 0.71 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 204176 kb
Host smart-f09c03dc-9aac-4745-91a0-f97df6d3aec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830678304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3830678304
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3794866527
Short name T1085
Test name
Test status
Simulation time 200102364 ps
CPU time 3.94 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 215372 kb
Host smart-44732370-3875-49ce-9618-986e15e770e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794866527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3794866527
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2461409725
Short name T1101
Test name
Test status
Simulation time 72144044 ps
CPU time 4.25 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:42 PM PDT 24
Peak memory 215556 kb
Host smart-65bfea8c-457f-4d4f-b11d-1885d5ed20e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461409725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2461409725
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2046623732
Short name T1109
Test name
Test status
Simulation time 298919728 ps
CPU time 8.7 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 215788 kb
Host smart-b3f1d10f-b0a1-498c-b087-a212cb78bc99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046623732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2046623732
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2131888958
Short name T119
Test name
Test status
Simulation time 201435060 ps
CPU time 1.85 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:51 PM PDT 24
Peak memory 215384 kb
Host smart-4436c9a4-3f64-47b4-b9e8-8f23c375b24d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131888958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2131888958
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3686627284
Short name T1113
Test name
Test status
Simulation time 57293933 ps
CPU time 1.89 seconds
Started Jul 09 05:04:39 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 207212 kb
Host smart-ccf20605-856f-4480-8a1e-18f7fff492e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686627284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3686627284
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2960362503
Short name T1036
Test name
Test status
Simulation time 47540618 ps
CPU time 0.76 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 203812 kb
Host smart-d16b421c-51b3-45d9-a6c7-f86faeba1ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960362503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2960362503
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3451589379
Short name T1063
Test name
Test status
Simulation time 137786214 ps
CPU time 2.18 seconds
Started Jul 09 05:04:38 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 215308 kb
Host smart-9b724df0-c597-47d9-99b8-34e577491feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451589379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3451589379
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2227956411
Short name T1116
Test name
Test status
Simulation time 104547131 ps
CPU time 3.55 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 215544 kb
Host smart-512f038a-2e6d-4996-9745-a69119c337a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227956411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2227956411
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3291375699
Short name T108
Test name
Test status
Simulation time 490583410 ps
CPU time 2.66 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 216312 kb
Host smart-ec3ffd70-ab3b-4a0e-9d09-aba07aa38df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291375699 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3291375699
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.86352273
Short name T1133
Test name
Test status
Simulation time 39376490 ps
CPU time 1.33 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215344 kb
Host smart-adc05724-1ef9-4af2-812a-40310bb4ebb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86352273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.86352273
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2651662452
Short name T1131
Test name
Test status
Simulation time 43537835 ps
CPU time 0.75 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 203976 kb
Host smart-9730a88c-c0a8-4b19-9d20-4e80f9b1308b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651662452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2651662452
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1854565422
Short name T1057
Test name
Test status
Simulation time 65381389 ps
CPU time 2.06 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:44 PM PDT 24
Peak memory 215316 kb
Host smart-8d6ace56-96b0-4ccf-a572-c5c92bdc7cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854565422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1854565422
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2222485418
Short name T1135
Test name
Test status
Simulation time 109161674 ps
CPU time 3.75 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 215624 kb
Host smart-52e5a40a-f980-48d6-8460-056e37b6a168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222485418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2222485418
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1833733619
Short name T1058
Test name
Test status
Simulation time 1358632533 ps
CPU time 23.96 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 215432 kb
Host smart-a3c7806b-f2db-4569-8ad2-27818851a069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833733619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1833733619
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.46335669
Short name T1124
Test name
Test status
Simulation time 144916147 ps
CPU time 2.76 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 216472 kb
Host smart-68278be6-2b48-4b8e-9488-c115f5c7109a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46335669 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.46335669
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.758786544
Short name T1078
Test name
Test status
Simulation time 36372010 ps
CPU time 2.42 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215412 kb
Host smart-e9292819-1ef6-4eae-84a1-3666e7f399f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758786544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.758786544
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4076363615
Short name T1073
Test name
Test status
Simulation time 30438622 ps
CPU time 0.79 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 203852 kb
Host smart-8238165f-a0e3-4c4c-8488-49f4d006aa5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076363615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4076363615
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.866693515
Short name T1056
Test name
Test status
Simulation time 43457677 ps
CPU time 2.63 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 215372 kb
Host smart-83961ccb-3a57-4abe-be68-619e49e4c019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866693515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.866693515
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.41470124
Short name T112
Test name
Test status
Simulation time 39762383 ps
CPU time 2.55 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 216556 kb
Host smart-b15aafd3-5781-4b0d-8f05-db84ea79b9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.41470124
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3989184785
Short name T1136
Test name
Test status
Simulation time 226804976 ps
CPU time 1.71 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 216420 kb
Host smart-026c9cef-9931-46d5-bf66-09d87dc75f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989184785 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3989184785
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1927527255
Short name T163
Test name
Test status
Simulation time 208965507 ps
CPU time 2.69 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 207092 kb
Host smart-62115bdf-bec1-4f93-a040-40d0e39e7ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927527255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1927527255
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2908434379
Short name T1077
Test name
Test status
Simulation time 16559992 ps
CPU time 0.75 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:42 PM PDT 24
Peak memory 203868 kb
Host smart-57173bcb-c4cf-41c7-9319-17dde9c06f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908434379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2908434379
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3175880624
Short name T1072
Test name
Test status
Simulation time 417666100 ps
CPU time 4.78 seconds
Started Jul 09 05:04:39 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215384 kb
Host smart-efea7775-1dd3-4270-b1bc-5c17224f0f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175880624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3175880624
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1523492989
Short name T1129
Test name
Test status
Simulation time 62604646 ps
CPU time 2.1 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 215600 kb
Host smart-4ca8e6df-bd3c-4ca7-a6e7-e64a65c69fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523492989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1523492989
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4266127240
Short name T118
Test name
Test status
Simulation time 850715459 ps
CPU time 21.73 seconds
Started Jul 09 05:04:47 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 215488 kb
Host smart-e0e43574-9b75-40d2-9d41-b063582e8db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266127240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4266127240
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.734677957
Short name T102
Test name
Test status
Simulation time 292899897 ps
CPU time 1.8 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215460 kb
Host smart-2f91245e-4fdb-49e6-a47d-2e32e81bcf09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734677957 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.734677957
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4213758316
Short name T164
Test name
Test status
Simulation time 185857839 ps
CPU time 1.44 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215412 kb
Host smart-641bf9bf-45d1-47f2-8ea3-8837cfd9e063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213758316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4213758316
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1052787522
Short name T1041
Test name
Test status
Simulation time 154718691 ps
CPU time 0.76 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 204268 kb
Host smart-0f859609-9ac1-4297-ae31-b5b6865699b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052787522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1052787522
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.561727674
Short name T1024
Test name
Test status
Simulation time 441008958 ps
CPU time 3.13 seconds
Started Jul 09 05:04:47 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 215444 kb
Host smart-2cbbce9b-9c4d-4d1a-a425-1b778f839aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561727674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.561727674
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4019082363
Short name T1144
Test name
Test status
Simulation time 191453549 ps
CPU time 4.64 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 215724 kb
Host smart-a1f24b86-e936-4117-9cdb-f688008ef2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019082363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4019082363
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4133823960
Short name T1074
Test name
Test status
Simulation time 5664945604 ps
CPU time 18.04 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 215940 kb
Host smart-c4c1ed0e-6807-4f2b-8e29-670a73e87b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133823960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4133823960
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2920781476
Short name T1086
Test name
Test status
Simulation time 46475192 ps
CPU time 1.74 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215376 kb
Host smart-4fcf92bf-fdc8-4b32-94c4-00e7faf7fa4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920781476 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2920781476
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2211570150
Short name T1138
Test name
Test status
Simulation time 110882326 ps
CPU time 2.68 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 207252 kb
Host smart-d7664687-bc0d-4125-9fbd-591e470fb992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211570150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2211570150
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.39144014
Short name T1044
Test name
Test status
Simulation time 13479359 ps
CPU time 0.74 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 203796 kb
Host smart-917655cf-1d18-4465-a427-d7765675cee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.39144014
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2735799974
Short name T1026
Test name
Test status
Simulation time 541910237 ps
CPU time 2.98 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:49 PM PDT 24
Peak memory 215380 kb
Host smart-d130d804-bf3d-4bca-99d9-93b9ede6c0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735799974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2735799974
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2895875840
Short name T114
Test name
Test status
Simulation time 1243949655 ps
CPU time 4.95 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 215660 kb
Host smart-fa2252ba-a6b8-4977-8659-92bac6fd3445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895875840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2895875840
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2920983612
Short name T165
Test name
Test status
Simulation time 726333811 ps
CPU time 16.76 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:05:02 PM PDT 24
Peak memory 215464 kb
Host smart-1ffc3c55-b8bc-4a52-af55-bea8992cef87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920983612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2920983612
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2145902343
Short name T1117
Test name
Test status
Simulation time 1244932593 ps
CPU time 16.46 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 215412 kb
Host smart-50312b02-7aed-45ef-a53f-e9b04c14a0a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145902343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2145902343
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3904322607
Short name T1098
Test name
Test status
Simulation time 7074725391 ps
CPU time 25.37 seconds
Started Jul 09 05:04:28 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 207180 kb
Host smart-69c2135b-de42-4a1d-8748-a1d0464a5e9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904322607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3904322607
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2853136141
Short name T85
Test name
Test status
Simulation time 135726709 ps
CPU time 1.2 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 217392 kb
Host smart-6555807d-2a0b-4fea-8bb9-fa2dd8a33e6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853136141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2853136141
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.408742193
Short name T1132
Test name
Test status
Simulation time 426518046 ps
CPU time 2.98 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 217148 kb
Host smart-1a1f97a9-4f7a-41e6-8cb4-93946e713dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408742193 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.408742193
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.458421185
Short name T1105
Test name
Test status
Simulation time 61041331 ps
CPU time 1.92 seconds
Started Jul 09 05:04:27 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 207300 kb
Host smart-e3d23822-9fd0-4589-b14f-5d6cfe383e79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458421185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.458421185
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.984194170
Short name T1053
Test name
Test status
Simulation time 29001798 ps
CPU time 0.72 seconds
Started Jul 09 05:04:27 PM PDT 24
Finished Jul 09 05:04:29 PM PDT 24
Peak memory 203836 kb
Host smart-1e982e3d-2915-482f-afd3-bb16f62f4d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984194170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.984194170
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.121758902
Short name T1069
Test name
Test status
Simulation time 23988126 ps
CPU time 1.66 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:29 PM PDT 24
Peak memory 215348 kb
Host smart-d6e4cc86-57c6-4eb2-b1f7-ebd8a6e18e29
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121758902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.121758902
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3257429793
Short name T1028
Test name
Test status
Simulation time 33627375 ps
CPU time 0.68 seconds
Started Jul 09 05:04:26 PM PDT 24
Finished Jul 09 05:04:28 PM PDT 24
Peak memory 203744 kb
Host smart-5efe38a3-1ad2-4222-8040-db3aacf67670
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257429793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3257429793
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2848586786
Short name T1048
Test name
Test status
Simulation time 223029000 ps
CPU time 3.56 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:30 PM PDT 24
Peak memory 215392 kb
Host smart-f334f0d9-d04b-42ed-b629-25a60368db43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848586786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2848586786
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1642344662
Short name T120
Test name
Test status
Simulation time 3088103417 ps
CPU time 15.61 seconds
Started Jul 09 05:04:25 PM PDT 24
Finished Jul 09 05:04:42 PM PDT 24
Peak memory 215468 kb
Host smart-3e07556c-5175-4479-a901-bead7ef30fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642344662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1642344662
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.581241046
Short name T1035
Test name
Test status
Simulation time 50272401 ps
CPU time 0.78 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 203968 kb
Host smart-261548a4-f32d-41d7-8403-3a1d3ec6e2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581241046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.581241046
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1517694487
Short name T1134
Test name
Test status
Simulation time 45341709 ps
CPU time 0.79 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 203924 kb
Host smart-d93a5b9b-c2e9-4d61-8cbf-30d254f6a7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517694487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1517694487
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.481856737
Short name T1103
Test name
Test status
Simulation time 14154545 ps
CPU time 0.75 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 203868 kb
Host smart-ef6bedde-c093-44ad-9f34-9f8ec8a335c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481856737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.481856737
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4210598682
Short name T1029
Test name
Test status
Simulation time 23487814 ps
CPU time 0.75 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:51 PM PDT 24
Peak memory 203868 kb
Host smart-8d5fe35b-a3eb-4356-961b-8ec4434145ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210598682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4210598682
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.867333452
Short name T1061
Test name
Test status
Simulation time 47772989 ps
CPU time 0.76 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 204268 kb
Host smart-0e0822cd-fb12-49fc-a0ef-bc74cb206848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867333452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.867333452
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.815508500
Short name T1110
Test name
Test status
Simulation time 13897211 ps
CPU time 0.78 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 203848 kb
Host smart-18fedf7c-6cb6-4f99-94b8-9f54d7128591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815508500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.815508500
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2877060259
Short name T1060
Test name
Test status
Simulation time 47814606 ps
CPU time 0.79 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 203724 kb
Host smart-f1b4faf6-73b3-45db-970e-f3b7f6cfb485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877060259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2877060259
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.648153556
Short name T1065
Test name
Test status
Simulation time 36243037 ps
CPU time 0.75 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 203848 kb
Host smart-41110569-f077-440d-94c7-f520c5d989be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648153556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.648153556
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3363851693
Short name T1046
Test name
Test status
Simulation time 45268607 ps
CPU time 0.71 seconds
Started Jul 09 05:04:47 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 204184 kb
Host smart-8c94ac36-9ddf-4a0f-8368-5c69d913c848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363851693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3363851693
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3519353926
Short name T1034
Test name
Test status
Simulation time 14191724 ps
CPU time 0.7 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:44 PM PDT 24
Peak memory 203808 kb
Host smart-58fe17c6-afa8-4423-87fc-9048a1e17dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519353926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3519353926
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.523329865
Short name T127
Test name
Test status
Simulation time 407530116 ps
CPU time 14.36 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:51 PM PDT 24
Peak memory 215348 kb
Host smart-3d7e60f3-a799-4e4b-b1ad-3b6f0f8cde69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523329865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.523329865
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1526236430
Short name T1140
Test name
Test status
Simulation time 4327524958 ps
CPU time 13.33 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 207396 kb
Host smart-32e31e75-39a8-4bcf-ba4e-cf6093dcc518
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526236430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1526236430
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2920522917
Short name T84
Test name
Test status
Simulation time 27181898 ps
CPU time 0.99 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 207020 kb
Host smart-b3c5e7b1-f990-4afd-8119-1ddabf6ef2af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920522917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2920522917
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2226529607
Short name T1050
Test name
Test status
Simulation time 204346716 ps
CPU time 3.01 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 218016 kb
Host smart-fcb15a82-a8fd-4f7e-a47b-d835951d75a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226529607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2226529607
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2516953378
Short name T133
Test name
Test status
Simulation time 183981923 ps
CPU time 2.7 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215408 kb
Host smart-039f3776-496b-470b-9ae8-c2a1903c6f6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516953378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
516953378
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3254828658
Short name T1112
Test name
Test status
Simulation time 18509462 ps
CPU time 0.74 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:34 PM PDT 24
Peak memory 204164 kb
Host smart-a501493a-4259-4d69-97af-c6948bffc9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254828658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
254828658
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2291448452
Short name T1068
Test name
Test status
Simulation time 59311378 ps
CPU time 2.05 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215468 kb
Host smart-6f0fd613-bbdb-4e21-b566-a3e88463133e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291448452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2291448452
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1824581494
Short name T1089
Test name
Test status
Simulation time 43258929 ps
CPU time 0.67 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:31 PM PDT 24
Peak memory 203824 kb
Host smart-ece57e66-007c-4d64-9cc8-435c1441c854
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824581494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1824581494
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2450703429
Short name T1118
Test name
Test status
Simulation time 108263701 ps
CPU time 3.69 seconds
Started Jul 09 05:04:34 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215340 kb
Host smart-cbeba768-c150-4536-aa82-8b93595ec2e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450703429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2450703429
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2686133234
Short name T109
Test name
Test status
Simulation time 52158220 ps
CPU time 1.97 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 215564 kb
Host smart-e4703cb1-3aeb-46ba-b9ca-f8604714e864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686133234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
686133234
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.563622374
Short name T123
Test name
Test status
Simulation time 565339698 ps
CPU time 7.59 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:38 PM PDT 24
Peak memory 215336 kb
Host smart-52eab69f-8618-4211-bfe8-fdcccc24d150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563622374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.563622374
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1888755353
Short name T1090
Test name
Test status
Simulation time 53046283 ps
CPU time 0.8 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 203916 kb
Host smart-ca28288d-d2fe-4d8e-9248-5920822b17ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888755353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1888755353
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1641027132
Short name T1027
Test name
Test status
Simulation time 107298547 ps
CPU time 0.74 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 204260 kb
Host smart-8beb812d-a00c-49e0-9b96-ae9dfb1e9be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641027132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1641027132
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.688210755
Short name T1047
Test name
Test status
Simulation time 14677395 ps
CPU time 0.73 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 204200 kb
Host smart-d8dd730e-7518-4417-809c-94dbac0d49c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688210755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.688210755
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.66906363
Short name T1038
Test name
Test status
Simulation time 21685318 ps
CPU time 0.74 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 204140 kb
Host smart-0b7320b8-1eb7-477d-a100-faf6f46d2fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66906363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.66906363
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1696121226
Short name T1091
Test name
Test status
Simulation time 39156435 ps
CPU time 0.74 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 203800 kb
Host smart-a7e83277-fdf1-4657-813c-b89a9118288a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696121226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1696121226
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2114078537
Short name T1092
Test name
Test status
Simulation time 44585769 ps
CPU time 0.74 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 204156 kb
Host smart-453c98dd-f51f-4244-ab06-40100c418f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114078537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2114078537
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3450001426
Short name T1145
Test name
Test status
Simulation time 75649753 ps
CPU time 0.73 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 203936 kb
Host smart-54cbdae8-e4c2-484b-9236-874d0f60cc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450001426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3450001426
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3166419201
Short name T1120
Test name
Test status
Simulation time 27436769 ps
CPU time 0.71 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 204168 kb
Host smart-5b78f39d-a7ff-4a55-a138-6336c4f4f6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166419201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3166419201
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2104452604
Short name T1030
Test name
Test status
Simulation time 13227522 ps
CPU time 0.71 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 203916 kb
Host smart-9af1e3fb-10cb-41c9-a757-7270b2c33bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104452604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2104452604
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2705189526
Short name T1146
Test name
Test status
Simulation time 13166667 ps
CPU time 0.78 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 204120 kb
Host smart-b7a46896-948b-40eb-822f-50406a45fcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705189526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2705189526
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.974763115
Short name T1142
Test name
Test status
Simulation time 850221105 ps
CPU time 7.8 seconds
Started Jul 09 05:04:31 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215388 kb
Host smart-f9d2ac9b-cbf1-418f-8f85-c632f5df530f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974763115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.974763115
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.623352883
Short name T137
Test name
Test status
Simulation time 1816023454 ps
CPU time 15.61 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 207244 kb
Host smart-de463b99-8b26-47fe-8de0-a5b8ab9c8340
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623352883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.623352883
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3187539458
Short name T1052
Test name
Test status
Simulation time 16156575 ps
CPU time 0.98 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 207052 kb
Host smart-53b96aa7-8981-4f97-8741-8069dea36598
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187539458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3187539458
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1872152285
Short name T1070
Test name
Test status
Simulation time 25263423 ps
CPU time 1.88 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 216584 kb
Host smart-58be84b8-3f59-4b76-93bc-f829927e3981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872152285 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1872152285
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1229794309
Short name T1151
Test name
Test status
Simulation time 151432607 ps
CPU time 2.82 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:35 PM PDT 24
Peak memory 215408 kb
Host smart-6558a063-dc4a-4d5f-ad6a-dc3e321c9bed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229794309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
229794309
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2727752696
Short name T1108
Test name
Test status
Simulation time 26782091 ps
CPU time 0.73 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 203912 kb
Host smart-87a7f1c7-0ab4-4c62-9063-bb74a8669b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727752696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
727752696
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1535246679
Short name T126
Test name
Test status
Simulation time 16956311 ps
CPU time 1.26 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:38 PM PDT 24
Peak memory 215416 kb
Host smart-41bd8000-2137-4068-812b-65689922dfa6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535246679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1535246679
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2247387367
Short name T1062
Test name
Test status
Simulation time 73194521 ps
CPU time 0.68 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 203808 kb
Host smart-ace8ab2e-2b5b-412b-b940-6f2f1b9ebfd8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247387367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2247387367
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2007598135
Short name T1075
Test name
Test status
Simulation time 27889061 ps
CPU time 1.82 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:32 PM PDT 24
Peak memory 215300 kb
Host smart-6fd5b034-9b6c-409d-a792-cf86d779feb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007598135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2007598135
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2527110219
Short name T100
Test name
Test status
Simulation time 1691575008 ps
CPU time 20.95 seconds
Started Jul 09 05:04:29 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 215296 kb
Host smart-744ab271-a127-4e6e-9ef7-75da00b269e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527110219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2527110219
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2457164563
Short name T1040
Test name
Test status
Simulation time 14316181 ps
CPU time 0.75 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:51 PM PDT 24
Peak memory 203852 kb
Host smart-149cb870-570c-4b02-9aca-5a258fa28ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457164563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2457164563
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.521588704
Short name T1064
Test name
Test status
Simulation time 51810946 ps
CPU time 0.73 seconds
Started Jul 09 05:04:43 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 204156 kb
Host smart-2f0789a7-4706-4f1b-89d1-307fb04332cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521588704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.521588704
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.718098072
Short name T1147
Test name
Test status
Simulation time 54503291 ps
CPU time 0.76 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:58 PM PDT 24
Peak memory 204192 kb
Host smart-9fdc4d32-ad5a-478f-a672-8a94ff492297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718098072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.718098072
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2041550662
Short name T1037
Test name
Test status
Simulation time 11048106 ps
CPU time 0.69 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:49 PM PDT 24
Peak memory 203816 kb
Host smart-94441be3-df35-4ead-aaf9-703fd6ae4b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041550662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2041550662
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1356005802
Short name T1042
Test name
Test status
Simulation time 60345120 ps
CPU time 0.78 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 203912 kb
Host smart-facff2e1-59a3-4155-a265-b13fd3d5fc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356005802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1356005802
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2175973956
Short name T1081
Test name
Test status
Simulation time 11790975 ps
CPU time 0.72 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 203944 kb
Host smart-0ddb56c2-c9c0-410a-ab63-26d0e398ff06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175973956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2175973956
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4212477364
Short name T1082
Test name
Test status
Simulation time 13743592 ps
CPU time 0.74 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 203928 kb
Host smart-e77d4d66-4718-410b-bf62-493bddb3dec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212477364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4212477364
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2003199141
Short name T1114
Test name
Test status
Simulation time 66963203 ps
CPU time 0.78 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 203852 kb
Host smart-582c9991-f0df-40f1-8668-f0ec10328d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003199141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2003199141
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2079693993
Short name T1025
Test name
Test status
Simulation time 13881697 ps
CPU time 0.75 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 204160 kb
Host smart-2a494eb5-8949-4171-8000-2377a9597f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079693993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2079693993
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3330658239
Short name T1051
Test name
Test status
Simulation time 18216539 ps
CPU time 0.77 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 203956 kb
Host smart-226e7443-40d8-4ffb-b94e-b222088de803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330658239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3330658239
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3803944322
Short name T1104
Test name
Test status
Simulation time 138606188 ps
CPU time 3.51 seconds
Started Jul 09 05:04:31 PM PDT 24
Finished Jul 09 05:04:36 PM PDT 24
Peak memory 217912 kb
Host smart-74d1fa15-05d9-4f4c-bd32-059f666d0b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803944322 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3803944322
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.262934529
Short name T138
Test name
Test status
Simulation time 197895300 ps
CPU time 1.39 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:34 PM PDT 24
Peak memory 207208 kb
Host smart-33e7d265-e5b0-4fcd-af7a-09f80e8b0037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262934529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.262934529
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1970052609
Short name T1067
Test name
Test status
Simulation time 11376505 ps
CPU time 0.71 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 203828 kb
Host smart-648dde75-70f5-46af-8557-e0e6816c2841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970052609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
970052609
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3846739803
Short name T1125
Test name
Test status
Simulation time 132364269 ps
CPU time 3.1 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:36 PM PDT 24
Peak memory 215416 kb
Host smart-c156ebd4-2e4a-42b2-9b28-4123e13b16ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846739803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3846739803
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1468322584
Short name T104
Test name
Test status
Simulation time 683949682 ps
CPU time 4.86 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:36 PM PDT 24
Peak memory 215616 kb
Host smart-494aebe6-ff5b-4f96-bdce-85c09b60b8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468322584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
468322584
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.950132411
Short name T1080
Test name
Test status
Simulation time 717905419 ps
CPU time 16.18 seconds
Started Jul 09 05:04:30 PM PDT 24
Finished Jul 09 05:04:48 PM PDT 24
Peak memory 216604 kb
Host smart-9f9779f4-b2da-4311-abc9-18ae2872ca0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950132411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.950132411
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2651170478
Short name T98
Test name
Test status
Simulation time 149980182 ps
CPU time 3 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 217324 kb
Host smart-76b036e7-c63d-434c-8a88-ebff381f6666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651170478 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2651170478
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1010820330
Short name T1049
Test name
Test status
Simulation time 85790209 ps
CPU time 1.47 seconds
Started Jul 09 05:04:34 PM PDT 24
Finished Jul 09 05:04:36 PM PDT 24
Peak memory 207212 kb
Host smart-b6fd748b-f0ee-4e14-8410-51329cf0492f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010820330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
010820330
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2049310656
Short name T1088
Test name
Test status
Simulation time 14179657 ps
CPU time 0.73 seconds
Started Jul 09 05:04:33 PM PDT 24
Finished Jul 09 05:04:34 PM PDT 24
Peak memory 204272 kb
Host smart-0072ac66-37bd-4578-bb30-dbcbd3c01fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049310656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
049310656
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3593514911
Short name T1039
Test name
Test status
Simulation time 596438276 ps
CPU time 3.99 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 207180 kb
Host smart-7e9bffda-60c0-4153-bac8-d53fef136624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593514911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3593514911
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.451425034
Short name T1150
Test name
Test status
Simulation time 281111809 ps
CPU time 2.21 seconds
Started Jul 09 05:04:31 PM PDT 24
Finished Jul 09 05:04:34 PM PDT 24
Peak memory 215812 kb
Host smart-93b8246d-a889-4122-91a9-80709dd0a839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451425034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.451425034
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1459713714
Short name T1100
Test name
Test status
Simulation time 1427809072 ps
CPU time 3.55 seconds
Started Jul 09 05:04:41 PM PDT 24
Finished Jul 09 05:04:47 PM PDT 24
Peak memory 218560 kb
Host smart-697a9b0c-bd54-46c2-bf6c-5ab2ed66ba6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459713714 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1459713714
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2011987493
Short name T132
Test name
Test status
Simulation time 984143039 ps
CPU time 3.1 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:40 PM PDT 24
Peak memory 215300 kb
Host smart-786b0e92-f688-461b-b783-1864a4df97be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011987493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
011987493
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.309879473
Short name T1083
Test name
Test status
Simulation time 12433705 ps
CPU time 0.75 seconds
Started Jul 09 05:04:31 PM PDT 24
Finished Jul 09 05:04:33 PM PDT 24
Peak memory 203860 kb
Host smart-0f6bec05-23e5-4e01-a51c-1b57c3d645f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309879473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.309879473
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.176294131
Short name T1076
Test name
Test status
Simulation time 152260150 ps
CPU time 1.96 seconds
Started Jul 09 05:04:32 PM PDT 24
Finished Jul 09 05:04:35 PM PDT 24
Peak memory 215380 kb
Host smart-ccad5531-e7a9-4c1d-a958-cc74d3b12bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176294131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.176294131
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1124339908
Short name T1141
Test name
Test status
Simulation time 944386450 ps
CPU time 5.55 seconds
Started Jul 09 05:04:31 PM PDT 24
Finished Jul 09 05:04:37 PM PDT 24
Peak memory 215504 kb
Host smart-ac9d11a6-79dc-4e96-8f28-139ff69e4053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124339908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
124339908
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.658021578
Short name T1087
Test name
Test status
Simulation time 3595585013 ps
CPU time 22.5 seconds
Started Jul 09 05:04:38 PM PDT 24
Finished Jul 09 05:05:01 PM PDT 24
Peak memory 216712 kb
Host smart-687db6a5-9d3c-4eb3-8b5e-ce90cbff820a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658021578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.658021578
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.272078730
Short name T1054
Test name
Test status
Simulation time 205838314 ps
CPU time 3.83 seconds
Started Jul 09 05:04:44 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 217728 kb
Host smart-b80aed6c-23ab-4aef-a9f5-5395bee0b3f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272078730 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.272078730
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2645598942
Short name T128
Test name
Test status
Simulation time 36279495 ps
CPU time 2.5 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:40 PM PDT 24
Peak memory 215476 kb
Host smart-8085c1cc-9051-458f-b4ea-c644ce3b10a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645598942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
645598942
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2848325100
Short name T1071
Test name
Test status
Simulation time 55924256 ps
CPU time 0.75 seconds
Started Jul 09 05:04:37 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 203772 kb
Host smart-8c3a9b41-2703-417d-a174-3ef61bafe0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848325100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
848325100
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1232816487
Short name T1084
Test name
Test status
Simulation time 78839552 ps
CPU time 2.03 seconds
Started Jul 09 05:04:38 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 215328 kb
Host smart-6ec4ae01-cf84-47b8-9f42-fcf765e58154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232816487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1232816487
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2109891964
Short name T107
Test name
Test status
Simulation time 135048369 ps
CPU time 3.62 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:39 PM PDT 24
Peak memory 215616 kb
Host smart-63391403-13c2-4231-89c3-7daac174b219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109891964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
109891964
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1704323288
Short name T1096
Test name
Test status
Simulation time 413612469 ps
CPU time 6.27 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:43 PM PDT 24
Peak memory 215488 kb
Host smart-255223a8-ec42-4dc0-8596-08989c0317a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704323288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1704323288
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2151423377
Short name T1106
Test name
Test status
Simulation time 226757965 ps
CPU time 1.87 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:37 PM PDT 24
Peak memory 215460 kb
Host smart-be9a757f-044b-4584-a00e-7f3226b163c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151423377 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2151423377
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.750964403
Short name T134
Test name
Test status
Simulation time 63176608 ps
CPU time 2.39 seconds
Started Jul 09 05:04:38 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 215332 kb
Host smart-4ca6bfb2-adef-4105-ac29-08ff6fa590a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750964403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.750964403
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.910091985
Short name T1111
Test name
Test status
Simulation time 46159447 ps
CPU time 0.74 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:41 PM PDT 24
Peak memory 204128 kb
Host smart-2a01418d-13c5-4e3b-a23a-360d2f3992ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910091985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.910091985
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2129682798
Short name T1045
Test name
Test status
Simulation time 156923939 ps
CPU time 3.89 seconds
Started Jul 09 05:04:40 PM PDT 24
Finished Jul 09 05:04:45 PM PDT 24
Peak memory 215344 kb
Host smart-4e7fee1e-eda0-4b70-b46b-da6188b952c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129682798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2129682798
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.200584184
Short name T1149
Test name
Test status
Simulation time 32114819 ps
CPU time 2.02 seconds
Started Jul 09 05:04:35 PM PDT 24
Finished Jul 09 05:04:38 PM PDT 24
Peak memory 215400 kb
Host smart-2f19e956-3c1c-42cc-bf37-3e896d000f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200584184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.200584184
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1277659791
Short name T121
Test name
Test status
Simulation time 107060763 ps
CPU time 7.07 seconds
Started Jul 09 05:04:36 PM PDT 24
Finished Jul 09 05:04:44 PM PDT 24
Peak memory 215396 kb
Host smart-783da36d-255d-4c93-86c4-48c1aeb99b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277659791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1277659791
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1020965671
Short name T449
Test name
Test status
Simulation time 14121738 ps
CPU time 0.75 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:28:08 PM PDT 24
Peak memory 205824 kb
Host smart-9505ad1f-7c12-4e09-946d-24d8f84236bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020965671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
020965671
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2191033755
Short name T514
Test name
Test status
Simulation time 435972032 ps
CPU time 5.74 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:28:13 PM PDT 24
Peak memory 233744 kb
Host smart-9bafa663-3ab4-47a2-889c-2822a7df407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191033755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2191033755
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2031898562
Short name T463
Test name
Test status
Simulation time 49823622 ps
CPU time 0.81 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:17 PM PDT 24
Peak memory 207504 kb
Host smart-d075cfcd-1be6-4909-bc26-e134ddfa073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031898562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2031898562
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.652068787
Short name T417
Test name
Test status
Simulation time 16986424308 ps
CPU time 116.55 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 252548 kb
Host smart-0f8baf28-cf04-4821-99e8-841bc525114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652068787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.652068787
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3355776174
Short name T755
Test name
Test status
Simulation time 26561010702 ps
CPU time 72.34 seconds
Started Jul 09 05:28:14 PM PDT 24
Finished Jul 09 05:29:28 PM PDT 24
Peak memory 250428 kb
Host smart-904e065b-3e0e-4a05-afdc-c81679234a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355776174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3355776174
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1972666767
Short name T989
Test name
Test status
Simulation time 25860629752 ps
CPU time 162.3 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 268992 kb
Host smart-4d2e3948-cc94-476a-86a5-37aa1091d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972666767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1972666767
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3909499
Short name T494
Test name
Test status
Simulation time 105499988 ps
CPU time 2.95 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:28:11 PM PDT 24
Peak memory 225496 kb
Host smart-f92e0c81-8acf-4b36-8225-fd4d128ae63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3909499
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1677393166
Short name T680
Test name
Test status
Simulation time 5520639239 ps
CPU time 46.51 seconds
Started Jul 09 05:28:03 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 225564 kb
Host smart-e547f81c-85c8-4424-abc1-874e1ed88f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677393166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1677393166
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2018947460
Short name T833
Test name
Test status
Simulation time 9239468863 ps
CPU time 45.49 seconds
Started Jul 09 05:28:07 PM PDT 24
Finished Jul 09 05:28:54 PM PDT 24
Peak memory 233780 kb
Host smart-8bc70121-00c9-4064-9eb7-2abb333a8474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018947460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2018947460
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1238580526
Short name T141
Test name
Test status
Simulation time 22570753202 ps
CPU time 20.23 seconds
Started Jul 09 05:28:07 PM PDT 24
Finished Jul 09 05:28:29 PM PDT 24
Peak memory 241908 kb
Host smart-46b7b3af-7184-4ba3-9bd1-d98040ef5c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238580526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1238580526
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1214236777
Short name T331
Test name
Test status
Simulation time 295966326 ps
CPU time 2.22 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:28:14 PM PDT 24
Peak memory 224804 kb
Host smart-a617ece3-6470-44d9-9bde-0e265a0ed044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214236777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1214236777
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1423641688
Short name T39
Test name
Test status
Simulation time 6667607759 ps
CPU time 14.13 seconds
Started Jul 09 05:28:04 PM PDT 24
Finished Jul 09 05:28:19 PM PDT 24
Peak memory 223192 kb
Host smart-ed6c1f4c-736b-4ae9-841e-87fb501c85ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423641688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1423641688
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2550404244
Short name T61
Test name
Test status
Simulation time 1225525575 ps
CPU time 1.19 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:28:14 PM PDT 24
Peak memory 236200 kb
Host smart-d0d034b2-e7f9-421b-b5d3-40daf2c5753d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550404244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2550404244
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2433573164
Short name T156
Test name
Test status
Simulation time 22108991965 ps
CPU time 149.64 seconds
Started Jul 09 05:28:05 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 270008 kb
Host smart-e822f26a-fc44-44fa-83e9-fcf161d7a195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433573164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2433573164
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.10847859
Short name T930
Test name
Test status
Simulation time 4396386488 ps
CPU time 8.08 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:28:15 PM PDT 24
Peak memory 217472 kb
Host smart-0e72ab1a-a31d-43e0-a349-920757c1eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10847859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.10847859
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.725253416
Short name T289
Test name
Test status
Simulation time 3289485167 ps
CPU time 4.31 seconds
Started Jul 09 05:28:03 PM PDT 24
Finished Jul 09 05:28:08 PM PDT 24
Peak memory 217480 kb
Host smart-9914f319-33af-402d-84f0-0ddf8595b706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725253416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.725253416
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.896878795
Short name T593
Test name
Test status
Simulation time 513661544 ps
CPU time 2.74 seconds
Started Jul 09 05:28:05 PM PDT 24
Finished Jul 09 05:28:09 PM PDT 24
Peak memory 217316 kb
Host smart-53a1057e-ac61-46c0-b162-6b32c61728e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896878795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.896878795
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3906142506
Short name T518
Test name
Test status
Simulation time 179342972 ps
CPU time 0.82 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:28:13 PM PDT 24
Peak memory 206884 kb
Host smart-18e94497-2c04-4118-be3d-eaa989eabfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906142506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3906142506
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.428684979
Short name T698
Test name
Test status
Simulation time 931969826 ps
CPU time 4.76 seconds
Started Jul 09 05:28:09 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 233680 kb
Host smart-a9ac62b5-58d0-4fc0-8e2c-e1de6770427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428684979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.428684979
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3460053633
Short name T769
Test name
Test status
Simulation time 11238386 ps
CPU time 0.75 seconds
Started Jul 09 05:28:13 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 206188 kb
Host smart-35cf3a61-ec8f-42ce-bac7-d4adcc103fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460053633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
460053633
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.698083900
Short name T539
Test name
Test status
Simulation time 1609779822 ps
CPU time 7.51 seconds
Started Jul 09 05:28:12 PM PDT 24
Finished Jul 09 05:28:21 PM PDT 24
Peak memory 225464 kb
Host smart-73a71fbf-3c27-4b78-8e89-93f416120465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698083900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.698083900
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.924365566
Short name T574
Test name
Test status
Simulation time 61795524 ps
CPU time 0.8 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:28:13 PM PDT 24
Peak memory 207492 kb
Host smart-6c1da52b-b878-4502-a091-aa2f107235cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924365566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.924365566
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3778353485
Short name T258
Test name
Test status
Simulation time 10113742854 ps
CPU time 73.96 seconds
Started Jul 09 05:28:07 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 258468 kb
Host smart-a547d6cf-09fa-4e3d-9ead-672558f7e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778353485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3778353485
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2392244865
Short name T727
Test name
Test status
Simulation time 21779999615 ps
CPU time 107.62 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 251300 kb
Host smart-4b4ff672-e950-45aa-b3b8-31aed61eded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392244865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2392244865
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.975919285
Short name T45
Test name
Test status
Simulation time 508011818862 ps
CPU time 484.55 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:36:17 PM PDT 24
Peak memory 266780 kb
Host smart-75805baf-bddd-4431-b7bb-d2328436715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975919285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
975919285
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3603650070
Short name T412
Test name
Test status
Simulation time 7902584442 ps
CPU time 34.37 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 250448 kb
Host smart-f3c4ff87-30e1-4a41-be05-97a581ae9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603650070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3603650070
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3157118736
Short name T268
Test name
Test status
Simulation time 5274958597 ps
CPU time 57.2 seconds
Started Jul 09 05:28:06 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 250256 kb
Host smart-739735d1-1af3-4af0-ac8f-976762347152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157118736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3157118736
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3689359991
Short name T672
Test name
Test status
Simulation time 4808088685 ps
CPU time 6.43 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:17 PM PDT 24
Peak memory 225708 kb
Host smart-2438642e-1826-4642-8fe5-c599bc660817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689359991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3689359991
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.580177426
Short name T478
Test name
Test status
Simulation time 194088977 ps
CPU time 2.27 seconds
Started Jul 09 05:28:15 PM PDT 24
Finished Jul 09 05:28:18 PM PDT 24
Peak memory 225556 kb
Host smart-43f2231f-e46f-4fe3-8b48-19d548870cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580177426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.580177426
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3895580013
Short name T60
Test name
Test status
Simulation time 118718056 ps
CPU time 1.04 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:11 PM PDT 24
Peak memory 217668 kb
Host smart-78d2d139-9f13-4aee-a95f-595ef4d0ec08
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895580013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3895580013
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3485225731
Short name T472
Test name
Test status
Simulation time 352352341 ps
CPU time 2.92 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:28:15 PM PDT 24
Peak memory 233728 kb
Host smart-b3a6eefe-70fd-47fa-8696-254ce5bf4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485225731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3485225731
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4185468214
Short name T418
Test name
Test status
Simulation time 110571683 ps
CPU time 2.41 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:13 PM PDT 24
Peak memory 233456 kb
Host smart-e120ea30-fe02-46b7-9d61-040e0741881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185468214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4185468214
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2342775428
Short name T798
Test name
Test status
Simulation time 429525416 ps
CPU time 4.25 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:14 PM PDT 24
Peak memory 224132 kb
Host smart-67d9e5cf-99fb-479e-aaab-6b55027efc68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342775428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2342775428
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2987522694
Short name T728
Test name
Test status
Simulation time 7826692136 ps
CPU time 31.63 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 217672 kb
Host smart-f5bc97c5-5c84-437f-8f5f-bf540b0cbbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987522694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2987522694
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2967720981
Short name T734
Test name
Test status
Simulation time 17021361 ps
CPU time 0.72 seconds
Started Jul 09 05:28:13 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 206484 kb
Host smart-0c63949b-b01e-4575-8ce5-7e0969d58e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967720981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2967720981
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1586087759
Short name T1021
Test name
Test status
Simulation time 29236047 ps
CPU time 1.08 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:18 PM PDT 24
Peak memory 217028 kb
Host smart-d41b9ca0-62d5-4774-9d3e-700ebd57bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586087759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1586087759
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1865729885
Short name T474
Test name
Test status
Simulation time 55703099 ps
CPU time 0.9 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:11 PM PDT 24
Peak memory 206920 kb
Host smart-3eb56d2d-023c-4972-9533-59bba8f30e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865729885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1865729885
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3574915200
Short name T393
Test name
Test status
Simulation time 155094823 ps
CPU time 2.5 seconds
Started Jul 09 05:28:09 PM PDT 24
Finished Jul 09 05:28:14 PM PDT 24
Peak memory 233504 kb
Host smart-ca43a53a-1256-4f59-8ab9-d3d2ce64ad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574915200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3574915200
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3654355737
Short name T408
Test name
Test status
Simulation time 10788242 ps
CPU time 0.69 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 206368 kb
Host smart-c45f5be2-b9dc-4f4e-8f03-bc84982ca807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654355737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3654355737
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2411530734
Short name T379
Test name
Test status
Simulation time 640023733 ps
CPU time 4.45 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:45 PM PDT 24
Peak memory 233624 kb
Host smart-bfe389f6-e4a2-4041-93ca-b0f24c4d937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411530734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2411530734
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1999227255
Short name T841
Test name
Test status
Simulation time 81317346 ps
CPU time 0.8 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 207432 kb
Host smart-ba275a34-8e47-417f-8a0d-5f361785ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999227255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1999227255
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.195337324
Short name T723
Test name
Test status
Simulation time 29701665 ps
CPU time 0.76 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 216912 kb
Host smart-09e05308-ed70-4c20-909b-00f15f453dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195337324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.195337324
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1195634193
Short name T211
Test name
Test status
Simulation time 22502565046 ps
CPU time 245.7 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:32:50 PM PDT 24
Peak memory 257132 kb
Host smart-34544110-5227-4c38-a19b-b7f3a5a4b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195634193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1195634193
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2939961511
Short name T804
Test name
Test status
Simulation time 6826151169 ps
CPU time 57.53 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 250444 kb
Host smart-913091ec-ea8c-4997-a060-55b2716aa500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939961511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2939961511
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1387393156
Short name T974
Test name
Test status
Simulation time 1256520373 ps
CPU time 9.64 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 225592 kb
Host smart-cacb2931-f205-4d42-b46b-1e1ee84583ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387393156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1387393156
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2268038896
Short name T571
Test name
Test status
Simulation time 52719041986 ps
CPU time 172.79 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:31:33 PM PDT 24
Peak memory 258348 kb
Host smart-871b3c4a-b658-4e08-9987-f06eabcf5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268038896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2268038896
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3526300647
Short name T973
Test name
Test status
Simulation time 2310097038 ps
CPU time 9.7 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:54 PM PDT 24
Peak memory 233896 kb
Host smart-02c0c26c-6912-4494-9126-db6407bac5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526300647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3526300647
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1845006214
Short name T205
Test name
Test status
Simulation time 8960474266 ps
CPU time 37.57 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:29:17 PM PDT 24
Peak memory 225676 kb
Host smart-d0edbbea-cb8a-4697-b292-a4ebc8936603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845006214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1845006214
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2198599231
Short name T927
Test name
Test status
Simulation time 25027992 ps
CPU time 0.99 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 218936 kb
Host smart-7fc417eb-949b-46dd-a5d4-97bbd2e63726
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198599231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2198599231
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2876871709
Short name T937
Test name
Test status
Simulation time 660585036 ps
CPU time 8.92 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:47 PM PDT 24
Peak memory 241172 kb
Host smart-3f85f744-24d4-4628-b618-cc6d820369e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876871709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2876871709
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3858074928
Short name T42
Test name
Test status
Simulation time 3414707024 ps
CPU time 5.35 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 233852 kb
Host smart-198e1642-00db-4b6f-849b-b1e0f59d4704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858074928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3858074928
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2319153486
Short name T768
Test name
Test status
Simulation time 2624993229 ps
CPU time 8.8 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:49 PM PDT 24
Peak memory 223556 kb
Host smart-5837e26b-69e4-4ea9-88c0-4288aa21ca76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2319153486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2319153486
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.448095603
Short name T900
Test name
Test status
Simulation time 969828960 ps
CPU time 3.65 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 217332 kb
Host smart-8f1dc4ce-dc08-486b-aaed-44e9dcb26736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448095603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.448095603
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3994961956
Short name T343
Test name
Test status
Simulation time 268097792 ps
CPU time 2.45 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 217252 kb
Host smart-484fbf42-e8bd-492e-ab9a-872149c8f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994961956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3994961956
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1167033699
Short name T977
Test name
Test status
Simulation time 214487892 ps
CPU time 3.31 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 217316 kb
Host smart-a91c9d7a-a1de-41f9-91ab-288e86f9982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167033699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1167033699
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3998717392
Short name T88
Test name
Test status
Simulation time 139417209 ps
CPU time 0.78 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 206964 kb
Host smart-fd711ba1-6813-4af5-9b24-ece2a9ca557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998717392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3998717392
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1986095539
Short name T187
Test name
Test status
Simulation time 1784362549 ps
CPU time 8.04 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 241840 kb
Host smart-726400a2-2cd5-4de2-8c55-d4da3200f12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986095539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1986095539
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.76047936
Short name T296
Test name
Test status
Simulation time 10856789 ps
CPU time 0.68 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 206272 kb
Host smart-6f32cbc2-5823-4de2-9ab3-099cfe874a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76047936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.76047936
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3976261267
Short name T682
Test name
Test status
Simulation time 195379088 ps
CPU time 4.59 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:54 PM PDT 24
Peak memory 233752 kb
Host smart-2c9b1e6d-8bd6-407f-9ee5-19918491b9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976261267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3976261267
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1736606673
Short name T443
Test name
Test status
Simulation time 17211946 ps
CPU time 0.76 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 207464 kb
Host smart-0b9f58c2-1d2b-418a-9db0-e80b389d99b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736606673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1736606673
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3156864355
Short name T5
Test name
Test status
Simulation time 196337355614 ps
CPU time 146.51 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:31:11 PM PDT 24
Peak memory 242092 kb
Host smart-dcfc46eb-691c-4a0b-88e7-2e2f57bb1437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156864355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3156864355
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4248683938
Short name T942
Test name
Test status
Simulation time 1691091266 ps
CPU time 37.1 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 250304 kb
Host smart-c2891e0e-9468-4e4c-95e6-10f2ad3a22e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248683938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4248683938
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2781123713
Short name T586
Test name
Test status
Simulation time 26828265043 ps
CPU time 289.23 seconds
Started Jul 09 05:28:52 PM PDT 24
Finished Jul 09 05:33:42 PM PDT 24
Peak memory 251440 kb
Host smart-75fd0b43-6bfd-48ac-8468-7d6a1cd54fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781123713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2781123713
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1084407926
Short name T902
Test name
Test status
Simulation time 1034085367 ps
CPU time 13.38 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 233616 kb
Host smart-765efee3-beb2-4159-b80c-de2f65816aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084407926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1084407926
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3249391306
Short name T935
Test name
Test status
Simulation time 29502672 ps
CPU time 0.75 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 216916 kb
Host smart-af3ed6d5-4e4b-41f3-a395-910fec4e6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249391306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3249391306
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1840136191
Short name T361
Test name
Test status
Simulation time 33207922 ps
CPU time 2.17 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 233552 kb
Host smart-858f438d-8a81-401c-bb7f-8cb1e53204f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840136191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1840136191
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2350066393
Short name T209
Test name
Test status
Simulation time 9158845894 ps
CPU time 46.47 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 233832 kb
Host smart-ec35c382-5a47-452f-87b3-f81190065c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350066393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2350066393
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4293297215
Short name T541
Test name
Test status
Simulation time 42930850 ps
CPU time 1.02 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 218832 kb
Host smart-31fc5d90-a992-46c7-8a72-90479d723000
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293297215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4293297215
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2052717510
Short name T454
Test name
Test status
Simulation time 284764855 ps
CPU time 2.24 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 225448 kb
Host smart-55e7c06c-f261-4b9c-8057-5dc035056a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052717510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2052717510
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2306258837
Short name T311
Test name
Test status
Simulation time 126897901 ps
CPU time 2.23 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 233816 kb
Host smart-c60c2e6a-7dd0-4b0c-9ee5-d089f49c2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306258837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2306258837
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4209384144
Short name T157
Test name
Test status
Simulation time 212197186 ps
CPU time 3.93 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:28:47 PM PDT 24
Peak memory 221420 kb
Host smart-d05d6ded-cec1-4777-a898-9652f511f8d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209384144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4209384144
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4121762133
Short name T359
Test name
Test status
Simulation time 46345897 ps
CPU time 0.92 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:49 PM PDT 24
Peak memory 206608 kb
Host smart-ebc290d5-e6d5-4fb6-aea7-c4a5d3b4d28a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121762133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4121762133
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.865184491
Short name T636
Test name
Test status
Simulation time 2621606104 ps
CPU time 11.52 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:11 PM PDT 24
Peak memory 217784 kb
Host smart-3857931b-7631-4e7b-b2f6-7b2a2abe8868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865184491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.865184491
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2669512745
Short name T410
Test name
Test status
Simulation time 560025296 ps
CPU time 3.85 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 217312 kb
Host smart-eadd734e-a6a9-443d-bb1b-b3d51f0be724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669512745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2669512745
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3077542856
Short name T370
Test name
Test status
Simulation time 29371395 ps
CPU time 1.83 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 217276 kb
Host smart-ec054897-f9ca-42ca-8927-70b16462b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077542856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3077542856
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2998742259
Short name T470
Test name
Test status
Simulation time 164250732 ps
CPU time 0.91 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:49 PM PDT 24
Peak memory 207880 kb
Host smart-b5731127-4333-448c-9c7e-3f9b48cdc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998742259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2998742259
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1930112120
Short name T519
Test name
Test status
Simulation time 13113707959 ps
CPU time 12.13 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 233900 kb
Host smart-cf23c209-c60c-492b-b8c6-b03c1bdce79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930112120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1930112120
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3301518487
Short name T344
Test name
Test status
Simulation time 17376808 ps
CPU time 0.71 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 206088 kb
Host smart-ab806782-303b-4d79-a2bb-78ecfdec9428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301518487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3301518487
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3824836273
Short name T363
Test name
Test status
Simulation time 409221444 ps
CPU time 3.33 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 233504 kb
Host smart-9660177b-9d6a-4901-ba54-ece620e3c5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824836273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3824836273
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3638150657
Short name T616
Test name
Test status
Simulation time 52975014 ps
CPU time 0.79 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 207844 kb
Host smart-ea5aa2de-d252-4179-b978-cece69f221e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638150657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3638150657
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3694795922
Short name T674
Test name
Test status
Simulation time 11733454358 ps
CPU time 121.22 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:31:01 PM PDT 24
Peak memory 258112 kb
Host smart-27f0b316-1367-4531-9ba5-98d73de0ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694795922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3694795922
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3758147317
Short name T939
Test name
Test status
Simulation time 108968034 ps
CPU time 0.79 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 218200 kb
Host smart-ef210aee-6891-4c84-9c7e-8725b318567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758147317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3758147317
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3029412950
Short name T497
Test name
Test status
Simulation time 391436004 ps
CPU time 8.45 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 225584 kb
Host smart-f3ba292f-8027-4047-8c62-aa21dbee3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029412950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3029412950
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.788673211
Short name T177
Test name
Test status
Simulation time 426946440822 ps
CPU time 238.77 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:32:59 PM PDT 24
Peak memory 250528 kb
Host smart-cb1a3a92-d1a0-4d5a-b5d5-c610e5790e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788673211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.788673211
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1065124493
Short name T648
Test name
Test status
Simulation time 231875919 ps
CPU time 2.79 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 233816 kb
Host smart-e03b7078-6d4c-49d3-8d55-80f26f4b68ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065124493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1065124493
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3051631579
Short name T466
Test name
Test status
Simulation time 3097366647 ps
CPU time 4.71 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 233880 kb
Host smart-b0d302f2-cd0b-4ce8-b78f-c5e95c0de21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051631579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3051631579
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1063185497
Short name T34
Test name
Test status
Simulation time 97274489 ps
CPU time 1.02 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 218752 kb
Host smart-a9e46774-614b-4a67-b37d-ca047c2b0d83
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063185497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1063185497
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2537786694
Short name T706
Test name
Test status
Simulation time 838674980 ps
CPU time 3.54 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 225496 kb
Host smart-d236fd23-2de6-4494-8fd2-ed6f312cfecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537786694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2537786694
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1025529042
Short name T944
Test name
Test status
Simulation time 28111875341 ps
CPU time 19.82 seconds
Started Jul 09 05:28:58 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 233908 kb
Host smart-44d080c9-0ac1-4cb3-8a34-3194c0020d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025529042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1025529042
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3670839125
Short name T430
Test name
Test status
Simulation time 3850058557 ps
CPU time 23.18 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 223212 kb
Host smart-89b416e0-20f4-44e4-b8c6-841313f72eb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3670839125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3670839125
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.762990387
Short name T777
Test name
Test status
Simulation time 160784096004 ps
CPU time 339.56 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:34:45 PM PDT 24
Peak memory 263236 kb
Host smart-2fcb5c05-b530-4b15-979c-80baee10c812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762990387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.762990387
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1515538417
Short name T280
Test name
Test status
Simulation time 19046565886 ps
CPU time 52.54 seconds
Started Jul 09 05:28:54 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 217468 kb
Host smart-1c7ecc6f-9c08-4cc5-ac4a-d4e611057768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515538417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1515538417
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3375620282
Short name T781
Test name
Test status
Simulation time 12879225286 ps
CPU time 5.47 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 217336 kb
Host smart-92b65726-f2b9-4f04-b146-20ed4413af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375620282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3375620282
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4098392349
Short name T837
Test name
Test status
Simulation time 243652010 ps
CPU time 5.87 seconds
Started Jul 09 05:28:54 PM PDT 24
Finished Jul 09 05:29:01 PM PDT 24
Peak memory 217324 kb
Host smart-fd72faa1-6260-454e-89d3-e5400f5726c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098392349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4098392349
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2638950194
Short name T585
Test name
Test status
Simulation time 35051371 ps
CPU time 0.78 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:47 PM PDT 24
Peak memory 206840 kb
Host smart-58f17772-9928-4971-a602-06121c3c1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638950194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2638950194
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1073914530
Short name T407
Test name
Test status
Simulation time 199261004 ps
CPU time 2.2 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:54 PM PDT 24
Peak memory 224992 kb
Host smart-f69aeb5c-3242-4e55-8927-b1f839753ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073914530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1073914530
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1976982211
Short name T432
Test name
Test status
Simulation time 16837564 ps
CPU time 0.72 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 205780 kb
Host smart-2c0524c2-468a-4b1d-9ac2-0ca54348122d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976982211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1976982211
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3853936905
Short name T225
Test name
Test status
Simulation time 234682982 ps
CPU time 3.92 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 233756 kb
Host smart-ad2df0a4-686e-427d-86ea-86b2fb1bbd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853936905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3853936905
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2430715610
Short name T740
Test name
Test status
Simulation time 21733041 ps
CPU time 0.78 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:49 PM PDT 24
Peak memory 207524 kb
Host smart-d3c6cc65-1eda-4548-b897-5e52f84f38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430715610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2430715610
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1183996116
Short name T341
Test name
Test status
Simulation time 54286711 ps
CPU time 0.76 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:47 PM PDT 24
Peak memory 216828 kb
Host smart-05346592-ecbc-49ea-af13-b74d4ab6a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183996116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1183996116
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2108375593
Short name T125
Test name
Test status
Simulation time 17283943051 ps
CPU time 27.31 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 239088 kb
Host smart-a9821364-5a15-4adf-9f68-b88e45e4d058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108375593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2108375593
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3477461951
Short name T665
Test name
Test status
Simulation time 2423088963 ps
CPU time 39.53 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 239624 kb
Host smart-0aff6c95-cd89-4711-9cb6-4a29c151b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477461951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3477461951
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2643954441
Short name T531
Test name
Test status
Simulation time 6372704545 ps
CPU time 5.3 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 238616 kb
Host smart-2b652912-67e0-472a-8f11-167f538549f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643954441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2643954441
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4064830304
Short name T711
Test name
Test status
Simulation time 2719569224 ps
CPU time 57.94 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 266036 kb
Host smart-3beab3ad-df9b-4bd7-84d6-333d4e248ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064830304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4064830304
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1687216448
Short name T1002
Test name
Test status
Simulation time 1016306684 ps
CPU time 5.35 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:56 PM PDT 24
Peak memory 225552 kb
Host smart-7e71fae1-0762-43e3-9fc8-5e8cf9c82772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687216448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1687216448
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2223149228
Short name T876
Test name
Test status
Simulation time 387292957 ps
CPU time 12.89 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:29:01 PM PDT 24
Peak memory 241472 kb
Host smart-2c8b7cb0-2aaf-4000-bc3a-929d85fb1973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223149228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2223149228
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3294997160
Short name T720
Test name
Test status
Simulation time 130345648 ps
CPU time 1.01 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 218848 kb
Host smart-91faef0d-daf6-49a5-9f9b-d293c3b22357
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294997160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3294997160
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1118791182
Short name T912
Test name
Test status
Simulation time 3360205636 ps
CPU time 9.54 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 241620 kb
Host smart-be12e6f8-e411-4a04-baf0-0f0a8a197664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118791182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1118791182
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.961722604
Short name T204
Test name
Test status
Simulation time 225385112 ps
CPU time 4.25 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 225520 kb
Host smart-5af62d86-13cf-475c-8783-25944bcc5762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961722604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.961722604
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3513332016
Short name T901
Test name
Test status
Simulation time 1542002463 ps
CPU time 4.34 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 223684 kb
Host smart-29984b46-357b-4e89-95df-b12a850286f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3513332016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3513332016
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3551824653
Short name T473
Test name
Test status
Simulation time 1691924057 ps
CPU time 9.04 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:28:54 PM PDT 24
Peak memory 217308 kb
Host smart-93642730-72c0-46d0-a9cf-8551038bd0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551824653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3551824653
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3147372542
Short name T314
Test name
Test status
Simulation time 495132062 ps
CPU time 3.11 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 217352 kb
Host smart-1159aabf-8b41-43e3-a548-1051276d846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147372542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3147372542
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2507954320
Short name T434
Test name
Test status
Simulation time 627849546 ps
CPU time 3.43 seconds
Started Jul 09 05:28:54 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 217320 kb
Host smart-da17f8ad-06fb-49e1-836e-51507be6cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507954320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2507954320
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.346953550
Short name T710
Test name
Test status
Simulation time 45665423 ps
CPU time 0.87 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 206988 kb
Host smart-2d09c6b3-6bcf-4ef1-be75-41ac55d6adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346953550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.346953550
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2508401473
Short name T523
Test name
Test status
Simulation time 41072547 ps
CPU time 2.67 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 225176 kb
Host smart-ad9a5b1a-7868-40ea-a4ce-270d2faf04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508401473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2508401473
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2200602337
Short name T373
Test name
Test status
Simulation time 12123961 ps
CPU time 0.73 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 206308 kb
Host smart-25ceaf57-c588-4642-99b0-628db9bcf0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200602337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2200602337
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.304691450
Short name T91
Test name
Test status
Simulation time 10036056606 ps
CPU time 12.96 seconds
Started Jul 09 05:28:52 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 225640 kb
Host smart-f7b2be4f-b23e-4ffe-9e6d-4f22a1ad6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304691450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.304691450
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.272118185
Short name T346
Test name
Test status
Simulation time 13306930 ps
CPU time 0.81 seconds
Started Jul 09 05:28:51 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 207496 kb
Host smart-a770c84c-4413-439d-9af4-d7e1a04ccd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272118185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.272118185
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2728647497
Short name T763
Test name
Test status
Simulation time 21834976453 ps
CPU time 115.82 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 251084 kb
Host smart-080facbc-7d70-46ce-a638-03fdc0ac44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728647497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2728647497
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.949267109
Short name T575
Test name
Test status
Simulation time 220153377082 ps
CPU time 404.26 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:35:52 PM PDT 24
Peak memory 253756 kb
Host smart-f29f9e94-e163-4e96-831d-435c2d345fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949267109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.949267109
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3355205183
Short name T259
Test name
Test status
Simulation time 1797461051 ps
CPU time 23.38 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 238756 kb
Host smart-b245ae1e-7021-411e-b894-db4206268b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355205183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3355205183
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.359076881
Short name T340
Test name
Test status
Simulation time 83288767 ps
CPU time 2.46 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 225528 kb
Host smart-9ff479ee-0e27-4cd6-abab-fa5c69b1d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359076881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.359076881
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3222742759
Short name T203
Test name
Test status
Simulation time 10286012564 ps
CPU time 78.91 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 250252 kb
Host smart-598cd3e3-945d-4b74-ae33-195be08f7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222742759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3222742759
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1864357298
Short name T226
Test name
Test status
Simulation time 2516521192 ps
CPU time 4.27 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 225632 kb
Host smart-6af81731-71ea-45ba-ab2a-9740d8ca80a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864357298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1864357298
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2024031039
Short name T790
Test name
Test status
Simulation time 5097729977 ps
CPU time 58.7 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 235360 kb
Host smart-253af503-716b-4b5b-b8bd-7e7affa3f1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024031039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2024031039
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2839880401
Short name T765
Test name
Test status
Simulation time 26400291 ps
CPU time 1.07 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 217572 kb
Host smart-4760fb77-976e-46ff-82cb-7c0d37664b01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839880401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2839880401
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1974102016
Short name T549
Test name
Test status
Simulation time 22792725525 ps
CPU time 22.32 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:29:11 PM PDT 24
Peak memory 233812 kb
Host smart-67470872-593d-4317-96da-930e80a4b04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974102016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1974102016
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3017416599
Short name T382
Test name
Test status
Simulation time 22776666327 ps
CPU time 17.89 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 233824 kb
Host smart-f3443bf0-4099-4b14-b12d-83393893b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017416599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3017416599
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1586521585
Short name T683
Test name
Test status
Simulation time 709674678 ps
CPU time 9.74 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:01 PM PDT 24
Peak memory 223020 kb
Host smart-2af81652-f50a-4a14-8ae1-4eb142ac68f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586521585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1586521585
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4027551620
Short name T251
Test name
Test status
Simulation time 68451548213 ps
CPU time 188.38 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:31:59 PM PDT 24
Peak memory 252716 kb
Host smart-af87cada-6cab-41eb-9052-6a7225320da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027551620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4027551620
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.88897535
Short name T534
Test name
Test status
Simulation time 1024407711 ps
CPU time 6.42 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:57 PM PDT 24
Peak memory 217560 kb
Host smart-e9733ec4-74d7-4cef-8778-6a9d526af687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88897535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.88897535
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.43110871
Short name T969
Test name
Test status
Simulation time 3843150195 ps
CPU time 4.17 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 217484 kb
Host smart-9a0ac323-1cb6-4fc9-a4e6-cb0b9110b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43110871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.43110871
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3502950937
Short name T606
Test name
Test status
Simulation time 490028688 ps
CPU time 2.41 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:00 PM PDT 24
Peak memory 217332 kb
Host smart-2ef9ec77-b655-4ef3-91f1-e6799221db23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502950937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3502950937
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.541151130
Short name T918
Test name
Test status
Simulation time 1279055577 ps
CPU time 0.98 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 207352 kb
Host smart-1e02e6f0-0b6a-4612-bde6-afb39c497dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541151130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.541151130
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2498955670
Short name T148
Test name
Test status
Simulation time 16798480834 ps
CPU time 14.95 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 233852 kb
Host smart-162d2699-4af9-4f75-93e4-994f29e5053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498955670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2498955670
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3224894860
Short name T542
Test name
Test status
Simulation time 30055994 ps
CPU time 0.71 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 206744 kb
Host smart-3429fb8d-c6c6-4e8d-a1db-818aa22684cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224894860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3224894860
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.199115211
Short name T162
Test name
Test status
Simulation time 771121058 ps
CPU time 8.82 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:29:01 PM PDT 24
Peak memory 225552 kb
Host smart-e27fc801-ab67-422d-864f-8483739f0bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199115211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.199115211
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1439644164
Short name T536
Test name
Test status
Simulation time 15505312 ps
CPU time 0.75 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:28:58 PM PDT 24
Peak memory 206404 kb
Host smart-41c0847d-b152-4183-9244-00553cc1b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439644164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1439644164
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3637502033
Short name T619
Test name
Test status
Simulation time 76682358686 ps
CPU time 200.29 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:32:12 PM PDT 24
Peak memory 266588 kb
Host smart-81dd71ca-812c-4932-bf66-b3668eaf7533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637502033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3637502033
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.307523642
Short name T56
Test name
Test status
Simulation time 42888800338 ps
CPU time 377.92 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:35:18 PM PDT 24
Peak memory 258576 kb
Host smart-1d4841aa-ddd3-418e-89d1-99ee0beecbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307523642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.307523642
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3347847753
Short name T605
Test name
Test status
Simulation time 29762365048 ps
CPU time 131.18 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 258580 kb
Host smart-3aff2933-9cd5-4489-8b5f-9314e6213db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347847753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3347847753
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2462161774
Short name T667
Test name
Test status
Simulation time 1628731318 ps
CPU time 13.04 seconds
Started Jul 09 05:28:51 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 241992 kb
Host smart-fcb7a470-2e8d-4bfc-a3aa-1c0e518821ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462161774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2462161774
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2267851000
Short name T874
Test name
Test status
Simulation time 81218717589 ps
CPU time 155.25 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:31:31 PM PDT 24
Peak memory 254128 kb
Host smart-efe5dd0f-338a-410a-9972-f0dd34210f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267851000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2267851000
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1635238270
Short name T827
Test name
Test status
Simulation time 363025255 ps
CPU time 6.61 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 225440 kb
Host smart-b5742f1d-3d6d-42f7-a8ce-da87de6ee90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635238270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1635238270
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.102075391
Short name T996
Test name
Test status
Simulation time 90854050 ps
CPU time 2.06 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 225188 kb
Host smart-97225402-e7d3-44d9-920b-f5b99f901148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102075391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.102075391
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3784760268
Short name T451
Test name
Test status
Simulation time 125436549 ps
CPU time 1.06 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 217652 kb
Host smart-e96837b9-509d-4787-8106-7584ac4958e8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784760268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3784760268
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2324991238
Short name T59
Test name
Test status
Simulation time 2421222477 ps
CPU time 6.58 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 233840 kb
Host smart-4dd3c744-a812-49b2-8df8-0663eb5e2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324991238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2324991238
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1308548258
Short name T966
Test name
Test status
Simulation time 157712293 ps
CPU time 4.89 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 233632 kb
Host smart-2f3a8e83-6178-429d-ad86-c705972689df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308548258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1308548258
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1756548650
Short name T899
Test name
Test status
Simulation time 836399700 ps
CPU time 7.65 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 223016 kb
Host smart-232145d9-cc0c-4d6a-9bd9-bc0e6a7435d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1756548650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1756548650
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2346199210
Short name T50
Test name
Test status
Simulation time 12604799681 ps
CPU time 194.2 seconds
Started Jul 09 05:28:51 PM PDT 24
Finished Jul 09 05:32:07 PM PDT 24
Peak memory 274176 kb
Host smart-f58c6599-b7f5-452d-9a72-8a6c94be53df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346199210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2346199210
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.47111776
Short name T86
Test name
Test status
Simulation time 2156778663 ps
CPU time 7.78 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 217468 kb
Host smart-a71e63c7-d133-4c7d-a93e-03a25bff0fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47111776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.47111776
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3558364052
Short name T334
Test name
Test status
Simulation time 4263774079 ps
CPU time 11.85 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 217480 kb
Host smart-66ff4585-818e-480c-9cb9-dd4f4dee6222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558364052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3558364052
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.638234082
Short name T307
Test name
Test status
Simulation time 89904945 ps
CPU time 1.45 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 217292 kb
Host smart-dc766165-8da5-43c2-b8b3-c63676ce8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638234082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.638234082
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2208439506
Short name T14
Test name
Test status
Simulation time 20374450 ps
CPU time 0.75 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 206928 kb
Host smart-964d874a-0fbb-41a0-93bd-b86e7f335e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208439506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2208439506
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3241292880
Short name T976
Test name
Test status
Simulation time 10435801227 ps
CPU time 11.91 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 225624 kb
Host smart-456aaaf8-6933-43f7-ae27-ef63a183432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241292880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3241292880
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.561467762
Short name T452
Test name
Test status
Simulation time 12895345 ps
CPU time 0.69 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 206644 kb
Host smart-a5f701bf-0d56-444e-8f37-6d9ddec16bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561467762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.561467762
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3882557248
Short name T732
Test name
Test status
Simulation time 33947851 ps
CPU time 2.32 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 233612 kb
Host smart-6fc72fed-8083-4794-b90e-01ffcc461dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882557248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3882557248
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4268407467
Short name T488
Test name
Test status
Simulation time 27596351 ps
CPU time 0.78 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 206732 kb
Host smart-ee6de498-aadb-46c5-a108-5766eefaca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268407467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4268407467
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3846488205
Short name T638
Test name
Test status
Simulation time 10242683582 ps
CPU time 84.61 seconds
Started Jul 09 05:28:51 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 253344 kb
Host smart-058c7d57-0113-497d-9848-c32774629381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846488205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3846488205
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3272338335
Short name T613
Test name
Test status
Simulation time 6402802668 ps
CPU time 41.16 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 256836 kb
Host smart-96782b7e-b72d-41ce-a1ea-9311d6ecea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272338335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3272338335
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2823431394
Short name T562
Test name
Test status
Simulation time 10525365646 ps
CPU time 20.91 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:11 PM PDT 24
Peak memory 221012 kb
Host smart-8d008745-a6c2-4b70-aadf-5f934a6fa234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823431394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2823431394
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.111313719
Short name T496
Test name
Test status
Simulation time 177744780 ps
CPU time 2.68 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:00 PM PDT 24
Peak memory 233784 kb
Host smart-899332db-73cf-4ebd-9726-ac219c122ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111313719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.111313719
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3539226303
Short name T402
Test name
Test status
Simulation time 9347523014 ps
CPU time 17.49 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 242076 kb
Host smart-db200c72-52fc-4493-b16b-620143f92202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539226303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3539226303
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2242910866
Short name T480
Test name
Test status
Simulation time 10482023734 ps
CPU time 9.81 seconds
Started Jul 09 05:28:58 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 225656 kb
Host smart-d3960d90-bc11-4f57-b1af-480377ec7f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242910866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2242910866
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.751025700
Short name T217
Test name
Test status
Simulation time 17491523485 ps
CPU time 38.59 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 225664 kb
Host smart-e54d42f0-e5f1-43b6-8b5f-37b8bc43143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751025700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.751025700
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2328127805
Short name T33
Test name
Test status
Simulation time 115862356 ps
CPU time 1.1 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 217652 kb
Host smart-9af78b4e-2998-4cb2-a94a-04880d7e8c7e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328127805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2328127805
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3584967587
Short name T649
Test name
Test status
Simulation time 19915286722 ps
CPU time 16.42 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 225628 kb
Host smart-34f2bbb4-b65a-4b4e-ba0a-052bd1efa94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584967587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3584967587
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1833947785
Short name T813
Test name
Test status
Simulation time 6707941823 ps
CPU time 9.11 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 236860 kb
Host smart-8f4f8ac2-eb85-43d7-90b3-186ef8a761bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833947785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1833947785
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2515100673
Short name T867
Test name
Test status
Simulation time 109513158 ps
CPU time 3.29 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 220392 kb
Host smart-56afb260-837a-4175-bb45-91c2ce479af2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2515100673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2515100673
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3518555667
Short name T167
Test name
Test status
Simulation time 252813430 ps
CPU time 1.03 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 208472 kb
Host smart-d8687959-a4ca-4f1a-b408-faf4b35798a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518555667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3518555667
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3858123571
Short name T597
Test name
Test status
Simulation time 8530533451 ps
CPU time 26.1 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 217844 kb
Host smart-056df784-f1bb-44e2-9537-cac37931086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858123571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3858123571
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.182212680
Short name T788
Test name
Test status
Simulation time 2630474830 ps
CPU time 8.11 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:08 PM PDT 24
Peak memory 217380 kb
Host smart-ae77db77-b75b-4ba6-a374-91ba479e40ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182212680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.182212680
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1411109870
Short name T910
Test name
Test status
Simulation time 124278523 ps
CPU time 1.95 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:29:00 PM PDT 24
Peak memory 217364 kb
Host smart-a5cf1951-495c-4d34-83ab-72589c2889c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411109870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1411109870
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2643109050
Short name T297
Test name
Test status
Simulation time 41460370 ps
CPU time 0.82 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 206984 kb
Host smart-d215495b-a486-43f0-9f54-344659597121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643109050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2643109050
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1926358796
Short name T486
Test name
Test status
Simulation time 1874733015 ps
CPU time 10.2 seconds
Started Jul 09 05:28:52 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 241884 kb
Host smart-1bd35b96-3212-4658-a3c2-85bfb0b22ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926358796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1926358796
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.720579192
Short name T1020
Test name
Test status
Simulation time 56674653 ps
CPU time 0.7 seconds
Started Jul 09 05:28:56 PM PDT 24
Finished Jul 09 05:28:58 PM PDT 24
Peak memory 205676 kb
Host smart-a5029768-56db-4bd4-9d83-654117c7fdfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720579192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.720579192
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2630762922
Short name T693
Test name
Test status
Simulation time 325332427 ps
CPU time 3.1 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 233724 kb
Host smart-2c246c79-356b-44d2-a397-eb4ec0add9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630762922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2630762922
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.739067701
Short name T730
Test name
Test status
Simulation time 18688915 ps
CPU time 0.79 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 207484 kb
Host smart-ab10c431-2be1-4b7a-8da6-434460a11675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739067701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.739067701
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3024029835
Short name T147
Test name
Test status
Simulation time 13046304983 ps
CPU time 69.13 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 255444 kb
Host smart-758dc5f8-c510-4ed4-abc8-2e66883c71c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024029835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3024029835
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4286654651
Short name T12
Test name
Test status
Simulation time 64018557 ps
CPU time 3.51 seconds
Started Jul 09 05:28:50 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 233624 kb
Host smart-091c8876-37b8-4a86-bd81-b77760c109a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286654651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4286654651
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.222124307
Short name T896
Test name
Test status
Simulation time 43124630181 ps
CPU time 139.47 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:31:26 PM PDT 24
Peak memory 251148 kb
Host smart-1aa76c83-0a67-4a5a-8258-2b13678a85b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222124307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.222124307
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2832517361
Short name T447
Test name
Test status
Simulation time 698922462 ps
CPU time 6.43 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 233760 kb
Host smart-cdb3229a-4a13-4119-b541-e7b4297234ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832517361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2832517361
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3738157000
Short name T642
Test name
Test status
Simulation time 103255278 ps
CPU time 2.08 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 219632 kb
Host smart-fc7ca301-cd3a-4ea9-876b-de3060232b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738157000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3738157000
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3481362118
Short name T817
Test name
Test status
Simulation time 43203465 ps
CPU time 1.04 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:11 PM PDT 24
Peak memory 217680 kb
Host smart-dcf2c65f-4579-4761-92db-5342fe2fbf6a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481362118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3481362118
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2612448843
Short name T909
Test name
Test status
Simulation time 4469245922 ps
CPU time 13.65 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 233556 kb
Host smart-4eb3325c-3c70-4ca9-9997-8b6ad79d233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612448843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2612448843
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3136157917
Short name T714
Test name
Test status
Simulation time 5225398628 ps
CPU time 13.47 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 225608 kb
Host smart-3f92c057-4503-4825-8f70-6198a2ee5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136157917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3136157917
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2111456201
Short name T816
Test name
Test status
Simulation time 429614718 ps
CPU time 4.14 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 220972 kb
Host smart-8c5c22e6-c59a-4023-9042-15faa24b6ca7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2111456201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2111456201
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2048385152
Short name T823
Test name
Test status
Simulation time 261195712 ps
CPU time 0.97 seconds
Started Jul 09 05:28:56 PM PDT 24
Finished Jul 09 05:28:58 PM PDT 24
Peak memory 207608 kb
Host smart-17ae7726-b2b1-4db2-8bc5-f169656d0abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048385152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2048385152
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3905133553
Short name T483
Test name
Test status
Simulation time 1316215886 ps
CPU time 21.97 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 217340 kb
Host smart-6994a5e2-989a-419a-aea5-9af472a95a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905133553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3905133553
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.196958970
Short name T811
Test name
Test status
Simulation time 215273207 ps
CPU time 1.58 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 208800 kb
Host smart-627c3de6-da80-45a2-8fe6-e0c236337ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196958970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.196958970
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3838428238
Short name T633
Test name
Test status
Simulation time 155950544 ps
CPU time 1.3 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 217176 kb
Host smart-94024955-c117-48f6-8b41-afcf3598831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838428238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3838428238
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.853243065
Short name T994
Test name
Test status
Simulation time 28211822 ps
CPU time 0.77 seconds
Started Jul 09 05:28:51 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 206960 kb
Host smart-ebcc1192-298d-473f-844b-273a66c05ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853243065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.853243065
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4140758000
Short name T776
Test name
Test status
Simulation time 119626458 ps
CPU time 2.57 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 225492 kb
Host smart-8571fd32-2076-4bf9-92f5-f7561660efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140758000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4140758000
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.208490636
Short name T725
Test name
Test status
Simulation time 30296454 ps
CPU time 0.73 seconds
Started Jul 09 05:28:58 PM PDT 24
Finished Jul 09 05:28:59 PM PDT 24
Peak memory 206640 kb
Host smart-55129f98-50dc-44a7-9dcf-1180dc452bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208490636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.208490636
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.914027026
Short name T62
Test name
Test status
Simulation time 354737859 ps
CPU time 3.35 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:08 PM PDT 24
Peak memory 225428 kb
Host smart-f4f3f76b-6deb-4cfc-8caf-e84b9715d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914027026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.914027026
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.502073995
Short name T592
Test name
Test status
Simulation time 18796712 ps
CPU time 0.79 seconds
Started Jul 09 05:28:49 PM PDT 24
Finished Jul 09 05:28:52 PM PDT 24
Peak memory 207484 kb
Host smart-f66c6651-db92-4ac0-860e-26120f40ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502073995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.502073995
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.952270470
Short name T886
Test name
Test status
Simulation time 1722863350 ps
CPU time 22.96 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 251188 kb
Host smart-b5285318-292b-4cc7-baf5-8a388605069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952270470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.952270470
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2712063696
Short name T51
Test name
Test status
Simulation time 110128368140 ps
CPU time 233.15 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:32:57 PM PDT 24
Peak memory 251976 kb
Host smart-a59d6466-5267-4543-b353-f54c340b1f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712063696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2712063696
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.726355488
Short name T398
Test name
Test status
Simulation time 77064065377 ps
CPU time 206.95 seconds
Started Jul 09 05:28:57 PM PDT 24
Finished Jul 09 05:32:25 PM PDT 24
Peak memory 257804 kb
Host smart-fb8b2f4a-8d49-4ecd-ba46-e066021b3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726355488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.726355488
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3151911721
Short name T235
Test name
Test status
Simulation time 12712900687 ps
CPU time 92.28 seconds
Started Jul 09 05:28:54 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 237172 kb
Host smart-9ab5ed54-f9c7-4487-8ce8-3653ee59cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151911721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3151911721
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2175856473
Short name T563
Test name
Test status
Simulation time 2742558551 ps
CPU time 4.7 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 225696 kb
Host smart-486ee7f1-9282-4aa9-8c22-1a9967231a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175856473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2175856473
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3941737886
Short name T390
Test name
Test status
Simulation time 557963596 ps
CPU time 3.17 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:14 PM PDT 24
Peak memory 233784 kb
Host smart-3e4909fc-5d82-45e2-a6a6-06ecd349f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941737886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3941737886
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3436866009
Short name T468
Test name
Test status
Simulation time 366094615 ps
CPU time 1.18 seconds
Started Jul 09 05:29:00 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 217680 kb
Host smart-dd5c3200-dbd7-4f49-9420-ea2228067327
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436866009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3436866009
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3341021962
Short name T240
Test name
Test status
Simulation time 2432787996 ps
CPU time 7.9 seconds
Started Jul 09 05:28:59 PM PDT 24
Finished Jul 09 05:29:07 PM PDT 24
Peak memory 225592 kb
Host smart-611097b5-4e53-4a20-a4e5-8831dc466989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341021962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3341021962
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1597528988
Short name T7
Test name
Test status
Simulation time 2186510146 ps
CPU time 9.12 seconds
Started Jul 09 05:28:56 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 239908 kb
Host smart-001b8ac7-1009-474f-94f2-f162dba330d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597528988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1597528988
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.761167698
Short name T696
Test name
Test status
Simulation time 927167186 ps
CPU time 4.42 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:16 PM PDT 24
Peak memory 223580 kb
Host smart-7c22d0c0-41c4-4fce-a1ac-c72e4cd6a638
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=761167698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.761167698
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3227424716
Short name T603
Test name
Test status
Simulation time 3570382914 ps
CPU time 7.16 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 217512 kb
Host smart-81526cf8-7482-4948-8d7e-4ed96a1fac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227424716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3227424716
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1061271466
Short name T759
Test name
Test status
Simulation time 23324594851 ps
CPU time 16.42 seconds
Started Jul 09 05:28:55 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 217392 kb
Host smart-6f684960-700f-42a4-b561-1a169fcd6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061271466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1061271466
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3222980222
Short name T24
Test name
Test status
Simulation time 21263107 ps
CPU time 0.95 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 208936 kb
Host smart-83d9f3a0-1aec-4809-91d7-880f66e85358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222980222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3222980222
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.788273132
Short name T28
Test name
Test status
Simulation time 231726243 ps
CPU time 0.89 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:07 PM PDT 24
Peak memory 206952 kb
Host smart-76ec476f-bb4f-40f2-9b8b-ce838ccb09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788273132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.788273132
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.526824186
Short name T555
Test name
Test status
Simulation time 12459662479 ps
CPU time 11.79 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:29:19 PM PDT 24
Peak memory 225700 kb
Host smart-604e494c-7941-488a-9b27-80789c39a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526824186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.526824186
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3971585411
Short name T756
Test name
Test status
Simulation time 43135893 ps
CPU time 0.72 seconds
Started Jul 09 05:29:12 PM PDT 24
Finished Jul 09 05:29:14 PM PDT 24
Peak memory 205760 kb
Host smart-80b49863-9414-40eb-91a8-467f2b31b671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971585411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3971585411
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.109671104
Short name T975
Test name
Test status
Simulation time 5796105795 ps
CPU time 27.23 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 233748 kb
Host smart-48f1095a-48de-48f8-9431-853d84f1100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109671104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.109671104
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1225630601
Short name T836
Test name
Test status
Simulation time 46150701 ps
CPU time 0.76 seconds
Started Jul 09 05:28:56 PM PDT 24
Finished Jul 09 05:28:58 PM PDT 24
Peak memory 206484 kb
Host smart-8aa3b44b-d099-493a-b360-e7f705e49cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225630601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1225630601
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4063371355
Short name T953
Test name
Test status
Simulation time 19734616545 ps
CPU time 37.9 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 238444 kb
Host smart-2d04dec0-0302-4f48-b27f-c0ff280a6ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063371355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4063371355
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2044953530
Short name T152
Test name
Test status
Simulation time 5422441045 ps
CPU time 96.8 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 258560 kb
Host smart-fb4d1a02-21a1-4e9e-a275-84c0cabb2d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044953530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2044953530
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3306281350
Short name T630
Test name
Test status
Simulation time 106498249990 ps
CPU time 225.59 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:32:50 PM PDT 24
Peak memory 242076 kb
Host smart-39cc118d-d7a3-4757-b5f6-0212d8778de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306281350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3306281350
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.240677555
Short name T791
Test name
Test status
Simulation time 2510541959 ps
CPU time 19.28 seconds
Started Jul 09 05:28:54 PM PDT 24
Finished Jul 09 05:29:15 PM PDT 24
Peak memory 233876 kb
Host smart-fbfd54d4-ffcd-408d-82c8-565c08ecbb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240677555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.240677555
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1806938967
Short name T260
Test name
Test status
Simulation time 17365670411 ps
CPU time 132.38 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:31:22 PM PDT 24
Peak memory 250244 kb
Host smart-afb82e3c-a3d2-42ed-b0bb-34f3ebaa440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806938967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1806938967
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.767377094
Short name T697
Test name
Test status
Simulation time 1872595782 ps
CPU time 10.35 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 225552 kb
Host smart-260f33ad-493e-4b3c-89a5-a9f214a1d03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767377094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.767377094
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2624381792
Short name T383
Test name
Test status
Simulation time 4902614942 ps
CPU time 47.02 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 225644 kb
Host smart-71db2310-806f-4b0b-8f3f-7630ec2f163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624381792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2624381792
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3157148986
Short name T962
Test name
Test status
Simulation time 67547808 ps
CPU time 1.06 seconds
Started Jul 09 05:29:03 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 217668 kb
Host smart-51824fff-66ca-498c-8982-e64aa7e374b6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157148986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3157148986
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2226505008
Short name T464
Test name
Test status
Simulation time 2561450994 ps
CPU time 4.15 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 233788 kb
Host smart-4c7ef298-bc3b-4f57-a35b-d4d4279894ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226505008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2226505008
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1564251696
Short name T845
Test name
Test status
Simulation time 20482050440 ps
CPU time 19.02 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 233924 kb
Host smart-98b3da08-0a97-4c62-a92e-a734579666c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564251696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1564251696
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2713331524
Short name T580
Test name
Test status
Simulation time 1131484247 ps
CPU time 14.6 seconds
Started Jul 09 05:28:58 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 220268 kb
Host smart-75db675a-e3e3-44e9-b884-a9e83aeb3b77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2713331524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2713331524
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2149790491
Short name T501
Test name
Test status
Simulation time 112941142029 ps
CPU time 236.6 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:32:59 PM PDT 24
Peak memory 266784 kb
Host smart-51f505e5-abc3-454c-9300-a4b48c4acf0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149790491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2149790491
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4111691062
Short name T457
Test name
Test status
Simulation time 20500144687 ps
CPU time 32.79 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:35 PM PDT 24
Peak memory 217392 kb
Host smart-60a64c49-93ba-445f-bdf3-69b694f9870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111691062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4111691062
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1534678242
Short name T987
Test name
Test status
Simulation time 14290062792 ps
CPU time 15.61 seconds
Started Jul 09 05:28:56 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 217364 kb
Host smart-bec8bf7a-7259-4226-b957-6d2ce0323c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534678242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1534678242
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4237400588
Short name T577
Test name
Test status
Simulation time 87709010 ps
CPU time 1.35 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 217308 kb
Host smart-15e6fcee-6da9-4a7a-90b5-e4b79ae9282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237400588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4237400588
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1554305317
Short name T78
Test name
Test status
Simulation time 53145299 ps
CPU time 0.95 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 207156 kb
Host smart-1d0570df-009f-4def-8014-cbf0d28386e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554305317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1554305317
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4239426931
Short name T582
Test name
Test status
Simulation time 27070038761 ps
CPU time 7.7 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 225616 kb
Host smart-9f49ce03-338b-472a-9587-bce3d34bc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239426931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4239426931
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4081599956
Short name T569
Test name
Test status
Simulation time 48311366 ps
CPU time 0.76 seconds
Started Jul 09 05:28:12 PM PDT 24
Finished Jul 09 05:28:15 PM PDT 24
Peak memory 206352 kb
Host smart-5b34cada-13c8-41ef-88d0-be339b521a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081599956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
081599956
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3089029348
Short name T786
Test name
Test status
Simulation time 2773373212 ps
CPU time 10.99 seconds
Started Jul 09 05:28:18 PM PDT 24
Finished Jul 09 05:28:30 PM PDT 24
Peak memory 233900 kb
Host smart-d8235b0d-1eb9-43ed-9879-504d2a8c55bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089029348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3089029348
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.371903437
Short name T645
Test name
Test status
Simulation time 14557389 ps
CPU time 0.77 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:28:13 PM PDT 24
Peak memory 206496 kb
Host smart-a8ed6fd5-60a8-466f-84c6-5ee8ae0572df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371903437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.371903437
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1826284432
Short name T264
Test name
Test status
Simulation time 73242535103 ps
CPU time 272.75 seconds
Started Jul 09 05:28:14 PM PDT 24
Finished Jul 09 05:32:48 PM PDT 24
Peak memory 257000 kb
Host smart-8c3bfa54-e8e0-41a6-9180-68d271479d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826284432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1826284432
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2095650701
Short name T199
Test name
Test status
Simulation time 2828901415 ps
CPU time 69.1 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 250340 kb
Host smart-6f4cb160-8bc4-4703-b019-abef470375bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095650701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2095650701
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4119687936
Short name T295
Test name
Test status
Simulation time 32819775 ps
CPU time 2.67 seconds
Started Jul 09 05:28:12 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 233736 kb
Host smart-192c388d-274c-48d5-b90d-d33731bfac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119687936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4119687936
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.497110794
Short name T502
Test name
Test status
Simulation time 46650349577 ps
CPU time 89.54 seconds
Started Jul 09 05:28:17 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 255872 kb
Host smart-ffe9928b-d937-4efd-98b3-9d7a5203c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497110794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
497110794
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1760022129
Short name T355
Test name
Test status
Simulation time 1240369278 ps
CPU time 5.96 seconds
Started Jul 09 05:28:25 PM PDT 24
Finished Jul 09 05:28:32 PM PDT 24
Peak memory 219812 kb
Host smart-33e83e5f-34f7-4194-8445-bb0bd010fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760022129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1760022129
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1106686951
Short name T189
Test name
Test status
Simulation time 1107759572 ps
CPU time 12.85 seconds
Started Jul 09 05:28:17 PM PDT 24
Finished Jul 09 05:28:31 PM PDT 24
Peak memory 249916 kb
Host smart-d10acaa8-285a-4623-94fb-9f0d6c9da755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106686951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1106686951
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2916369437
Short name T584
Test name
Test status
Simulation time 55138366 ps
CPU time 0.99 seconds
Started Jul 09 05:28:13 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 218804 kb
Host smart-b03f508b-6190-48be-b4f6-4ae356c4d32d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916369437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2916369437
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1291660472
Short name T262
Test name
Test status
Simulation time 784679065 ps
CPU time 5.34 seconds
Started Jul 09 05:28:08 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 225612 kb
Host smart-78431d78-5e12-4e78-b314-e7fa55f4abc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291660472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1291660472
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3834140892
Short name T318
Test name
Test status
Simulation time 15932053086 ps
CPU time 23.48 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:28:36 PM PDT 24
Peak memory 233924 kb
Host smart-dbcb9a4e-c8f8-4fe8-93bb-6058b09b0026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834140892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3834140892
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2293894381
Short name T388
Test name
Test status
Simulation time 430961798 ps
CPU time 4.39 seconds
Started Jul 09 05:28:14 PM PDT 24
Finished Jul 09 05:28:20 PM PDT 24
Peak memory 219888 kb
Host smart-499c8af0-ac44-4ced-b123-5adbba2c009f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2293894381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2293894381
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1036736609
Short name T70
Test name
Test status
Simulation time 87518536 ps
CPU time 1.06 seconds
Started Jul 09 05:28:14 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 236388 kb
Host smart-30111e46-d895-4ee1-8871-c1552a2b21d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036736609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1036736609
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.14982295
Short name T871
Test name
Test status
Simulation time 27142141653 ps
CPU time 250.34 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:32:23 PM PDT 24
Peak memory 266848 kb
Host smart-e9dcaf21-3712-4708-a5da-b6dc8b8ea84e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14982295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_
all.14982295
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1520655108
Short name T324
Test name
Test status
Simulation time 396347520 ps
CPU time 5.88 seconds
Started Jul 09 05:28:10 PM PDT 24
Finished Jul 09 05:28:18 PM PDT 24
Peak memory 217464 kb
Host smart-11ac773f-4c3e-4f61-9b6f-bed24d0af23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520655108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1520655108
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.153021114
Short name T818
Test name
Test status
Simulation time 12016743 ps
CPU time 0.73 seconds
Started Jul 09 05:28:14 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 206500 kb
Host smart-748adb0e-986a-4b2c-bf6e-a34f59ed2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153021114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.153021114
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3751277632
Short name T805
Test name
Test status
Simulation time 267325182 ps
CPU time 11.89 seconds
Started Jul 09 05:28:12 PM PDT 24
Finished Jul 09 05:28:26 PM PDT 24
Peak memory 217524 kb
Host smart-10bf67ba-403e-4805-8b48-34fb61a1a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751277632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3751277632
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1734380202
Short name T29
Test name
Test status
Simulation time 48922723 ps
CPU time 0.8 seconds
Started Jul 09 05:28:07 PM PDT 24
Finished Jul 09 05:28:09 PM PDT 24
Peak memory 206944 kb
Host smart-8cdf4a84-2d75-4092-83bb-cb3b90cd24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734380202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1734380202
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.336563836
Short name T505
Test name
Test status
Simulation time 1196321796 ps
CPU time 9.84 seconds
Started Jul 09 05:28:22 PM PDT 24
Finished Jul 09 05:28:32 PM PDT 24
Peak memory 233772 kb
Host smart-e6a49a22-47d6-48c3-a57f-53fb0beffaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336563836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.336563836
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3153271370
Short name T703
Test name
Test status
Simulation time 142883605 ps
CPU time 0.7 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 206776 kb
Host smart-44fd8331-9fb2-408a-be4f-d44ee4a75631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153271370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3153271370
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2223741941
Short name T179
Test name
Test status
Simulation time 110156529 ps
CPU time 2.11 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:07 PM PDT 24
Peak memory 225436 kb
Host smart-8ada4464-59eb-482c-810d-264c38be06ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223741941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2223741941
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1651114970
Short name T932
Test name
Test status
Simulation time 15935835 ps
CPU time 0.79 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 206516 kb
Host smart-6185f9ac-5d0c-4536-ad52-7cfedff83a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651114970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1651114970
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2235899905
Short name T873
Test name
Test status
Simulation time 1486728772 ps
CPU time 32.72 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 250156 kb
Host smart-22c9a28a-e767-4a65-8a73-655f9698c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235899905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2235899905
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3879246448
Short name T880
Test name
Test status
Simulation time 57246525428 ps
CPU time 94.65 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 256032 kb
Host smart-4aa6f2b5-459b-4a1d-a38b-17d56b845ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879246448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3879246448
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1898241420
Short name T285
Test name
Test status
Simulation time 10267386130 ps
CPU time 40.46 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 242208 kb
Host smart-3401c5c0-ae76-4b4e-91f5-dc762204c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898241420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1898241420
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1418561590
Short name T640
Test name
Test status
Simulation time 3071584380 ps
CPU time 25.29 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 242084 kb
Host smart-cd7b6d3f-e829-4a80-add4-270b26a373cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418561590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1418561590
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3996189723
Short name T252
Test name
Test status
Simulation time 41718630845 ps
CPU time 339.73 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:34:50 PM PDT 24
Peak memory 256984 kb
Host smart-01e45ee0-4c76-4df0-b18b-a45cfcc3bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996189723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3996189723
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2706784049
Short name T621
Test name
Test status
Simulation time 4477596213 ps
CPU time 10.25 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:16 PM PDT 24
Peak memory 225664 kb
Host smart-0dacb58b-ae65-4fc5-b617-69021d04c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706784049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2706784049
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1903251204
Short name T611
Test name
Test status
Simulation time 3064367787 ps
CPU time 8.68 seconds
Started Jul 09 05:29:11 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 233820 kb
Host smart-ff613116-0b2a-4b2c-af91-26757c79b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903251204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1903251204
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2799928390
Short name T741
Test name
Test status
Simulation time 2889918435 ps
CPU time 9.49 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:29:16 PM PDT 24
Peak memory 233832 kb
Host smart-500a7dee-4e7d-4fff-85ec-9df436dfe18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799928390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2799928390
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1029248556
Short name T753
Test name
Test status
Simulation time 2687571069 ps
CPU time 12 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:29:19 PM PDT 24
Peak memory 233816 kb
Host smart-8997d38b-8f73-4cee-9457-35ce2336c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029248556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1029248556
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.206762431
Short name T993
Test name
Test status
Simulation time 1400076314 ps
CPU time 14.45 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 224068 kb
Host smart-5047957e-0eeb-45ac-adb9-f559264c7715
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206762431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.206762431
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2129974936
Short name T249
Test name
Test status
Simulation time 128377423665 ps
CPU time 611.25 seconds
Started Jul 09 05:29:12 PM PDT 24
Finished Jul 09 05:39:24 PM PDT 24
Peak memory 258488 kb
Host smart-8abd42dd-d915-4d62-9ca3-59517e21bb01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129974936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2129974936
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2248444946
Short name T981
Test name
Test status
Simulation time 13022743964 ps
CPU time 37.58 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:49 PM PDT 24
Peak memory 217476 kb
Host smart-fd374c44-ca18-4023-9b7b-6a9e81b1a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248444946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2248444946
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.287555676
Short name T797
Test name
Test status
Simulation time 4408457569 ps
CPU time 3.75 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:15 PM PDT 24
Peak memory 217496 kb
Host smart-0e1b9965-8014-4dd6-a2a0-c3b7c76febc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287555676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.287555676
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1886266751
Short name T695
Test name
Test status
Simulation time 32031648 ps
CPU time 1.74 seconds
Started Jul 09 05:29:18 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 217416 kb
Host smart-dbbd0895-7a66-4047-8acc-18a96666a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886266751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1886266751
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2598617227
Short name T739
Test name
Test status
Simulation time 18356450 ps
CPU time 0.67 seconds
Started Jul 09 05:29:13 PM PDT 24
Finished Jul 09 05:29:15 PM PDT 24
Peak memory 206552 kb
Host smart-2c900892-fd9f-467f-ae05-4dd6b3b17d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598617227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2598617227
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3438982058
Short name T529
Test name
Test status
Simulation time 8539163355 ps
CPU time 16.39 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 225712 kb
Host smart-6dd66a81-6679-4e30-915f-80d5d6eaa9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438982058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3438982058
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3010006131
Short name T386
Test name
Test status
Simulation time 12396522 ps
CPU time 0.72 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:10 PM PDT 24
Peak memory 206256 kb
Host smart-d266639e-e37d-4a92-b714-243935671b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010006131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3010006131
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.87290481
Short name T885
Test name
Test status
Simulation time 430894151 ps
CPU time 2.41 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 225556 kb
Host smart-94f10c43-d913-40d4-9980-9ba2f24b980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87290481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.87290481
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3119709775
Short name T578
Test name
Test status
Simulation time 43361264 ps
CPU time 0.78 seconds
Started Jul 09 05:29:07 PM PDT 24
Finished Jul 09 05:29:08 PM PDT 24
Peak memory 207552 kb
Host smart-950923dc-4848-4c84-b370-c2615885c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119709775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3119709775
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2599689116
Short name T263
Test name
Test status
Simulation time 14644918831 ps
CPU time 78.8 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 266228 kb
Host smart-6abe8955-49d9-4cbb-8f6f-649729eafa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599689116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2599689116
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3076751593
Short name T984
Test name
Test status
Simulation time 10691387330 ps
CPU time 56.93 seconds
Started Jul 09 05:29:06 PM PDT 24
Finished Jul 09 05:30:04 PM PDT 24
Peak memory 240744 kb
Host smart-12f4d026-109a-4544-a559-bd3d0c8f5be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076751593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3076751593
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.71931883
Short name T424
Test name
Test status
Simulation time 1625395710 ps
CPU time 24.04 seconds
Started Jul 09 05:29:13 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 241280 kb
Host smart-e0116669-45be-4ad0-b631-8bae68c8461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71931883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.71931883
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2038775333
Short name T559
Test name
Test status
Simulation time 16152011808 ps
CPU time 87.47 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 258076 kb
Host smart-c90cb2f4-7baa-4f7d-bfef-94766f4aa2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038775333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2038775333
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1745962782
Short name T657
Test name
Test status
Simulation time 33410313 ps
CPU time 2.42 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 233444 kb
Host smart-1346cb9a-9c3a-4af6-a1c7-7edb1f44b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745962782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1745962782
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1972269564
Short name T375
Test name
Test status
Simulation time 99978089 ps
CPU time 2.84 seconds
Started Jul 09 05:29:05 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 233696 kb
Host smart-f5002d51-8e9f-443a-942d-9379851f28a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972269564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1972269564
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1386162690
Short name T245
Test name
Test status
Simulation time 17797796095 ps
CPU time 14.43 seconds
Started Jul 09 05:29:04 PM PDT 24
Finished Jul 09 05:29:20 PM PDT 24
Peak memory 235892 kb
Host smart-e39eedc9-856e-48c2-bde1-3a5e6d421ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386162690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1386162690
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3651216308
Short name T964
Test name
Test status
Simulation time 530944947 ps
CPU time 2.99 seconds
Started Jul 09 05:29:02 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 225432 kb
Host smart-ff0cabce-4355-4ae0-b2c7-d129afbcc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651216308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3651216308
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2082429437
Short name T795
Test name
Test status
Simulation time 294156860 ps
CPU time 3.93 seconds
Started Jul 09 05:29:16 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 224024 kb
Host smart-731076f6-a32b-40c5-b241-3f4d60718907
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082429437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2082429437
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.698721507
Short name T155
Test name
Test status
Simulation time 10683373151 ps
CPU time 202.49 seconds
Started Jul 09 05:29:17 PM PDT 24
Finished Jul 09 05:32:40 PM PDT 24
Peak memory 266480 kb
Host smart-5f6c0901-c065-4bde-a8ae-545b28f06621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698721507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.698721507
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2861314956
Short name T567
Test name
Test status
Simulation time 2507287562 ps
CPU time 22.65 seconds
Started Jul 09 05:29:11 PM PDT 24
Finished Jul 09 05:29:35 PM PDT 24
Peak memory 217456 kb
Host smart-e575e496-1032-4acf-b5ae-b0fdc3359bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861314956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2861314956
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.440795687
Short name T377
Test name
Test status
Simulation time 6326602411 ps
CPU time 5.86 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:08 PM PDT 24
Peak memory 217464 kb
Host smart-959b15d0-e54c-4f53-a5fb-82e456c8ee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440795687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.440795687
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4212419152
Short name T475
Test name
Test status
Simulation time 81461480 ps
CPU time 2.09 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 217368 kb
Host smart-b794a994-251f-4d19-ad99-325203a6b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212419152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4212419152
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3020046539
Short name T364
Test name
Test status
Simulation time 61550956 ps
CPU time 0.86 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:11 PM PDT 24
Peak memory 206984 kb
Host smart-3fe3a36c-4ad9-4673-8eea-57dc18fb338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020046539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3020046539
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1263031703
Short name T604
Test name
Test status
Simulation time 815345292 ps
CPU time 2.77 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 225608 kb
Host smart-3b20fb60-aaa0-44b6-af1e-7e76fcda8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263031703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1263031703
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2865959303
Short name T957
Test name
Test status
Simulation time 31376410 ps
CPU time 0.68 seconds
Started Jul 09 05:29:18 PM PDT 24
Finished Jul 09 05:29:19 PM PDT 24
Peak memory 205752 kb
Host smart-a0621398-9e61-42ff-bc5f-9731ba17d78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865959303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2865959303
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3778144787
Short name T4
Test name
Test status
Simulation time 629544102 ps
CPU time 5.75 seconds
Started Jul 09 05:29:18 PM PDT 24
Finished Jul 09 05:29:24 PM PDT 24
Peak memory 233768 kb
Host smart-4cd9bcb6-ed57-4119-900a-30639a6ed6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778144787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3778144787
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.120482982
Short name T893
Test name
Test status
Simulation time 18848331 ps
CPU time 0.75 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 206880 kb
Host smart-13f53ca3-0341-4b6d-b465-4c130ffb7de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120482982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.120482982
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.171887756
Short name T431
Test name
Test status
Simulation time 96891472721 ps
CPU time 140.22 seconds
Started Jul 09 05:29:13 PM PDT 24
Finished Jul 09 05:31:34 PM PDT 24
Peak memory 250488 kb
Host smart-2dc04f3a-5ba9-462f-be66-3589bde2403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171887756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.171887756
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4185647005
Short name T140
Test name
Test status
Simulation time 7404602128 ps
CPU time 56.49 seconds
Started Jul 09 05:29:16 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 258320 kb
Host smart-b325fa1c-dde4-45f0-a836-bd67fc2d363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185647005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4185647005
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2606782495
Short name T175
Test name
Test status
Simulation time 96136354646 ps
CPU time 223.22 seconds
Started Jul 09 05:29:11 PM PDT 24
Finished Jul 09 05:32:56 PM PDT 24
Peak memory 265860 kb
Host smart-81903666-41de-49b4-a343-53b93b6b6ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606782495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2606782495
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.688930892
Short name T228
Test name
Test status
Simulation time 8394629757 ps
CPU time 19.01 seconds
Started Jul 09 05:29:17 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 233924 kb
Host smart-d2d29dd7-8fad-4352-b249-4402866caae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688930892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.688930892
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1141707504
Short name T43
Test name
Test status
Simulation time 58696016058 ps
CPU time 38.6 seconds
Started Jul 09 05:29:17 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 233904 kb
Host smart-1afb6c61-6e3c-49d8-932a-30a7c2793f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141707504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1141707504
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3318273909
Short name T707
Test name
Test status
Simulation time 124779631 ps
CPU time 2.52 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 233364 kb
Host smart-c4539cdc-984b-41ca-be92-b7d46782e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318273909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3318273909
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2397528203
Short name T596
Test name
Test status
Simulation time 9350469456 ps
CPU time 4.8 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:16 PM PDT 24
Peak memory 233840 kb
Host smart-c00c8188-2945-4509-8b7d-ada317b9f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397528203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2397528203
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1691263020
Short name T929
Test name
Test status
Simulation time 833915515 ps
CPU time 7.56 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 222944 kb
Host smart-213ed0cd-7ad8-41d1-a4ff-f580459a9e87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691263020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1691263020
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2294031152
Short name T609
Test name
Test status
Simulation time 13146948946 ps
CPU time 62.84 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 235852 kb
Host smart-8bca1cf9-24ff-438b-821a-23c6a0efdc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294031152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2294031152
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.515231880
Short name T629
Test name
Test status
Simulation time 8077829087 ps
CPU time 38.83 seconds
Started Jul 09 05:29:08 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 217500 kb
Host smart-52a8ccd3-627f-4a02-b329-f38fc69fdef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515231880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.515231880
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4294091768
Short name T915
Test name
Test status
Simulation time 1350547538 ps
CPU time 3.25 seconds
Started Jul 09 05:29:09 PM PDT 24
Finished Jul 09 05:29:14 PM PDT 24
Peak memory 217292 kb
Host smart-0e991bc4-b43c-451c-bd81-54f03ddde972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294091768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4294091768
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1013538886
Short name T458
Test name
Test status
Simulation time 71968754 ps
CPU time 1.09 seconds
Started Jul 09 05:29:10 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 208600 kb
Host smart-cae61773-0f0d-4b52-92bb-8856a683d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013538886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1013538886
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2976377332
Short name T991
Test name
Test status
Simulation time 100540265 ps
CPU time 0.85 seconds
Started Jul 09 05:29:14 PM PDT 24
Finished Jul 09 05:29:15 PM PDT 24
Peak memory 207216 kb
Host smart-f94f36f5-53d3-4ce4-91f1-c875db27378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976377332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2976377332
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3453146333
Short name T411
Test name
Test status
Simulation time 220372522087 ps
CPU time 40.43 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:30:04 PM PDT 24
Peak memory 235804 kb
Host smart-386f82c0-2ac9-45fc-9a33-1ada537bd3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453146333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3453146333
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1289780872
Short name T321
Test name
Test status
Simulation time 21319876 ps
CPU time 0.71 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 206256 kb
Host smart-6d40a5c1-0a8b-4e40-82b2-7e92a7f84302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289780872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1289780872
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4022334828
Short name T894
Test name
Test status
Simulation time 206196765 ps
CPU time 2.17 seconds
Started Jul 09 05:29:12 PM PDT 24
Finished Jul 09 05:29:15 PM PDT 24
Peak memory 225560 kb
Host smart-94d62b26-6e4f-4af1-94fc-139bffa0968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022334828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4022334828
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1617375892
Short name T336
Test name
Test status
Simulation time 53032444 ps
CPU time 0.78 seconds
Started Jul 09 05:29:16 PM PDT 24
Finished Jul 09 05:29:17 PM PDT 24
Peak memory 207756 kb
Host smart-2aefd936-8ca9-4890-bb1b-fa0096816a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617375892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1617375892
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2082576777
Short name T236
Test name
Test status
Simulation time 5010430656 ps
CPU time 86.93 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 250188 kb
Host smart-1112dedd-9d1f-46f6-81a2-8d36038181cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082576777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2082576777
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3349223464
Short name T242
Test name
Test status
Simulation time 10730739845 ps
CPU time 123.56 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:31:30 PM PDT 24
Peak memory 268236 kb
Host smart-fb13c1b6-01b0-4690-abb3-7d5201d5f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349223464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3349223464
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2093914568
Short name T509
Test name
Test status
Simulation time 4243223786 ps
CPU time 53.49 seconds
Started Jul 09 05:29:11 PM PDT 24
Finished Jul 09 05:30:05 PM PDT 24
Peak memory 252832 kb
Host smart-77038e62-1984-41f5-a7cf-15524465b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093914568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2093914568
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3792965506
Short name T950
Test name
Test status
Simulation time 3233175820 ps
CPU time 4.41 seconds
Started Jul 09 05:29:13 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 235628 kb
Host smart-225e3b27-eaad-400a-9e9e-7c12613ba884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792965506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3792965506
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3959856747
Short name T558
Test name
Test status
Simulation time 8448430312 ps
CPU time 42.24 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 267036 kb
Host smart-6b437424-7605-4f6c-9aed-ab328dc9faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959856747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3959856747
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.791281673
Short name T215
Test name
Test status
Simulation time 11358275439 ps
CPU time 24.98 seconds
Started Jul 09 05:29:16 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 225648 kb
Host smart-6b6d1722-b376-4084-83ee-0c86378e1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791281673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.791281673
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1939447319
Short name T490
Test name
Test status
Simulation time 30109547847 ps
CPU time 28.25 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 240528 kb
Host smart-a7a2ece5-967a-448e-a960-454435bffb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939447319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1939447319
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.382919750
Short name T1018
Test name
Test status
Simulation time 395640333 ps
CPU time 2.1 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 225472 kb
Host smart-b99d0fb8-7f5c-4489-aa36-4d11dd6acfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382919750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.382919750
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.325946893
Short name T612
Test name
Test status
Simulation time 807198068 ps
CPU time 4.32 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 225572 kb
Host smart-024ce14a-9fe1-41d2-a3e3-d77a365aaa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325946893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.325946893
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1689265873
Short name T716
Test name
Test status
Simulation time 311163862 ps
CPU time 3.48 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 219832 kb
Host smart-279dc45d-664d-4f7b-b951-97f145720373
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1689265873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1689265873
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2045515303
Short name T2
Test name
Test status
Simulation time 245129449 ps
CPU time 1.12 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 208828 kb
Host smart-8aec5920-526b-460e-9b2b-f41f33df4cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045515303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2045515303
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3621173897
Short name T919
Test name
Test status
Simulation time 6046750082 ps
CPU time 30.2 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:55 PM PDT 24
Peak memory 217424 kb
Host smart-1ca1dd39-436b-414d-8a4c-6d3e6ce1ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621173897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3621173897
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.996721971
Short name T469
Test name
Test status
Simulation time 2123678836 ps
CPU time 3.72 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 217252 kb
Host smart-d4f37973-05cd-4d3e-b8ad-08b56808644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996721971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.996721971
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4170122712
Short name T288
Test name
Test status
Simulation time 187090255 ps
CPU time 2.93 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 217200 kb
Host smart-8020eade-5157-4174-bb44-3aca86853f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170122712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4170122712
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2351589677
Short name T329
Test name
Test status
Simulation time 56839608 ps
CPU time 0.85 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:20 PM PDT 24
Peak memory 206856 kb
Host smart-77886282-6d64-480b-8233-d8c3b36410bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351589677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2351589677
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2081089878
Short name T922
Test name
Test status
Simulation time 1286324917 ps
CPU time 6.82 seconds
Started Jul 09 05:29:18 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 225512 kb
Host smart-1a504712-7e8e-4638-9f20-156495db376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081089878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2081089878
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.805415718
Short name T347
Test name
Test status
Simulation time 15000617 ps
CPU time 0.71 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 206268 kb
Host smart-56dc03dc-96db-41db-a9f5-93b2286813bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805415718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.805415718
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2673033725
Short name T456
Test name
Test status
Simulation time 3352125855 ps
CPU time 7.84 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 225672 kb
Host smart-5cc66ff0-5e81-49a0-adf9-83945c0a370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673033725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2673033725
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4058839952
Short name T789
Test name
Test status
Simulation time 108560779 ps
CPU time 0.79 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 207384 kb
Host smart-82760b40-0134-4249-8a39-7a567635ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058839952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4058839952
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3707765640
Short name T855
Test name
Test status
Simulation time 15621799829 ps
CPU time 54.71 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 258448 kb
Host smart-b634a2d9-e8fc-479c-ad19-f63d2c0f402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707765640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3707765640
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1531894322
Short name T351
Test name
Test status
Simulation time 1156797268 ps
CPU time 6.33 seconds
Started Jul 09 05:29:17 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 233804 kb
Host smart-c7bcf22e-7ca9-4762-a2b8-94023bb49359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531894322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1531894322
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1274909538
Short name T704
Test name
Test status
Simulation time 18962317646 ps
CPU time 89.29 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 251652 kb
Host smart-5bd1ce46-7367-498f-b6f6-7d62240263c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274909538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1274909538
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4134794239
Short name T770
Test name
Test status
Simulation time 5218595554 ps
CPU time 57.39 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 250280 kb
Host smart-dd21ae6b-e4eb-4b6d-9f55-e02a84b8b686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134794239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4134794239
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2934959052
Short name T97
Test name
Test status
Simulation time 188072665826 ps
CPU time 366.7 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:35:33 PM PDT 24
Peak memory 254600 kb
Host smart-a4b4207d-de97-4452-bf6f-16bce97f0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934959052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2934959052
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.92282195
Short name T535
Test name
Test status
Simulation time 2810218310 ps
CPU time 7.73 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 219952 kb
Host smart-de99d553-aab7-4d9f-af2d-401a6aac9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92282195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.92282195
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2723094795
Short name T857
Test name
Test status
Simulation time 4497976511 ps
CPU time 5.86 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 240416 kb
Host smart-cd39dab1-2358-4e03-b5bd-63c176de0c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723094795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2723094795
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1744472048
Short name T747
Test name
Test status
Simulation time 613475311 ps
CPU time 4 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 233692 kb
Host smart-b8bdb16e-5c6a-4339-815a-ee789ad57a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744472048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1744472048
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.542251661
Short name T499
Test name
Test status
Simulation time 1126983925 ps
CPU time 6.53 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 225572 kb
Host smart-33de61da-21ee-44de-9f3a-b4db8773c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542251661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.542251661
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1622797881
Short name T588
Test name
Test status
Simulation time 3562004089 ps
CPU time 8.77 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 223692 kb
Host smart-86815899-bbdb-46f8-9835-ebdb7f1db31f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622797881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1622797881
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.669729079
Short name T625
Test name
Test status
Simulation time 2120102855 ps
CPU time 21.15 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:53 PM PDT 24
Peak memory 225156 kb
Host smart-291f71c6-325a-466b-892a-35a7b040dc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669729079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.669729079
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2952470684
Short name T646
Test name
Test status
Simulation time 8494430018 ps
CPU time 12.03 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 217480 kb
Host smart-42130c41-00d3-49a4-acc2-7c48e6486467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952470684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2952470684
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2364558867
Short name T462
Test name
Test status
Simulation time 5620152685 ps
CPU time 6.43 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:28 PM PDT 24
Peak memory 217472 kb
Host smart-e2fa44a0-c7aa-4303-b43f-2dcf6fab8a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364558867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2364558867
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.428211758
Short name T286
Test name
Test status
Simulation time 233093257 ps
CPU time 1.25 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 217180 kb
Host smart-a1a143e4-8f05-4966-8180-2e2af5a800d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428211758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.428211758
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3072487421
Short name T715
Test name
Test status
Simulation time 36372958 ps
CPU time 0.78 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 206960 kb
Host smart-3ac27998-e92a-4d3d-ac0e-16ece3387af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072487421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3072487421
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.555548039
Short name T221
Test name
Test status
Simulation time 5468551309 ps
CPU time 3.89 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 225504 kb
Host smart-1eff2c77-8a97-44ad-bf6b-61fe317f3079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555548039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.555548039
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.232319419
Short name T676
Test name
Test status
Simulation time 12267459 ps
CPU time 0.77 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:29:28 PM PDT 24
Peak memory 206388 kb
Host smart-f87dbb72-ef70-43b2-ae70-3668ac525b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232319419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.232319419
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4014830232
Short name T124
Test name
Test status
Simulation time 4666332476 ps
CPU time 15.92 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 233856 kb
Host smart-af9e4675-4a30-46b4-a9b5-c73bbc164117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014830232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4014830232
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3394550732
Short name T397
Test name
Test status
Simulation time 119588320 ps
CPU time 0.79 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 207392 kb
Host smart-1a71d4c4-f151-4c61-8f39-97f65a0e18f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394550732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3394550732
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.360343000
Short name T191
Test name
Test status
Simulation time 53099717132 ps
CPU time 286.57 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:34:12 PM PDT 24
Peak memory 256460 kb
Host smart-d0669957-38ea-4176-901a-8fed76e8422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360343000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.360343000
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2221635149
Short name T718
Test name
Test status
Simulation time 42904960070 ps
CPU time 88 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 241092 kb
Host smart-61f53ab9-e7e1-4cf1-ae0c-c0d0bef0164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221635149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2221635149
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1950526403
Short name T219
Test name
Test status
Simulation time 15056520968 ps
CPU time 132.32 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:31:33 PM PDT 24
Peak memory 255580 kb
Host smart-cdb988f3-a657-40f5-8fb4-bc6384d5a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950526403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1950526403
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1838220185
Short name T783
Test name
Test status
Simulation time 663412226 ps
CPU time 10.69 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:37 PM PDT 24
Peak memory 241880 kb
Host smart-1a38051d-2d19-465f-84c4-538d1c5c861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838220185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1838220185
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1517181096
Short name T938
Test name
Test status
Simulation time 8499922715 ps
CPU time 29.79 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 242000 kb
Host smart-1ff54bc8-f975-41b1-ac5e-b98e9a85c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517181096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1517181096
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2673784888
Short name T591
Test name
Test status
Simulation time 1483783933 ps
CPU time 2.18 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 225480 kb
Host smart-0fa18107-ff02-4a0d-bc70-c466f7fe5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673784888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2673784888
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.157742256
Short name T44
Test name
Test status
Simulation time 26841979077 ps
CPU time 17.84 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:54 PM PDT 24
Peak memory 225636 kb
Host smart-70b42069-ee55-41ef-a1c8-8a09ad8ffc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157742256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.157742256
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1457786368
Short name T838
Test name
Test status
Simulation time 1467558668 ps
CPU time 3.43 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 225568 kb
Host smart-ec67fd16-9e77-4b41-88fb-c38abf896773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457786368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1457786368
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1508504199
Short name T934
Test name
Test status
Simulation time 229342313 ps
CPU time 5.34 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 222712 kb
Host smart-7ddd5562-f56c-454b-b76f-887ef70bcff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508504199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1508504199
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3530947141
Short name T702
Test name
Test status
Simulation time 225341611 ps
CPU time 1.13 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 208596 kb
Host smart-d0147dde-5190-4b5c-8048-bc109601d4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530947141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3530947141
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1327567766
Short name T802
Test name
Test status
Simulation time 819468272 ps
CPU time 2.22 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:24 PM PDT 24
Peak memory 217388 kb
Host smart-8d0e2ace-736e-4b69-81bc-c920bdfad1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327567766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1327567766
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.361290405
Short name T460
Test name
Test status
Simulation time 8512142385 ps
CPU time 21.11 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 217464 kb
Host smart-07fed02a-f854-4171-9a5c-a9e4e9f25312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361290405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.361290405
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2457108730
Short name T643
Test name
Test status
Simulation time 9884032 ps
CPU time 0.69 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 206444 kb
Host smart-4e639502-816a-40a6-8558-8cafaf486028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457108730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2457108730
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1712803052
Short name T952
Test name
Test status
Simulation time 80798689 ps
CPU time 0.79 seconds
Started Jul 09 05:29:32 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 206824 kb
Host smart-cf696ed4-c154-4698-bb09-5086e98ee9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712803052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1712803052
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2161013780
Short name T198
Test name
Test status
Simulation time 1167447324 ps
CPU time 7.93 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:50 PM PDT 24
Peak memory 233624 kb
Host smart-f884a6eb-174c-462a-8790-c7b3e9d177f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161013780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2161013780
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2288118235
Short name T406
Test name
Test status
Simulation time 39975076 ps
CPU time 0.71 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 206104 kb
Host smart-ef4ea637-6d9f-4018-912e-10817ffa9dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288118235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2288118235
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2753312641
Short name T856
Test name
Test status
Simulation time 60839129 ps
CPU time 2.76 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:26 PM PDT 24
Peak memory 233756 kb
Host smart-b25f70a7-6aad-436f-b0b6-2b40a30c4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753312641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2753312641
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.900189352
Short name T376
Test name
Test status
Simulation time 18002356 ps
CPU time 0.78 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 206360 kb
Host smart-9bcdc095-54bd-41b0-a003-53d9b96da703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900189352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.900189352
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1293916908
Short name T877
Test name
Test status
Simulation time 6760662288 ps
CPU time 73.02 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 251220 kb
Host smart-00a8a92c-9b59-4977-be6f-43a0d4ca0245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293916908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1293916908
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1428568081
Short name T862
Test name
Test status
Simulation time 12760914394 ps
CPU time 72.78 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 253212 kb
Host smart-0475b4dd-cfd5-4361-bfd8-4b2abfba05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428568081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1428568081
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2759726852
Short name T255
Test name
Test status
Simulation time 34418094958 ps
CPU time 179.72 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:32:42 PM PDT 24
Peak memory 271496 kb
Host smart-c230b5c8-ca96-4eb9-88cc-4b088f711c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759726852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2759726852
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.959378328
Short name T73
Test name
Test status
Simulation time 187784185 ps
CPU time 7.88 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 233804 kb
Host smart-969e5312-807d-4b23-8aba-0133ed01480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959378328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.959378328
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.679578342
Short name T36
Test name
Test status
Simulation time 661513232 ps
CPU time 4.59 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 235796 kb
Host smart-5b7454a5-50da-4e36-b78d-7d4ac27865d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679578342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.679578342
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2368359669
Short name T538
Test name
Test status
Simulation time 1594104049 ps
CPU time 17.05 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 233768 kb
Host smart-62088b15-d224-4da7-a79e-b10cb5fc68f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368359669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2368359669
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3877086761
Short name T378
Test name
Test status
Simulation time 2690680695 ps
CPU time 23.01 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:49 PM PDT 24
Peak memory 233868 kb
Host smart-3359c941-2047-4b24-8731-46ecb4c06ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877086761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3877086761
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2489309753
Short name T190
Test name
Test status
Simulation time 4659584877 ps
CPU time 10.5 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 233712 kb
Host smart-9884176a-c0a3-4b91-8923-c5494be7bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489309753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2489309753
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.444378524
Short name T453
Test name
Test status
Simulation time 5379277159 ps
CPU time 16.63 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:29:37 PM PDT 24
Peak memory 233844 kb
Host smart-fe212ea1-3242-45d0-9d94-ee3362a97cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444378524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.444378524
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1119823681
Short name T362
Test name
Test status
Simulation time 4833224891 ps
CPU time 13.79 seconds
Started Jul 09 05:29:23 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 221712 kb
Host smart-22c4e567-d5a3-4b99-b909-44b18bf06720
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119823681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1119823681
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3872557353
Short name T809
Test name
Test status
Simulation time 56695679867 ps
CPU time 284.67 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:34:11 PM PDT 24
Peak memory 266728 kb
Host smart-fcebf80f-c10c-4991-829a-0dfeb2635a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872557353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3872557353
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.396013629
Short name T26
Test name
Test status
Simulation time 1804550208 ps
CPU time 7.75 seconds
Started Jul 09 05:29:21 PM PDT 24
Finished Jul 09 05:29:30 PM PDT 24
Peak memory 217824 kb
Host smart-e9ea0299-7828-42d9-9185-d3f65fbcee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396013629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.396013629
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1647384902
Short name T627
Test name
Test status
Simulation time 1582112438 ps
CPU time 3.76 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 217376 kb
Host smart-f08ac8a1-3085-4166-ba8b-cd16400c9976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647384902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1647384902
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.488996765
Short name T440
Test name
Test status
Simulation time 540597630 ps
CPU time 1.86 seconds
Started Jul 09 05:29:20 PM PDT 24
Finished Jul 09 05:29:22 PM PDT 24
Peak memory 217388 kb
Host smart-b8a6562f-5794-43e8-8c55-973772c3556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488996765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.488996765
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1554371681
Short name T694
Test name
Test status
Simulation time 214671674 ps
CPU time 0.9 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:24 PM PDT 24
Peak memory 206952 kb
Host smart-34fb54ce-6fec-4cfe-8cf8-7d3307e2b33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554371681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1554371681
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1585160406
Short name T607
Test name
Test status
Simulation time 1328209251 ps
CPU time 3.77 seconds
Started Jul 09 05:29:19 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 225520 kb
Host smart-96f34dae-fa0a-46fa-8b06-1041c3636bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585160406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1585160406
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1721019323
Short name T365
Test name
Test status
Simulation time 38230870 ps
CPU time 0.7 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 206264 kb
Host smart-a1ceeaa8-3a47-4fd2-818e-f952982bdc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721019323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1721019323
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2127248808
Short name T1
Test name
Test status
Simulation time 940577101 ps
CPU time 8.24 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 233680 kb
Host smart-4927bb5e-05de-4326-a362-ced89160d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127248808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2127248808
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2066124672
Short name T349
Test name
Test status
Simulation time 26131160 ps
CPU time 0.74 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:31 PM PDT 24
Peak memory 206492 kb
Host smart-b20fe4ec-5570-4764-aed7-2879cd5a5154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066124672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2066124672
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.597608701
Short name T675
Test name
Test status
Simulation time 17602746390 ps
CPU time 60.68 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:30:32 PM PDT 24
Peak memory 250268 kb
Host smart-85ce8688-6d1c-4a1d-87d1-144697d17085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597608701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.597608701
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2820881088
Short name T819
Test name
Test status
Simulation time 27049345416 ps
CPU time 118.17 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:31:35 PM PDT 24
Peak memory 254760 kb
Host smart-79dea9b6-354f-401c-a6a5-901837556be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820881088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2820881088
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3788318253
Short name T810
Test name
Test status
Simulation time 53158642 ps
CPU time 3.21 seconds
Started Jul 09 05:29:46 PM PDT 24
Finished Jul 09 05:29:50 PM PDT 24
Peak memory 233620 kb
Host smart-f9414026-0086-41f4-99c4-be3e2cf0ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788318253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3788318253
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4037007381
Short name T35
Test name
Test status
Simulation time 8316543064 ps
CPU time 56.68 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:30:37 PM PDT 24
Peak memory 225596 kb
Host smart-a9d2b766-45fd-463f-a4ec-444409526afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037007381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4037007381
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3231900749
Short name T193
Test name
Test status
Simulation time 7480605921 ps
CPU time 15.13 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 225600 kb
Host smart-4182abcb-0021-42fd-930a-f8e4ea8634c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231900749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3231900749
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2473692697
Short name T812
Test name
Test status
Simulation time 7466227303 ps
CPU time 22.08 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 241532 kb
Host smart-da6adf33-f4e5-4a1c-ab8e-1fdf8dff2324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473692697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2473692697
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3930303051
Short name T267
Test name
Test status
Simulation time 2319950748 ps
CPU time 7.83 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:34 PM PDT 24
Peak memory 225672 kb
Host smart-d0b67af5-9e57-44a1-95e7-1a187fa39976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930303051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3930303051
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2789432187
Short name T400
Test name
Test status
Simulation time 849237030 ps
CPU time 7.13 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 233680 kb
Host smart-9407b41d-ceee-439a-88b9-1607ca769f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789432187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2789432187
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1040216970
Short name T58
Test name
Test status
Simulation time 581083233 ps
CPU time 3.98 seconds
Started Jul 09 05:29:24 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 224176 kb
Host smart-3b482a69-7f21-480d-9804-0feb3740cb30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1040216970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1040216970
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.547158415
Short name T803
Test name
Test status
Simulation time 52719656575 ps
CPU time 381.31 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:35:49 PM PDT 24
Peak memory 258056 kb
Host smart-5d5b7bb3-d373-4258-b1d3-c476aa2c69d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547158415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.547158415
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3271137106
Short name T80
Test name
Test status
Simulation time 12147255 ps
CPU time 0.72 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 206536 kb
Host smart-3310a8ea-c080-478c-a42d-8a0a21faf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271137106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3271137106
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1548217512
Short name T941
Test name
Test status
Simulation time 1905560150 ps
CPU time 1.94 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:29:30 PM PDT 24
Peak memory 208744 kb
Host smart-42961b0d-11d9-48a8-b0b5-b2f7a60df80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548217512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1548217512
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1088161611
Short name T882
Test name
Test status
Simulation time 32763684 ps
CPU time 0.9 seconds
Started Jul 09 05:29:22 PM PDT 24
Finished Jul 09 05:29:24 PM PDT 24
Peak memory 208852 kb
Host smart-fd19b4bb-84d2-4a23-937f-5de05bf166a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088161611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1088161611
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1239072162
Short name T681
Test name
Test status
Simulation time 52568938 ps
CPU time 0.85 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 207260 kb
Host smart-dc7e2696-ccaf-4f5b-947f-c599300a254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239072162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1239072162
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3102044848
Short name T182
Test name
Test status
Simulation time 3672455212 ps
CPU time 11.86 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 225708 kb
Host smart-de51e4b3-769d-44d1-935c-cf8fac5719a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102044848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3102044848
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.206570583
Short name T66
Test name
Test status
Simulation time 75270555 ps
CPU time 0.69 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:39 PM PDT 24
Peak memory 206268 kb
Host smart-e7232d37-4b8d-4a92-a54d-99f13fc65139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206570583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.206570583
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.644129079
Short name T512
Test name
Test status
Simulation time 502900077 ps
CPU time 2.59 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 225576 kb
Host smart-39c0070d-a67d-421d-a6d1-dee426df082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644129079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.644129079
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.797489217
Short name T650
Test name
Test status
Simulation time 20954707 ps
CPU time 0.79 seconds
Started Jul 09 05:29:27 PM PDT 24
Finished Jul 09 05:29:29 PM PDT 24
Peak memory 207504 kb
Host smart-d2deee5a-b0f1-4a75-b458-59d062a99ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797489217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.797489217
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3563545286
Short name T895
Test name
Test status
Simulation time 4167071017 ps
CPU time 20.58 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 250272 kb
Host smart-3f25b0cb-62f9-43d4-9db5-25548714beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563545286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3563545286
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.752331506
Short name T1022
Test name
Test status
Simulation time 184966139523 ps
CPU time 321.36 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:34:53 PM PDT 24
Peak memory 250324 kb
Host smart-3d3a3ede-cb71-4a71-afdc-1222c810a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752331506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.752331506
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4070314329
Short name T853
Test name
Test status
Simulation time 68297282178 ps
CPU time 447.55 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:37:10 PM PDT 24
Peak memory 258492 kb
Host smart-ae0c3f38-3117-4fc9-b41e-614b193ec5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070314329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4070314329
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4047700650
Short name T530
Test name
Test status
Simulation time 636053144 ps
CPU time 12.43 seconds
Started Jul 09 05:29:33 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 233788 kb
Host smart-25d13b21-871c-468f-a7b9-9157b501602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047700650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4047700650
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.584565908
Short name T174
Test name
Test status
Simulation time 1648045676 ps
CPU time 31.12 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:30:08 PM PDT 24
Peak memory 254036 kb
Host smart-59beb85d-b3fb-40f8-aa93-005732bdca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584565908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.584565908
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3779591042
Short name T510
Test name
Test status
Simulation time 1571173581 ps
CPU time 11.95 seconds
Started Jul 09 05:29:33 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 225548 kb
Host smart-aa7679b5-207e-4fdc-9c98-78ed96dba89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779591042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3779591042
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3354238819
Short name T686
Test name
Test status
Simulation time 2104658648 ps
CPU time 18.21 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:57 PM PDT 24
Peak memory 238284 kb
Host smart-76759df0-e18a-4096-98de-039c08d162cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354238819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3354238819
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.770777272
Short name T1004
Test name
Test status
Simulation time 153568446 ps
CPU time 2.73 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 225400 kb
Host smart-c53d4de0-aa23-45c2-87c1-b70c54a4f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770777272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.770777272
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3786916782
Short name T333
Test name
Test status
Simulation time 5694014563 ps
CPU time 17.98 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:29:57 PM PDT 24
Peak memory 233844 kb
Host smart-e4da59ad-5e58-4ff8-ba03-1008846e3118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786916782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3786916782
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2583978446
Short name T403
Test name
Test status
Simulation time 336318502 ps
CPU time 3.68 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:39 PM PDT 24
Peak memory 221436 kb
Host smart-d5ee3c57-33db-4fa3-b6cb-70d0e1400aff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2583978446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2583978446
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3916533206
Short name T615
Test name
Test status
Simulation time 3490028489 ps
CPU time 30.37 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 217564 kb
Host smart-fca0e1e9-f7a8-4d90-9c4f-516e0246a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916533206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3916533206
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1040126435
Short name T366
Test name
Test status
Simulation time 33690134 ps
CPU time 0.73 seconds
Started Jul 09 05:29:25 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 206540 kb
Host smart-7e33b1e2-1c5e-47dd-87eb-47cd7cb04a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040126435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1040126435
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2340401274
Short name T610
Test name
Test status
Simulation time 78939751 ps
CPU time 3.54 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 217332 kb
Host smart-492497d5-ddf0-4f1c-9de1-fbe9954dbb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340401274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2340401274
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2087082434
Short name T641
Test name
Test status
Simulation time 25908956 ps
CPU time 0.78 seconds
Started Jul 09 05:29:28 PM PDT 24
Finished Jul 09 05:29:30 PM PDT 24
Peak memory 207248 kb
Host smart-bcb3a733-547c-4975-8102-5f1e244b4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087082434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2087082434
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1467216210
Short name T762
Test name
Test status
Simulation time 33555043 ps
CPU time 2.44 seconds
Started Jul 09 05:29:32 PM PDT 24
Finished Jul 09 05:29:35 PM PDT 24
Peak memory 225260 kb
Host smart-ff502b94-454e-47da-97b0-06f5058c0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467216210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1467216210
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3358168269
Short name T623
Test name
Test status
Simulation time 85752027 ps
CPU time 0.69 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:29:39 PM PDT 24
Peak memory 206276 kb
Host smart-d71bab05-7afd-4620-906c-7469b4ffba8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358168269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3358168269
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.306769837
Short name T872
Test name
Test status
Simulation time 1804391506 ps
CPU time 9.04 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 225496 kb
Host smart-aacd04f9-470a-48ca-8bc4-a89a4beee192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306769837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.306769837
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2980453183
Short name T304
Test name
Test status
Simulation time 30834477 ps
CPU time 0.8 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:37 PM PDT 24
Peak memory 207400 kb
Host smart-515f02bc-074c-4565-8033-3177305fb1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980453183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2980453183
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2705756560
Short name T1013
Test name
Test status
Simulation time 204274824 ps
CPU time 4.63 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 225572 kb
Host smart-cd09a8f9-df83-46cf-96e9-06f967be9bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705756560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2705756560
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4127655008
Short name T213
Test name
Test status
Simulation time 80112786641 ps
CPU time 139.29 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:31:51 PM PDT 24
Peak memory 257840 kb
Host smart-abe75890-4ded-4127-8690-5469d051bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127655008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4127655008
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2517882374
Short name T188
Test name
Test status
Simulation time 6251930810 ps
CPU time 89.82 seconds
Started Jul 09 05:29:34 PM PDT 24
Finished Jul 09 05:31:04 PM PDT 24
Peak memory 254148 kb
Host smart-74af932c-9b77-474d-b06c-abb9d772dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517882374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2517882374
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1773041615
Short name T983
Test name
Test status
Simulation time 169947008 ps
CPU time 9.08 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 235820 kb
Host smart-69d6fa6c-308c-4a59-9066-ab7002671a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773041615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1773041615
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3002802425
Short name T94
Test name
Test status
Simulation time 1984472461 ps
CPU time 27.44 seconds
Started Jul 09 05:29:28 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 251884 kb
Host smart-0f47e4de-1171-46c7-ab32-09af954ea1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002802425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3002802425
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1780424838
Short name T339
Test name
Test status
Simulation time 829684795 ps
CPU time 5.55 seconds
Started Jul 09 05:29:34 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 222956 kb
Host smart-61aff64c-bf5d-443d-b0bf-86020ea9b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780424838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1780424838
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.799628869
Short name T1016
Test name
Test status
Simulation time 48538197 ps
CPU time 2.22 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 233468 kb
Host smart-bc4f08b6-2273-400d-927f-30bc736207e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799628869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.799628869
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2477623998
Short name T889
Test name
Test status
Simulation time 11082211015 ps
CPU time 8.82 seconds
Started Jul 09 05:29:29 PM PDT 24
Finished Jul 09 05:29:39 PM PDT 24
Peak memory 233908 kb
Host smart-875480b2-2234-4c57-be5d-c0d4a362faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477623998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2477623998
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2945751032
Short name T878
Test name
Test status
Simulation time 183016094 ps
CPU time 4.21 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 233632 kb
Host smart-84bdec1a-710e-44ee-bc3c-9d0e164eebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945751032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2945751032
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4117514748
Short name T354
Test name
Test status
Simulation time 1573658250 ps
CPU time 11.53 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:53 PM PDT 24
Peak memory 223076 kb
Host smart-0926afc5-5ad1-4ea2-865c-9e55fb6408fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4117514748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4117514748
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1370101426
Short name T20
Test name
Test status
Simulation time 88983942 ps
CPU time 0.96 seconds
Started Jul 09 05:29:26 PM PDT 24
Finished Jul 09 05:29:28 PM PDT 24
Peak memory 208508 kb
Host smart-79e09ed8-4893-4ce6-a438-cff447b4378e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370101426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1370101426
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1584674567
Short name T322
Test name
Test status
Simulation time 1166265681 ps
CPU time 5.22 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 217276 kb
Host smart-c5136496-80c4-4b4e-b34d-d4429395ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584674567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1584674567
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2504237887
Short name T87
Test name
Test status
Simulation time 4643369600 ps
CPU time 3.52 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 217536 kb
Host smart-185cb3be-64a8-47d2-b8c4-835e94048a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504237887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2504237887
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3867344027
Short name T1015
Test name
Test status
Simulation time 152967952 ps
CPU time 1.14 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 208360 kb
Host smart-f67a1fd0-9b49-42b2-889b-2632c9ecf515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867344027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3867344027
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2679575300
Short name T666
Test name
Test status
Simulation time 184532345 ps
CPU time 0.8 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:32 PM PDT 24
Peak memory 206944 kb
Host smart-4d6201a4-7d6d-4c36-a3a1-23aef9313b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679575300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2679575300
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.118710191
Short name T484
Test name
Test status
Simulation time 35644645741 ps
CPU time 14.59 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 241756 kb
Host smart-324c3658-a7c7-40d2-be56-4e02b168fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118710191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.118710191
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4132459866
Short name T144
Test name
Test status
Simulation time 19210331 ps
CPU time 0.75 seconds
Started Jul 09 05:28:15 PM PDT 24
Finished Jul 09 05:28:17 PM PDT 24
Peak memory 205824 kb
Host smart-57c9e30f-bad3-40f3-92d1-12c096fce84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132459866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
132459866
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2595981132
Short name T413
Test name
Test status
Simulation time 108760748 ps
CPU time 2.65 seconds
Started Jul 09 05:28:23 PM PDT 24
Finished Jul 09 05:28:25 PM PDT 24
Peak memory 225524 kb
Host smart-ebe557ff-146b-44e1-9ff9-f9e6a2a728a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595981132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2595981132
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.182128987
Short name T767
Test name
Test status
Simulation time 16967839 ps
CPU time 0.76 seconds
Started Jul 09 05:28:15 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 207848 kb
Host smart-77c511cf-0bd7-4a86-b8c1-21a33889ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182128987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.182128987
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4156239736
Short name T779
Test name
Test status
Simulation time 9175562848 ps
CPU time 81.03 seconds
Started Jul 09 05:28:18 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 257148 kb
Host smart-50f55cb9-7f49-453d-ba0b-48db7494954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156239736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4156239736
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.22452921
Short name T866
Test name
Test status
Simulation time 3795660110 ps
CPU time 16.3 seconds
Started Jul 09 05:28:23 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 225732 kb
Host smart-2a3816b7-6512-4fe7-955e-e7dc2cdbbbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22452921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.22452921
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3831965168
Short name T717
Test name
Test status
Simulation time 5074040811 ps
CPU time 67.18 seconds
Started Jul 09 05:28:17 PM PDT 24
Finished Jul 09 05:29:25 PM PDT 24
Peak memory 256220 kb
Host smart-31f5047d-13cc-4539-ba26-922da2c31d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831965168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3831965168
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.828827680
Short name T274
Test name
Test status
Simulation time 2658921180 ps
CPU time 33.59 seconds
Started Jul 09 05:28:17 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 225564 kb
Host smart-e32c0dbf-f862-4e0a-ae51-701334e31473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828827680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.828827680
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3321240295
Short name T316
Test name
Test status
Simulation time 18356704 ps
CPU time 0.74 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:18 PM PDT 24
Peak memory 216896 kb
Host smart-e4b41197-68c8-43f1-9910-8b047fa0d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321240295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3321240295
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2515362304
Short name T970
Test name
Test status
Simulation time 1661248837 ps
CPU time 5.17 seconds
Started Jul 09 05:28:28 PM PDT 24
Finished Jul 09 05:28:34 PM PDT 24
Peak memory 225400 kb
Host smart-5efa5474-9024-4cd5-8881-50796efd7754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515362304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2515362304
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.811737376
Short name T738
Test name
Test status
Simulation time 12921633076 ps
CPU time 11.85 seconds
Started Jul 09 05:28:18 PM PDT 24
Finished Jul 09 05:28:30 PM PDT 24
Peak memory 225676 kb
Host smart-cc59c56c-a7ce-42a8-b1e7-6951f76d79be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811737376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.811737376
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2670295891
Short name T736
Test name
Test status
Simulation time 50296827 ps
CPU time 0.99 seconds
Started Jul 09 05:28:11 PM PDT 24
Finished Jul 09 05:28:14 PM PDT 24
Peak memory 218888 kb
Host smart-9ff3ba05-7e3a-40d0-9686-11de748a0d7f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670295891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2670295891
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.408521895
Short name T924
Test name
Test status
Simulation time 1042844361 ps
CPU time 6.67 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:24 PM PDT 24
Peak memory 225416 kb
Host smart-608e69d2-b030-42fa-b325-d6f58887211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408521895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
408521895
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4125718165
Short name T998
Test name
Test status
Simulation time 453854636 ps
CPU time 3.14 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:20 PM PDT 24
Peak memory 233704 kb
Host smart-bf0da81e-9238-48c9-ad3b-ea669192f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125718165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4125718165
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2723862315
Short name T664
Test name
Test status
Simulation time 350533706 ps
CPU time 4.02 seconds
Started Jul 09 05:28:17 PM PDT 24
Finished Jul 09 05:28:22 PM PDT 24
Peak memory 220396 kb
Host smart-6dcba580-893c-48b1-8038-5ac6eb7a58dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2723862315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2723862315
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3870979288
Short name T72
Test name
Test status
Simulation time 271698250 ps
CPU time 1.08 seconds
Started Jul 09 05:28:30 PM PDT 24
Finished Jul 09 05:28:31 PM PDT 24
Peak memory 236388 kb
Host smart-0ef2e183-ebbb-4d24-9eb6-330324fa22bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870979288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3870979288
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.944413609
Short name T1017
Test name
Test status
Simulation time 18020806876 ps
CPU time 115.75 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 250312 kb
Host smart-8e486397-0d04-47c3-9cf5-b7b495880e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944413609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.944413609
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1257547797
Short name T570
Test name
Test status
Simulation time 20120105034 ps
CPU time 24.56 seconds
Started Jul 09 05:28:18 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 217408 kb
Host smart-78c1443c-4143-4523-99b7-721cee1b26ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257547797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1257547797
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2096837293
Short name T305
Test name
Test status
Simulation time 2944141368 ps
CPU time 8.08 seconds
Started Jul 09 05:28:16 PM PDT 24
Finished Jul 09 05:28:25 PM PDT 24
Peak memory 217380 kb
Host smart-481bdbe6-eef8-44cb-91b9-b48d06a1d543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096837293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2096837293
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1774416701
Short name T869
Test name
Test status
Simulation time 442270096 ps
CPU time 1.81 seconds
Started Jul 09 05:28:15 PM PDT 24
Finished Jul 09 05:28:18 PM PDT 24
Peak memory 217404 kb
Host smart-f0e75fe3-cca2-4a1f-a7b6-24d51d1ddf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774416701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1774416701
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1546570560
Short name T566
Test name
Test status
Simulation time 692446381 ps
CPU time 0.97 seconds
Started Jul 09 05:28:15 PM PDT 24
Finished Jul 09 05:28:17 PM PDT 24
Peak memory 207960 kb
Host smart-fbb444e7-4521-4d5e-b2cf-0d5438c9d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546570560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1546570560
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4281472668
Short name T237
Test name
Test status
Simulation time 1824746623 ps
CPU time 10.2 seconds
Started Jul 09 05:28:28 PM PDT 24
Finished Jul 09 05:28:39 PM PDT 24
Peak memory 235556 kb
Host smart-c2d16b15-3c17-46ae-a217-81f5b6d90227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281472668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4281472668
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1254865386
Short name T775
Test name
Test status
Simulation time 15092716 ps
CPU time 0.78 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 206712 kb
Host smart-83d21453-55af-400c-af46-e2cd2026da93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254865386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1254865386
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2834883575
Short name T353
Test name
Test status
Simulation time 1657590401 ps
CPU time 6.05 seconds
Started Jul 09 05:29:33 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 233772 kb
Host smart-0eb3f55d-9526-4c8c-ad03-e9d37fd5916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834883575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2834883575
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1121706999
Short name T908
Test name
Test status
Simulation time 22330858 ps
CPU time 0.76 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 207852 kb
Host smart-6c9bfd69-bf87-4411-81bf-b0fdcd4a4938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121706999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1121706999
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.158796416
Short name T598
Test name
Test status
Simulation time 15038708368 ps
CPU time 60.22 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:30:37 PM PDT 24
Peak memory 239620 kb
Host smart-22dd9244-def5-428e-afe0-c81b37e243cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158796416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.158796416
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4049079750
Short name T602
Test name
Test status
Simulation time 3104549929 ps
CPU time 25.08 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 242176 kb
Host smart-4f5a0776-30c6-4f5d-8902-22a6a9fc9c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049079750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4049079750
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4031125268
Short name T620
Test name
Test status
Simulation time 473469386 ps
CPU time 3.52 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 225492 kb
Host smart-f909b228-5a04-49b1-852b-197e49f237bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031125268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4031125268
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1615031080
Short name T246
Test name
Test status
Simulation time 1789750582 ps
CPU time 17.63 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 233664 kb
Host smart-d1b80940-9388-45e8-8392-58cf4c9eebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615031080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1615031080
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1464506112
Short name T426
Test name
Test status
Simulation time 2310041670 ps
CPU time 7.5 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:49 PM PDT 24
Peak memory 225652 kb
Host smart-a3adc678-f02a-460e-90a3-20707fe64d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464506112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1464506112
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2039448863
Short name T928
Test name
Test status
Simulation time 2512865568 ps
CPU time 28.58 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:30:06 PM PDT 24
Peak memory 225676 kb
Host smart-2ea82f3a-fba6-480d-a604-c50d2eed6408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039448863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2039448863
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.542676045
Short name T420
Test name
Test status
Simulation time 10433839080 ps
CPU time 8.37 seconds
Started Jul 09 05:29:33 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 233856 kb
Host smart-e2157884-14cd-4a55-85dc-05dd0200e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542676045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.542676045
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1352009548
Short name T444
Test name
Test status
Simulation time 1702149833 ps
CPU time 2.17 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 224668 kb
Host smart-26b5c75b-06ae-4cf7-9e1c-458405871769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352009548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1352009548
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.302320154
Short name T394
Test name
Test status
Simulation time 1276167227 ps
CPU time 6.92 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 220324 kb
Host smart-659182a1-d479-489f-a804-c92c946d8906
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302320154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.302320154
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2929442443
Short name T18
Test name
Test status
Simulation time 21850701639 ps
CPU time 116.96 seconds
Started Jul 09 05:29:45 PM PDT 24
Finished Jul 09 05:31:43 PM PDT 24
Peak memory 257960 kb
Host smart-7c7d0172-e80c-46ea-ae71-19fe56e6e59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929442443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2929442443
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3565858486
Short name T287
Test name
Test status
Simulation time 3407461088 ps
CPU time 4.77 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:36 PM PDT 24
Peak memory 217460 kb
Host smart-7ef839e1-9a84-402a-be86-9b003092ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565858486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3565858486
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.782433148
Short name T278
Test name
Test status
Simulation time 3767291709 ps
CPU time 14.42 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 217536 kb
Host smart-47e16ca9-9390-493a-bb72-a0b9856cf36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782433148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.782433148
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2346063697
Short name T847
Test name
Test status
Simulation time 389227438 ps
CPU time 6.15 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 217268 kb
Host smart-16c3f2cd-83d3-42f6-a447-45458701d675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346063697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2346063697
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2284398597
Short name T601
Test name
Test status
Simulation time 45239525 ps
CPU time 0.89 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 207956 kb
Host smart-79654ffc-17d2-4181-8b54-f037662b1cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284398597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2284398597
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2672985347
Short name T223
Test name
Test status
Simulation time 3767105991 ps
CPU time 13.95 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 233740 kb
Host smart-2df7e769-f78f-4099-b4df-298e87678baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672985347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2672985347
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3119702800
Short name T815
Test name
Test status
Simulation time 54221343 ps
CPU time 0.77 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 205736 kb
Host smart-051b643e-9496-4179-b18e-505b38d82e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119702800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3119702800
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2253252450
Short name T93
Test name
Test status
Simulation time 913646062 ps
CPU time 9.76 seconds
Started Jul 09 05:29:34 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 225492 kb
Host smart-94bd2a4b-d856-4aa4-930c-60e8a8bce1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253252450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2253252450
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.33731188
Short name T352
Test name
Test status
Simulation time 41549521 ps
CPU time 0.75 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 206696 kb
Host smart-61a02c10-b3a1-4878-b486-cb2a0152acfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33731188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.33731188
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4161338423
Short name T972
Test name
Test status
Simulation time 15034480987 ps
CPU time 65.19 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 255580 kb
Host smart-0585a3f5-eff4-4334-a1af-ec34867e492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161338423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4161338423
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2858417162
Short name T757
Test name
Test status
Simulation time 143510098538 ps
CPU time 293.87 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:34:30 PM PDT 24
Peak memory 257804 kb
Host smart-e314a565-ff61-40fc-9cc6-6b3e215d922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858417162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2858417162
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.926916101
Short name T384
Test name
Test status
Simulation time 1480760343 ps
CPU time 4.85 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 218808 kb
Host smart-c9d521d0-23cb-4161-9201-0de6df912ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926916101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.926916101
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3583112341
Short name T590
Test name
Test status
Simulation time 1741644320 ps
CPU time 14.85 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:51 PM PDT 24
Peak memory 225576 kb
Host smart-eda68c1d-c3bf-44cd-855e-58ba334483b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583112341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3583112341
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1968239035
Short name T868
Test name
Test status
Simulation time 444621696467 ps
CPU time 206.9 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:33:06 PM PDT 24
Peak memory 250584 kb
Host smart-ccf6c8e8-0bfa-451e-8755-8ec12ef0adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968239035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1968239035
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2161433010
Short name T859
Test name
Test status
Simulation time 1358126820 ps
CPU time 5.81 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:43 PM PDT 24
Peak memory 225548 kb
Host smart-9563f21b-9144-481b-ae71-6526559af766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161433010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2161433010
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3077818274
Short name T560
Test name
Test status
Simulation time 10607744237 ps
CPU time 86.95 seconds
Started Jul 09 05:29:34 PM PDT 24
Finished Jul 09 05:31:02 PM PDT 24
Peak memory 225616 kb
Host smart-7b97564d-dcba-4cc3-8d43-19cf89a55174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077818274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3077818274
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1957785496
Short name T372
Test name
Test status
Simulation time 277123685 ps
CPU time 3.98 seconds
Started Jul 09 05:29:34 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 225580 kb
Host smart-d8edc89e-5143-48df-b4c4-4973dbda27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957785496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1957785496
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1020226975
Short name T945
Test name
Test status
Simulation time 45278092843 ps
CPU time 16.91 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 233896 kb
Host smart-5c80c4c1-ccb3-452e-81a0-1bcd6caeec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020226975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1020226975
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3673638823
Short name T160
Test name
Test status
Simulation time 970668544 ps
CPU time 6.43 seconds
Started Jul 09 05:29:35 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 219764 kb
Host smart-21e46db5-0f6f-43a9-92cb-2813adddb912
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3673638823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3673638823
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2442273287
Short name T55
Test name
Test status
Simulation time 25761586263 ps
CPU time 144.59 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:32:08 PM PDT 24
Peak memory 250808 kb
Host smart-14901e8e-5d11-49ed-a164-dd64e4981a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442273287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2442273287
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2254200850
Short name T381
Test name
Test status
Simulation time 1674659049 ps
CPU time 8.42 seconds
Started Jul 09 05:29:30 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 217588 kb
Host smart-0fcdac52-ff74-43ca-ad20-ad3f7100628f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254200850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2254200850
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3114277547
Short name T63
Test name
Test status
Simulation time 3968840375 ps
CPU time 5.21 seconds
Started Jul 09 05:29:31 PM PDT 24
Finished Jul 09 05:29:37 PM PDT 24
Peak memory 217468 kb
Host smart-ebe77c38-1806-4938-881f-c23f2230cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114277547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3114277547
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.261725520
Short name T315
Test name
Test status
Simulation time 17985103 ps
CPU time 1.19 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 217376 kb
Host smart-3966b56f-a1d2-4e9f-ad0a-72cc26e1c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261725520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.261725520
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1394060023
Short name T521
Test name
Test status
Simulation time 122235933 ps
CPU time 0.85 seconds
Started Jul 09 05:29:33 PM PDT 24
Finished Jul 09 05:29:35 PM PDT 24
Peak memory 206852 kb
Host smart-8bc9b900-bebe-4f14-b241-2bd8d8e340ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394060023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1394060023
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.794863810
Short name T849
Test name
Test status
Simulation time 127084052 ps
CPU time 2.4 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 233340 kb
Host smart-5759aebe-7d7f-49f6-be21-8f782c37c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794863810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.794863810
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2917618809
Short name T990
Test name
Test status
Simulation time 96657378 ps
CPU time 0.71 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:39 PM PDT 24
Peak memory 205808 kb
Host smart-6d4a6a89-b8e4-4f3b-b6c6-f49099e868b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917618809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2917618809
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3618746066
Short name T985
Test name
Test status
Simulation time 583691640 ps
CPU time 9.34 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:29:53 PM PDT 24
Peak memory 225540 kb
Host smart-eef56600-d2fd-402e-ac84-d685f072b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618746066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3618746066
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1923630693
Short name T439
Test name
Test status
Simulation time 76295734 ps
CPU time 0.76 seconds
Started Jul 09 05:29:32 PM PDT 24
Finished Jul 09 05:29:33 PM PDT 24
Peak memory 207524 kb
Host smart-1e388e84-8e94-4f38-b738-22df019db1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923630693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1923630693
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3111858982
Short name T374
Test name
Test status
Simulation time 3711847029 ps
CPU time 52.96 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 255700 kb
Host smart-b785dd95-87fe-4bb5-9dac-98f615d415d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111858982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3111858982
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2328784063
Short name T433
Test name
Test status
Simulation time 38609127206 ps
CPU time 366.98 seconds
Started Jul 09 05:29:49 PM PDT 24
Finished Jul 09 05:35:56 PM PDT 24
Peak memory 254396 kb
Host smart-04534a17-ef8e-41dc-bedd-ce05b5e20c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328784063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2328784063
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3801250848
Short name T273
Test name
Test status
Simulation time 1372173852 ps
CPU time 9.38 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 235624 kb
Host smart-72117e27-02d0-4a86-9b84-5c8f4f7ccd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801250848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3801250848
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1824639798
Short name T897
Test name
Test status
Simulation time 9726544787 ps
CPU time 13.5 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 233756 kb
Host smart-105c823a-da02-4944-bbe6-d946b9ef131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824639798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1824639798
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1885116395
Short name T404
Test name
Test status
Simulation time 78253949259 ps
CPU time 138.35 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:32:01 PM PDT 24
Peak memory 250280 kb
Host smart-b631211b-4c00-48eb-80e7-bd8db380dbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885116395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1885116395
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.243769926
Short name T982
Test name
Test status
Simulation time 186638675 ps
CPU time 2.55 seconds
Started Jul 09 05:29:44 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 233528 kb
Host smart-98aa7361-67c2-4aaa-997a-587dbd253a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243769926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.243769926
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3642677433
Short name T898
Test name
Test status
Simulation time 345031586 ps
CPU time 2.4 seconds
Started Jul 09 05:29:45 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 225552 kb
Host smart-825b6848-818e-4b16-81f8-0b637c8dfb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642677433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3642677433
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4190359866
Short name T688
Test name
Test status
Simulation time 1071146714 ps
CPU time 5.82 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 221588 kb
Host smart-8dd8581a-a397-4ab7-884d-96adc0ffcb67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4190359866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4190359866
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2938288692
Short name T282
Test name
Test status
Simulation time 2947074968 ps
CPU time 17.63 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 217476 kb
Host smart-7a98b987-3216-4d87-b670-df1b2da6aabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938288692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2938288692
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2857905348
Short name T940
Test name
Test status
Simulation time 2471847766 ps
CPU time 2.34 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 217464 kb
Host smart-9794956c-8e33-4a34-98bf-fd5aba4746ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857905348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2857905348
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3277320092
Short name T689
Test name
Test status
Simulation time 88100381 ps
CPU time 1.01 seconds
Started Jul 09 05:29:39 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 208120 kb
Host smart-2b4a9a9e-2d4d-401c-af2f-f82da9e93ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277320092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3277320092
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1523115830
Short name T414
Test name
Test status
Simulation time 53017297 ps
CPU time 0.83 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 207256 kb
Host smart-b52b78d9-b926-45d2-bc98-ae9aaed609b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523115830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1523115830
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1927740280
Short name T326
Test name
Test status
Simulation time 115590462 ps
CPU time 2.28 seconds
Started Jul 09 05:29:36 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 225308 kb
Host smart-01dac553-46e3-410a-b9c0-5ccb6f600fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927740280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1927740280
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2385836469
Short name T840
Test name
Test status
Simulation time 75594744 ps
CPU time 0.74 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 205776 kb
Host smart-9bb7bc0d-8125-4f91-8cad-3b9db0d72ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385836469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2385836469
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1205158959
Short name T724
Test name
Test status
Simulation time 215041165 ps
CPU time 5.9 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:50 PM PDT 24
Peak memory 233656 kb
Host smart-c84a9f89-e761-45fc-acfd-51e26db6fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205158959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1205158959
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4249013389
Short name T369
Test name
Test status
Simulation time 15493012 ps
CPU time 0.76 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 206480 kb
Host smart-b2917815-9b21-4e19-ab45-bc2ce9dd6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249013389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4249013389
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2161826068
Short name T892
Test name
Test status
Simulation time 19374997106 ps
CPU time 64.61 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 250628 kb
Host smart-78a5d203-07b7-400d-b8ad-29c600ce9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161826068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2161826068
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3024596225
Short name T450
Test name
Test status
Simulation time 4701541502 ps
CPU time 76.12 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 250428 kb
Host smart-24884b4e-16fc-4062-9311-adc9ea06dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024596225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3024596225
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2302529927
Short name T828
Test name
Test status
Simulation time 1432401815 ps
CPU time 26.97 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 233752 kb
Host smart-31855022-1010-4677-b158-8d6ea2830e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302529927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2302529927
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3789118495
Short name T829
Test name
Test status
Simulation time 7247254891 ps
CPU time 44.77 seconds
Started Jul 09 05:29:38 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 250728 kb
Host smart-bf734a07-7dde-4e68-9f6c-c7ab317734c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789118495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3789118495
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.678832900
Short name T913
Test name
Test status
Simulation time 3925753930 ps
CPU time 10.17 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:53 PM PDT 24
Peak memory 233748 kb
Host smart-fcab6057-4a5b-4c04-ac6a-c290b4446f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678832900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.678832900
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1705139590
Short name T515
Test name
Test status
Simulation time 358255196 ps
CPU time 11 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 235500 kb
Host smart-20b3d353-9ae8-4251-8fc8-e7c0d04592c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705139590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1705139590
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1301918623
Short name T298
Test name
Test status
Simulation time 380866279 ps
CPU time 2.31 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 224900 kb
Host smart-dc2a38ec-4339-4c45-bdbc-99eda20f254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301918623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1301918623
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1204184860
Short name T234
Test name
Test status
Simulation time 5417969632 ps
CPU time 5.74 seconds
Started Jul 09 05:29:37 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 225704 kb
Host smart-9bcadc95-5d68-45a8-a6d5-5e81f603af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204184860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1204184860
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2656266748
Short name T745
Test name
Test status
Simulation time 495475982 ps
CPU time 6.85 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:29:50 PM PDT 24
Peak memory 222632 kb
Host smart-6e2921f8-edd8-4af8-96b8-598cf831d717
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2656266748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2656266748
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.365826138
Short name T154
Test name
Test status
Simulation time 18755046649 ps
CPU time 196.97 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:33:01 PM PDT 24
Peak memory 251472 kb
Host smart-3ef8c4a3-4e40-44d1-bdbe-81675e07612f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365826138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.365826138
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3927216914
Short name T279
Test name
Test status
Simulation time 16101518260 ps
CPU time 25.29 seconds
Started Jul 09 05:29:46 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 217368 kb
Host smart-d47e9145-7c7f-4300-a602-0f09d64b0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927216914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3927216914
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.321163603
Short name T890
Test name
Test status
Simulation time 1189188812 ps
CPU time 4.57 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 217356 kb
Host smart-da7c82e4-c661-43cf-b28e-2a449646b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321163603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.321163603
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.553056416
Short name T978
Test name
Test status
Simulation time 29249960 ps
CPU time 0.82 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:41 PM PDT 24
Peak memory 207868 kb
Host smart-867fd31e-d738-4f99-adae-908e606211c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553056416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.553056416
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1046958932
Short name T476
Test name
Test status
Simulation time 50384997 ps
CPU time 0.83 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:42 PM PDT 24
Peak memory 206960 kb
Host smart-2ffb5d1f-cbd7-4825-8ee8-3865e5f829d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046958932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1046958932
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.216757677
Short name T701
Test name
Test status
Simulation time 247869000 ps
CPU time 3.22 seconds
Started Jul 09 05:29:44 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 233632 kb
Host smart-00c90ef9-1a55-41b1-9f6c-48961934e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216757677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.216757677
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1522570768
Short name T309
Test name
Test status
Simulation time 19850576 ps
CPU time 0.69 seconds
Started Jul 09 05:29:51 PM PDT 24
Finished Jul 09 05:29:52 PM PDT 24
Peak memory 206316 kb
Host smart-7bf9564c-e0e4-42d6-aebf-3d7e8371ebf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522570768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1522570768
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3868057520
Short name T635
Test name
Test status
Simulation time 168860739 ps
CPU time 5.22 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 233684 kb
Host smart-d1df517b-5020-4487-9af3-7093d82421dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868057520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3868057520
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1800111506
Short name T961
Test name
Test status
Simulation time 33062158 ps
CPU time 0.82 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 207492 kb
Host smart-80d0366f-cd89-4dbf-ad39-3bdd8d6ce013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800111506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1800111506
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1743468506
Short name T183
Test name
Test status
Simulation time 1046184493 ps
CPU time 13.52 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 225520 kb
Host smart-6501c8ef-5588-43e2-8812-8215b964af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743468506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1743468506
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.461345766
Short name T543
Test name
Test status
Simulation time 26935646307 ps
CPU time 221.25 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:33:25 PM PDT 24
Peak memory 250352 kb
Host smart-25fdd79c-ef2a-46fd-a640-e96e9d816368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461345766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.461345766
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.704036502
Short name T992
Test name
Test status
Simulation time 6756854965 ps
CPU time 20.58 seconds
Started Jul 09 05:29:53 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 242196 kb
Host smart-db839aae-ca2e-45e4-b8e9-711cacb8027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704036502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.704036502
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2952870385
Short name T583
Test name
Test status
Simulation time 1021586030 ps
CPU time 5.17 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 233792 kb
Host smart-ffac30d3-746f-4cb4-aa61-6f592f04bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952870385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2952870385
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3485868589
Short name T579
Test name
Test status
Simulation time 49688784 ps
CPU time 0.83 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 216828 kb
Host smart-9cceff53-a829-4dd4-b09d-2037675d03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485868589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3485868589
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.211913904
Short name T185
Test name
Test status
Simulation time 432078565 ps
CPU time 5.46 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:29:49 PM PDT 24
Peak memory 225376 kb
Host smart-892e1ff0-f340-4e11-8ec9-33d938eaf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211913904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.211913904
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3046608263
Short name T385
Test name
Test status
Simulation time 113026411 ps
CPU time 2.65 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 233508 kb
Host smart-3eaf39ed-26f3-4de3-b31e-21843156e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046608263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3046608263
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1171978565
Short name T500
Test name
Test status
Simulation time 199660291 ps
CPU time 2.25 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 225504 kb
Host smart-3f3e2128-be0a-4072-898e-27812f8d418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171978565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1171978565
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2560205720
Short name T244
Test name
Test status
Simulation time 11189076379 ps
CPU time 9.5 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:54 PM PDT 24
Peak memory 233832 kb
Host smart-9a165480-b997-446b-991e-c25b5f50d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560205720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2560205720
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2159254614
Short name T360
Test name
Test status
Simulation time 154647162 ps
CPU time 4.8 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:49 PM PDT 24
Peak memory 224164 kb
Host smart-bad7bdd9-f441-4f65-93d9-4c708d5981ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2159254614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2159254614
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4093230635
Short name T980
Test name
Test status
Simulation time 47524419683 ps
CPU time 383.91 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:36:19 PM PDT 24
Peak memory 268748 kb
Host smart-510a4784-ee98-4b4c-a72b-fffe7ca7f0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093230635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4093230635
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1431076567
Short name T881
Test name
Test status
Simulation time 19626910755 ps
CPU time 31.05 seconds
Started Jul 09 05:29:42 PM PDT 24
Finished Jul 09 05:30:14 PM PDT 24
Peak memory 217516 kb
Host smart-327742cb-82e1-48e6-af2b-7cfe3dc2c2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431076567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1431076567
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1328202439
Short name T743
Test name
Test status
Simulation time 31522664604 ps
CPU time 14.83 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 218676 kb
Host smart-1afe0bb1-d267-4a35-9f5f-4d9d382eae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328202439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1328202439
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3202149993
Short name T312
Test name
Test status
Simulation time 14244974 ps
CPU time 0.67 seconds
Started Jul 09 05:29:40 PM PDT 24
Finished Jul 09 05:29:43 PM PDT 24
Peak memory 206492 kb
Host smart-fa4415b2-483a-4d5e-ac45-7e81ff9d1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202149993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3202149993
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.930864551
Short name T594
Test name
Test status
Simulation time 24007154 ps
CPU time 0.84 seconds
Started Jul 09 05:29:43 PM PDT 24
Finished Jul 09 05:29:45 PM PDT 24
Peak memory 206904 kb
Host smart-0068d1a6-6d73-43e2-9fc9-6ec4da35bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930864551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.930864551
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2204751559
Short name T145
Test name
Test status
Simulation time 105356396 ps
CPU time 2.57 seconds
Started Jul 09 05:29:41 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 233712 kb
Host smart-812905af-e4bb-4401-9e0f-d7c77190936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204751559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2204751559
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.230111045
Short name T143
Test name
Test status
Simulation time 12830832 ps
CPU time 0.73 seconds
Started Jul 09 05:29:45 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 205680 kb
Host smart-d4c7593f-49e5-4d1f-a54c-1fe46fe52890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230111045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.230111045
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.859251711
Short name T631
Test name
Test status
Simulation time 3741989210 ps
CPU time 7.98 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 233792 kb
Host smart-b780e04f-795e-46be-87f2-d81baf4bee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859251711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.859251711
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1227892935
Short name T943
Test name
Test status
Simulation time 16039384 ps
CPU time 0.72 seconds
Started Jul 09 05:29:44 PM PDT 24
Finished Jul 09 05:29:46 PM PDT 24
Peak memory 206716 kb
Host smart-261990eb-b673-4b96-bdba-94022c42125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227892935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1227892935
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1732174993
Short name T516
Test name
Test status
Simulation time 22884914080 ps
CPU time 140.25 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:32:16 PM PDT 24
Peak memory 255520 kb
Host smart-866efb30-58b2-4f30-bf70-7596340de896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732174993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1732174993
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3681912665
Short name T834
Test name
Test status
Simulation time 20211932770 ps
CPU time 199.61 seconds
Started Jul 09 05:29:57 PM PDT 24
Finished Jul 09 05:33:18 PM PDT 24
Peak memory 250340 kb
Host smart-1d0833a9-fdef-4055-9f10-2afca2c0fa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681912665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3681912665
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3873109810
Short name T238
Test name
Test status
Simulation time 7656969316 ps
CPU time 113.08 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:31:48 PM PDT 24
Peak memory 265628 kb
Host smart-a08780c7-6024-4bcc-b786-3c112c25040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873109810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3873109810
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2092774376
Short name T661
Test name
Test status
Simulation time 1883528171 ps
CPU time 16.71 seconds
Started Jul 09 05:29:53 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 233724 kb
Host smart-68d4cec8-dc42-4e3f-8a4e-b7034ac0377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092774376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2092774376
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3090690528
Short name T595
Test name
Test status
Simulation time 15772603587 ps
CPU time 72.51 seconds
Started Jul 09 05:29:48 PM PDT 24
Finished Jul 09 05:31:01 PM PDT 24
Peak memory 252336 kb
Host smart-1f60b087-f2fc-4cec-9505-f0140436b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090690528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3090690528
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1341807370
Short name T860
Test name
Test status
Simulation time 3207083532 ps
CPU time 29.1 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 225584 kb
Host smart-c4e6994f-1042-406a-aba1-dbcfd8dcb010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341807370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1341807370
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3326467192
Short name T956
Test name
Test status
Simulation time 32739462827 ps
CPU time 70.67 seconds
Started Jul 09 05:29:45 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 233888 kb
Host smart-95daa918-2ebc-4af2-bf8a-20143d62a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326467192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3326467192
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2144017361
Short name T959
Test name
Test status
Simulation time 403222011 ps
CPU time 3.32 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 225512 kb
Host smart-6ef0e839-852f-4803-bde8-b6bf2539cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144017361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2144017361
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2166724582
Short name T691
Test name
Test status
Simulation time 45495478 ps
CPU time 2.16 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 225572 kb
Host smart-bb4b24ea-1203-43d2-80c3-f757a42be0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166724582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2166724582
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3078230690
Short name T749
Test name
Test status
Simulation time 625877641 ps
CPU time 4.2 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 222988 kb
Host smart-3a705e3b-63c9-4011-bf68-139c41c4410f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078230690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3078230690
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3731770747
Short name T21
Test name
Test status
Simulation time 48653246319 ps
CPU time 243.71 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:33:56 PM PDT 24
Peak memory 273128 kb
Host smart-33ccf246-1986-4a32-a454-e9efa780aa49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731770747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3731770747
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1778975494
Short name T283
Test name
Test status
Simulation time 8775893876 ps
CPU time 9.06 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 217372 kb
Host smart-72dd73ab-e9a7-4332-9558-95633d288f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778975494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1778975494
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.674160497
Short name T547
Test name
Test status
Simulation time 670165675 ps
CPU time 3.32 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 217252 kb
Host smart-ffac6e21-e316-4d6a-a648-ddfc34bfd150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674160497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.674160497
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2430967480
Short name T684
Test name
Test status
Simulation time 54405117 ps
CPU time 0.88 seconds
Started Jul 09 05:29:46 PM PDT 24
Finished Jul 09 05:29:47 PM PDT 24
Peak memory 207924 kb
Host smart-5cd5d6e8-e7b9-45ea-bcde-cba116caae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430967480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2430967480
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2949710107
Short name T396
Test name
Test status
Simulation time 73463877 ps
CPU time 0.93 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 206944 kb
Host smart-afdb3104-493b-48f8-9e62-eda708bc36d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949710107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2949710107
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.180642391
Short name T243
Test name
Test status
Simulation time 6015421934 ps
CPU time 7.22 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 242056 kb
Host smart-7ae82666-34b5-4653-94fb-bfcdaa763ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180642391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.180642391
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.248857013
Short name T884
Test name
Test status
Simulation time 17435056 ps
CPU time 0.8 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 205820 kb
Host smart-2061340b-6d23-446f-8cd4-e1ff19a1098b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248857013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.248857013
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2176059134
Short name T782
Test name
Test status
Simulation time 299099773 ps
CPU time 2.49 seconds
Started Jul 09 05:29:53 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 225528 kb
Host smart-e59885f7-2ed4-43f1-ab1d-d40b73e8a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176059134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2176059134
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3474605411
Short name T293
Test name
Test status
Simulation time 35033409 ps
CPU time 0.78 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 206500 kb
Host smart-db62bfb4-4c5d-41e2-8f76-417fa7becc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474605411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3474605411
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2135758867
Short name T438
Test name
Test status
Simulation time 14286782195 ps
CPU time 116.91 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:31:56 PM PDT 24
Peak memory 250308 kb
Host smart-ce44c0bd-6418-4388-bf4e-c07492aea176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135758867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2135758867
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.303044170
Short name T89
Test name
Test status
Simulation time 1818359853 ps
CPU time 15.02 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 233728 kb
Host smart-21e93a2a-06ee-4a03-8cf0-ef5e339dacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303044170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.303044170
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.577960491
Short name T926
Test name
Test status
Simulation time 59554600240 ps
CPU time 221.31 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:33:35 PM PDT 24
Peak memory 254924 kb
Host smart-58c73d10-82d5-4b83-b1a5-4d62136cac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577960491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.577960491
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2316057696
Short name T493
Test name
Test status
Simulation time 4259938945 ps
CPU time 8.35 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 225668 kb
Host smart-74114408-37ea-406d-b3c8-8b3383a8e0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316057696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2316057696
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2689118337
Short name T726
Test name
Test status
Simulation time 541513435 ps
CPU time 6.54 seconds
Started Jul 09 05:32:51 PM PDT 24
Finished Jul 09 05:32:59 PM PDT 24
Peak memory 225504 kb
Host smart-01191568-1e29-4a76-b006-fcaceea54562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689118337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2689118337
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.834518196
Short name T239
Test name
Test status
Simulation time 292696867 ps
CPU time 3.42 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 225540 kb
Host smart-01ffac8b-0092-4993-b992-118fc5b7dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834518196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.834518196
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1698306620
Short name T415
Test name
Test status
Simulation time 30584520 ps
CPU time 2.37 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 233504 kb
Host smart-f0a0941b-c1a2-40dc-84c6-9cd3c02a0811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698306620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1698306620
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1658120536
Short name T41
Test name
Test status
Simulation time 7181872535 ps
CPU time 14.96 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 224116 kb
Host smart-57707ef5-6193-4e56-a77f-6ab894d83b0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658120536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1658120536
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.517652913
Short name T149
Test name
Test status
Simulation time 139820930218 ps
CPU time 243.38 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:34:00 PM PDT 24
Peak memory 255344 kb
Host smart-4fb719e4-71ba-4213-9525-b579af8b0d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517652913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.517652913
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1678697403
Short name T851
Test name
Test status
Simulation time 6100908286 ps
CPU time 17.5 seconds
Started Jul 09 05:29:48 PM PDT 24
Finished Jul 09 05:30:06 PM PDT 24
Peak memory 217464 kb
Host smart-3b4002d2-b8ee-41f8-9751-8f2dff466888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678697403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1678697403
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2906161755
Short name T477
Test name
Test status
Simulation time 17215044 ps
CPU time 0.72 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:29:54 PM PDT 24
Peak memory 206552 kb
Host smart-16f18772-4431-44ff-b64d-ae20a9cfd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906161755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2906161755
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3627950189
Short name T719
Test name
Test status
Simulation time 57937246 ps
CPU time 0.96 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 207888 kb
Host smart-4de32808-1882-4f13-8ddc-069b134d5581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627950189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3627950189
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1979980470
Short name T670
Test name
Test status
Simulation time 65708349 ps
CPU time 0.76 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 206964 kb
Host smart-8cb69fac-990f-4bbe-8b62-8dd5cd25d612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979980470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1979980470
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1786374398
Short name T799
Test name
Test status
Simulation time 4078949764 ps
CPU time 21.09 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:21 PM PDT 24
Peak memory 233892 kb
Host smart-81b36d37-5571-415e-99d4-7f5d2a0eab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786374398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1786374398
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2115796515
Short name T599
Test name
Test status
Simulation time 16623218 ps
CPU time 0.75 seconds
Started Jul 09 05:29:57 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 206244 kb
Host smart-d34d8bd7-cd58-43d4-8ce8-ba7a71557ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115796515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2115796515
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1639744586
Short name T955
Test name
Test status
Simulation time 182686665 ps
CPU time 3.82 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 233580 kb
Host smart-20ec9483-17a7-491d-a983-4fb52ac17f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639744586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1639744586
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3598917979
Short name T773
Test name
Test status
Simulation time 38117523 ps
CPU time 0.83 seconds
Started Jul 09 05:29:48 PM PDT 24
Finished Jul 09 05:29:50 PM PDT 24
Peak memory 207448 kb
Host smart-86b05d71-13cc-45b9-b0c1-96394d884a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598917979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3598917979
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2440924737
Short name T960
Test name
Test status
Simulation time 10429836243 ps
CPU time 47.64 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 253544 kb
Host smart-f1238668-db77-4c51-8d4b-bf789bc0978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440924737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2440924737
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3200455967
Short name T248
Test name
Test status
Simulation time 91969729486 ps
CPU time 415.8 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:36:56 PM PDT 24
Peak memory 267344 kb
Host smart-28e09a38-6c2b-48c5-b288-666803d0416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200455967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3200455967
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2094608928
Short name T546
Test name
Test status
Simulation time 445214340 ps
CPU time 7.26 seconds
Started Jul 09 05:29:53 PM PDT 24
Finished Jul 09 05:30:01 PM PDT 24
Peak memory 233784 kb
Host smart-11036f5e-91c6-4d8e-84df-f531f7bf63e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094608928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2094608928
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2600550538
Short name T821
Test name
Test status
Simulation time 23056551896 ps
CPU time 51.61 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:30:44 PM PDT 24
Peak memory 239576 kb
Host smart-1005d719-4c6b-4791-a056-fdccd718d9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600550538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2600550538
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4043253936
Short name T206
Test name
Test status
Simulation time 308616476 ps
CPU time 3.23 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 233800 kb
Host smart-2471717d-0f3f-48bb-a140-5132df861d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043253936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4043253936
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1795164831
Short name T587
Test name
Test status
Simulation time 213703048 ps
CPU time 4.44 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 233708 kb
Host smart-8b707a79-1e09-4afe-ba35-c12cbb0344a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795164831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1795164831
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1933628510
Short name T916
Test name
Test status
Simulation time 8157305959 ps
CPU time 11.59 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 225732 kb
Host smart-9a0339dd-9dd0-42bf-9b03-a194ef77e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933628510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1933628510
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3039761265
Short name T513
Test name
Test status
Simulation time 10091399401 ps
CPU time 18.44 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:30:14 PM PDT 24
Peak memory 241768 kb
Host smart-fb7fc4a4-e305-4295-b4b7-11031a0c9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039761265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3039761265
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2852932385
Short name T911
Test name
Test status
Simulation time 222084508 ps
CPU time 3.59 seconds
Started Jul 09 05:32:26 PM PDT 24
Finished Jul 09 05:32:30 PM PDT 24
Peak memory 223704 kb
Host smart-75d5947b-954e-4f6d-981d-e2d8a291820f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2852932385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2852932385
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.182349769
Short name T8
Test name
Test status
Simulation time 7554864820 ps
CPU time 69.62 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:31:07 PM PDT 24
Peak memory 250432 kb
Host smart-30354c13-0c8d-4dd1-989a-af7953268a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182349769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.182349769
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3840978970
Short name T888
Test name
Test status
Simulation time 18282553 ps
CPU time 0.69 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 206640 kb
Host smart-fe70a7a1-bcae-41c0-8171-a567ed6b3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840978970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3840978970
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1806022139
Short name T806
Test name
Test status
Simulation time 3514234542 ps
CPU time 10.68 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 217268 kb
Host smart-6c954640-52f3-45fa-8471-62aad7f19590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806022139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1806022139
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2195736705
Short name T663
Test name
Test status
Simulation time 112131213 ps
CPU time 4.4 seconds
Started Jul 09 05:29:52 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 217300 kb
Host smart-ea801347-94a1-4aee-9008-90834bb9ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195736705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2195736705
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.410531049
Short name T75
Test name
Test status
Simulation time 26770426 ps
CPU time 0.8 seconds
Started Jul 09 05:30:03 PM PDT 24
Finished Jul 09 05:30:04 PM PDT 24
Peak memory 206540 kb
Host smart-6e39ad3e-3889-47f4-8940-633925812619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410531049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.410531049
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1130869136
Short name T554
Test name
Test status
Simulation time 182642449 ps
CPU time 3.5 seconds
Started Jul 09 05:30:54 PM PDT 24
Finished Jul 09 05:31:01 PM PDT 24
Peak memory 225488 kb
Host smart-897b32f5-79e2-42ff-921e-aeeed74f307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130869136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1130869136
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1014934900
Short name T65
Test name
Test status
Simulation time 23207815 ps
CPU time 0.76 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 206320 kb
Host smart-1a9899a0-9706-43c2-835f-aef4b9f5dbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014934900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1014934900
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4160247446
Short name T879
Test name
Test status
Simulation time 889179693 ps
CPU time 11.6 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 233724 kb
Host smart-22b8b841-7ea3-4a0f-9d9f-bab0cc34da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160247446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4160247446
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2676384339
Short name T356
Test name
Test status
Simulation time 15898453 ps
CPU time 0.76 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 206480 kb
Host smart-8a964815-c8f6-490e-9ff5-932b12232282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676384339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2676384339
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4055261564
Short name T82
Test name
Test status
Simulation time 35362343950 ps
CPU time 299.39 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:35:00 PM PDT 24
Peak memory 267536 kb
Host smart-3a3eb47f-f3b7-4020-8c32-663595745a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055261564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4055261564
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3932946778
Short name T230
Test name
Test status
Simulation time 22466918749 ps
CPU time 106.04 seconds
Started Jul 09 05:30:03 PM PDT 24
Finished Jul 09 05:31:50 PM PDT 24
Peak memory 253480 kb
Host smart-470243a1-75ad-4691-a87b-80ffe9ef3981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932946778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3932946778
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.606255042
Short name T511
Test name
Test status
Simulation time 222185661072 ps
CPU time 300.08 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:35:00 PM PDT 24
Peak memory 265184 kb
Host smart-6d0e46ac-5396-4641-b5b6-10d6debf0d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606255042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.606255042
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2153425044
Short name T556
Test name
Test status
Simulation time 1693880182 ps
CPU time 6.9 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:07 PM PDT 24
Peak memory 225456 kb
Host smart-668311b7-135d-44d6-8789-62abcd184ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153425044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2153425044
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1163743663
Short name T525
Test name
Test status
Simulation time 25630461317 ps
CPU time 170.84 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:32:48 PM PDT 24
Peak memory 250244 kb
Host smart-4c3ba346-9168-42a5-afb6-7e369754b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163743663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1163743663
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1760491031
Short name T754
Test name
Test status
Simulation time 3123877659 ps
CPU time 17.85 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 233880 kb
Host smart-e7f8e99c-2b98-4b82-926e-191912797d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760491031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1760491031
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3311376371
Short name T824
Test name
Test status
Simulation time 9544989033 ps
CPU time 54.14 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 234088 kb
Host smart-267d9c33-a3c8-4cc3-805f-e1df069204a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311376371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3311376371
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3264709655
Short name T241
Test name
Test status
Simulation time 4300271569 ps
CPU time 8.67 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 225684 kb
Host smart-b2c5153f-cd74-48a6-84d7-d9c1bfe3c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264709655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3264709655
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1928176122
Short name T224
Test name
Test status
Simulation time 1574902001 ps
CPU time 5.04 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 225600 kb
Host smart-d14a96d6-715a-46a1-9782-13185f917b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928176122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1928176122
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1439864637
Short name T1000
Test name
Test status
Simulation time 1222170504 ps
CPU time 18.93 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:30:16 PM PDT 24
Peak memory 220888 kb
Host smart-205b689f-d7c7-4629-be52-516e2d5f4d0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439864637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1439864637
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2530257093
Short name T644
Test name
Test status
Simulation time 47364385 ps
CPU time 1.03 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 207752 kb
Host smart-fd224e5d-e23c-414d-82a7-679b631a0803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530257093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2530257093
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3331042075
Short name T751
Test name
Test status
Simulation time 21108394870 ps
CPU time 14.24 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 217464 kb
Host smart-ba698cae-a658-4227-8a61-41bf749b3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331042075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3331042075
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2929258832
Short name T553
Test name
Test status
Simulation time 14565063362 ps
CPU time 15.38 seconds
Started Jul 09 05:29:56 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 217496 kb
Host smart-0989e3de-d2be-4105-ba56-60aba9dd544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929258832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2929258832
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2875857691
Short name T864
Test name
Test status
Simulation time 311498199 ps
CPU time 1.39 seconds
Started Jul 09 05:29:55 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 209200 kb
Host smart-ce45db53-9827-4719-96eb-ad15a4c3b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875857691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2875857691
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3205571308
Short name T581
Test name
Test status
Simulation time 103037347 ps
CPU time 0.87 seconds
Started Jul 09 05:29:54 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 207336 kb
Host smart-e6e07df6-8211-4fa5-8efc-866608d2d34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205571308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3205571308
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2772111548
Short name T479
Test name
Test status
Simulation time 3329082981 ps
CPU time 22.55 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 251964 kb
Host smart-24e146e2-31ed-4712-b238-c56087b0a5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772111548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2772111548
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.705750733
Short name T842
Test name
Test status
Simulation time 19377801 ps
CPU time 0.73 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 206712 kb
Host smart-355a2dcb-7c25-4b5c-8af4-0b6f043d336f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705750733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.705750733
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2980383362
Short name T947
Test name
Test status
Simulation time 449284815 ps
CPU time 7.59 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 225592 kb
Host smart-bc60ba40-9cdf-4126-9ed5-790b38add219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980383362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2980383362
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.582626113
Short name T419
Test name
Test status
Simulation time 43880670 ps
CPU time 0.75 seconds
Started Jul 09 05:29:57 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 207388 kb
Host smart-93563b85-efc4-4420-802f-d63d802f2cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582626113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.582626113
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1623963940
Short name T914
Test name
Test status
Simulation time 18106773143 ps
CPU time 61.14 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:31:08 PM PDT 24
Peak memory 225652 kb
Host smart-5a84b59d-6a94-45ae-8c42-e16c401c167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623963940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1623963940
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3313399534
Short name T256
Test name
Test status
Simulation time 74548688725 ps
CPU time 726.4 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 273996 kb
Host smart-865d0ba0-c6c5-489b-86d9-95c4ec444f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313399534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3313399534
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4178712159
Short name T181
Test name
Test status
Simulation time 88170038919 ps
CPU time 182.32 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:33:06 PM PDT 24
Peak memory 253260 kb
Host smart-ccc1b196-bd64-4aeb-82ad-af5e122c0b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178712159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4178712159
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2693704898
Short name T272
Test name
Test status
Simulation time 1799233567 ps
CPU time 10.71 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 225496 kb
Host smart-a37f8d38-67e1-408b-98a1-f402929de07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693704898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2693704898
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1748765672
Short name T37
Test name
Test status
Simulation time 1853253467 ps
CPU time 34.65 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 241936 kb
Host smart-ac7dc91f-d12f-428a-a9a1-61f851b84499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748765672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1748765672
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2905462313
Short name T308
Test name
Test status
Simulation time 193822079 ps
CPU time 2.52 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:05 PM PDT 24
Peak memory 233504 kb
Host smart-0dc62a3b-2ef7-4026-bb7a-7252ea78015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905462313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2905462313
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2667225948
Short name T528
Test name
Test status
Simulation time 166492691 ps
CPU time 2.42 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 233512 kb
Host smart-cce96fb8-1732-4aeb-92e9-a83474b5d296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667225948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2667225948
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.953535789
Short name T416
Test name
Test status
Simulation time 281077686 ps
CPU time 2.23 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 225312 kb
Host smart-e5eb5e65-dc87-45d2-ab97-e3599e9a95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953535789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.953535789
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1374201358
Short name T986
Test name
Test status
Simulation time 1016066131 ps
CPU time 3.37 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:30:05 PM PDT 24
Peak memory 225252 kb
Host smart-596d5b39-f3b5-458e-9ce5-757dc31236eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374201358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1374201358
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2636242167
Short name T527
Test name
Test status
Simulation time 4532325613 ps
CPU time 14.02 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 220764 kb
Host smart-52c42999-22af-41d4-946b-c66686b1065b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636242167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2636242167
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3960373510
Short name T1008
Test name
Test status
Simulation time 283997716 ps
CPU time 1.13 seconds
Started Jul 09 05:29:57 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 208184 kb
Host smart-4f92efae-ce71-4a18-b5c1-d19500e559f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960373510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3960373510
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1995250416
Short name T53
Test name
Test status
Simulation time 2440318607 ps
CPU time 6.6 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:07 PM PDT 24
Peak memory 217772 kb
Host smart-14d274f1-8966-4b9c-ae65-6abd48316d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995250416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1995250416
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.153569535
Short name T395
Test name
Test status
Simulation time 3774424810 ps
CPU time 6.27 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:05 PM PDT 24
Peak memory 217552 kb
Host smart-e91078d7-8c5e-40bd-82d4-8fabd7e1755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153569535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.153569535
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3866303669
Short name T778
Test name
Test status
Simulation time 334237984 ps
CPU time 1.9 seconds
Started Jul 09 05:29:58 PM PDT 24
Finished Jul 09 05:30:01 PM PDT 24
Peak memory 217340 kb
Host smart-d6c8f854-be5f-4486-b858-b3b301d164f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866303669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3866303669
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2796857443
Short name T948
Test name
Test status
Simulation time 19851570 ps
CPU time 0.73 seconds
Started Jul 09 05:29:57 PM PDT 24
Finished Jul 09 05:29:59 PM PDT 24
Peak memory 206848 kb
Host smart-f298fc84-da75-47e0-99b9-88c8b8d961a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796857443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2796857443
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3859217056
Short name T906
Test name
Test status
Simulation time 29693835960 ps
CPU time 24.22 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 233840 kb
Host smart-c4513605-815f-4c86-b034-92786f635bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859217056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3859217056
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.910645468
Short name T338
Test name
Test status
Simulation time 12303552 ps
CPU time 0.73 seconds
Started Jul 09 05:28:29 PM PDT 24
Finished Jul 09 05:28:30 PM PDT 24
Peak memory 205692 kb
Host smart-83ce403c-799d-423c-9ae2-e412b767a160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910645468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.910645468
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3919499782
Short name T1009
Test name
Test status
Simulation time 356366846 ps
CPU time 3.62 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:36 PM PDT 24
Peak memory 233776 kb
Host smart-0779c1db-7c01-4258-ae0c-5c3bea320453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919499782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3919499782
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3567970006
Short name T750
Test name
Test status
Simulation time 33660617 ps
CPU time 0.82 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:28:29 PM PDT 24
Peak memory 207476 kb
Host smart-f2a92b55-9073-4e78-addc-cd1bc34a45c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567970006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3567970006
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.21353574
Short name T760
Test name
Test status
Simulation time 314005516 ps
CPU time 7.06 seconds
Started Jul 09 05:28:30 PM PDT 24
Finished Jul 09 05:28:37 PM PDT 24
Peak memory 233796 kb
Host smart-60d0e9de-9eba-4201-bb9e-b186b51ca408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21353574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.21353574
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3037891979
Short name T210
Test name
Test status
Simulation time 10224338892 ps
CPU time 128.49 seconds
Started Jul 09 05:28:33 PM PDT 24
Finished Jul 09 05:30:42 PM PDT 24
Peak memory 253992 kb
Host smart-26f72c28-b2f3-4fb5-8fd2-10d4d3aa2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037891979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3037891979
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3869184540
Short name T170
Test name
Test status
Simulation time 14707322225 ps
CPU time 192.78 seconds
Started Jul 09 05:28:21 PM PDT 24
Finished Jul 09 05:31:34 PM PDT 24
Peak memory 256932 kb
Host smart-1f0b2917-b114-4be7-8721-cb47bacfb404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869184540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3869184540
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1597826991
Short name T1019
Test name
Test status
Simulation time 111591813 ps
CPU time 4.79 seconds
Started Jul 09 05:28:30 PM PDT 24
Finished Jul 09 05:28:35 PM PDT 24
Peak memory 224068 kb
Host smart-9d40369e-7e92-4efd-9440-a236ac7b1aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597826991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1597826991
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1733996251
Short name T1001
Test name
Test status
Simulation time 25036585912 ps
CPU time 177.01 seconds
Started Jul 09 05:28:28 PM PDT 24
Finished Jul 09 05:31:25 PM PDT 24
Peak memory 250920 kb
Host smart-f4f1fae3-05c4-432b-a6bb-534f1fd2633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733996251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1733996251
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.377861463
Short name T655
Test name
Test status
Simulation time 741923560 ps
CPU time 4.25 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:29 PM PDT 24
Peak memory 225444 kb
Host smart-c15161a8-5504-42ed-80bc-509068c71b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377861463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.377861463
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2006722339
Short name T923
Test name
Test status
Simulation time 3333957364 ps
CPU time 34.43 seconds
Started Jul 09 05:28:20 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 252936 kb
Host smart-fbca7940-6342-434e-b64c-0531bd8647e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006722339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2006722339
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1669264689
Short name T949
Test name
Test status
Simulation time 137991323 ps
CPU time 1.09 seconds
Started Jul 09 05:28:25 PM PDT 24
Finished Jul 09 05:28:27 PM PDT 24
Peak memory 217668 kb
Host smart-3c99d03c-f631-4455-9e49-a941f94d8cab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669264689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1669264689
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2714282771
Short name T436
Test name
Test status
Simulation time 1083389413 ps
CPU time 5.25 seconds
Started Jul 09 05:28:22 PM PDT 24
Finished Jul 09 05:28:28 PM PDT 24
Peak memory 233772 kb
Host smart-473fc412-740c-4907-a554-3d57acff945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714282771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2714282771
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3913169488
Short name T814
Test name
Test status
Simulation time 117250483 ps
CPU time 2.26 seconds
Started Jul 09 05:28:18 PM PDT 24
Finished Jul 09 05:28:21 PM PDT 24
Peak memory 233536 kb
Host smart-c58bc961-67e1-4e3b-8bf1-e166d2a08324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913169488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3913169488
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.214157101
Short name T142
Test name
Test status
Simulation time 601097761 ps
CPU time 10.27 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:28:37 PM PDT 24
Peak memory 221244 kb
Host smart-29858081-60a8-44f1-b5f2-14f35fcf264b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214157101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.214157101
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.211781271
Short name T71
Test name
Test status
Simulation time 86477520 ps
CPU time 1.25 seconds
Started Jul 09 05:28:30 PM PDT 24
Finished Jul 09 05:28:32 PM PDT 24
Peak memory 237756 kb
Host smart-ad562230-f3d4-469e-8b03-226e9d730d9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211781271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.211781271
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1912415353
Short name T220
Test name
Test status
Simulation time 104020344994 ps
CPU time 134.32 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 250380 kb
Host smart-eed7dd47-e84c-41e0-bd66-ec3c34499e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912415353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1912415353
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1646460168
Short name T557
Test name
Test status
Simulation time 18052287381 ps
CPU time 25.12 seconds
Started Jul 09 05:28:21 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 217496 kb
Host smart-ec84e424-f180-4b4c-90fa-c8614dca089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646460168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1646460168
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4142062356
Short name T461
Test name
Test status
Simulation time 567357862 ps
CPU time 2.87 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:27 PM PDT 24
Peak memory 217312 kb
Host smart-b877cf3f-a358-4a85-b479-b8991dbf6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142062356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4142062356
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4204560024
Short name T835
Test name
Test status
Simulation time 459414790 ps
CPU time 6.65 seconds
Started Jul 09 05:28:19 PM PDT 24
Finished Jul 09 05:28:26 PM PDT 24
Peak memory 217316 kb
Host smart-8afd1eb8-f7ae-4d75-8226-929a1cd750b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204560024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4204560024
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1793438647
Short name T772
Test name
Test status
Simulation time 38190393 ps
CPU time 0.82 seconds
Started Jul 09 05:28:22 PM PDT 24
Finished Jul 09 05:28:23 PM PDT 24
Peak memory 206964 kb
Host smart-a84b3f5f-56bd-48cf-a896-e802f6d1db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793438647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1793438647
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1782998341
Short name T207
Test name
Test status
Simulation time 1048765809 ps
CPU time 10.57 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:35 PM PDT 24
Peak memory 241628 kb
Host smart-e0c2e540-1dd6-464a-91de-9585883e15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782998341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1782998341
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2187081001
Short name T958
Test name
Test status
Simulation time 15695948 ps
CPU time 0.77 seconds
Started Jul 09 05:30:03 PM PDT 24
Finished Jul 09 05:30:04 PM PDT 24
Peak memory 206624 kb
Host smart-9cb5bd9a-34cf-4ad1-bd6e-986c20ee5ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187081001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2187081001
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1553086062
Short name T858
Test name
Test status
Simulation time 67471004 ps
CPU time 2.65 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 233716 kb
Host smart-f74b5b1b-11c1-44a3-a7b2-436e63d60793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553086062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1553086062
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3914059937
Short name T504
Test name
Test status
Simulation time 282257426 ps
CPU time 0.78 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:02 PM PDT 24
Peak memory 207820 kb
Host smart-33b07ccf-ce77-4caa-a74c-6ff79ba9e135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914059937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3914059937
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2646352424
Short name T999
Test name
Test status
Simulation time 2570453691 ps
CPU time 11.59 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 236452 kb
Host smart-94ee190d-bd0b-474d-a8b3-850d779b4d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646352424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2646352424
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3362200946
Short name T748
Test name
Test status
Simulation time 2676268139 ps
CPU time 66.03 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:31:16 PM PDT 24
Peak memory 252368 kb
Host smart-4e6a47c9-32c1-45a1-abba-2e8dc72e40ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362200946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3362200946
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3813021583
Short name T194
Test name
Test status
Simulation time 62061728131 ps
CPU time 170.03 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:33:00 PM PDT 24
Peak memory 270540 kb
Host smart-315a46a2-e1c1-4726-ac79-f9848ac92e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813021583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3813021583
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1414339965
Short name T995
Test name
Test status
Simulation time 11848948150 ps
CPU time 28.36 seconds
Started Jul 09 05:30:04 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 253944 kb
Host smart-b9c439d4-cadf-465e-9236-c2701be08395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414339965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1414339965
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2684013797
Short name T668
Test name
Test status
Simulation time 12381961381 ps
CPU time 17.13 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 238044 kb
Host smart-a712158a-1988-4b45-b73c-db6c3ac8b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684013797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2684013797
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3586539903
Short name T801
Test name
Test status
Simulation time 677025870 ps
CPU time 8.77 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 233796 kb
Host smart-e35153bb-f238-443e-8a41-49bca80165d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586539903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3586539903
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3805597565
Short name T227
Test name
Test status
Simulation time 28559762797 ps
CPU time 107.16 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:31:53 PM PDT 24
Peak memory 233804 kb
Host smart-8b8cc893-6d49-4270-9c4f-3d908f7edf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805597565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3805597565
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1257201970
Short name T10
Test name
Test status
Simulation time 541198873 ps
CPU time 4.43 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:06 PM PDT 24
Peak memory 225396 kb
Host smart-1c669406-6818-4a15-a88f-c59b0b915bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257201970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1257201970
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3207741090
Short name T195
Test name
Test status
Simulation time 4158986171 ps
CPU time 8.1 seconds
Started Jul 09 05:30:00 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 225676 kb
Host smart-17ba9596-bf32-4ea2-a131-b28002fa204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207741090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3207741090
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2373232209
Short name T737
Test name
Test status
Simulation time 424785363 ps
CPU time 4.03 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:14 PM PDT 24
Peak memory 224164 kb
Host smart-9cf1a1e9-091b-4f31-adee-c3444496dee9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2373232209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2373232209
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1189203525
Short name T169
Test name
Test status
Simulation time 22657648797 ps
CPU time 260.25 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:34:28 PM PDT 24
Peak memory 270052 kb
Host smart-f7093f2f-bebd-4bbf-b0ac-2bbbfaa9b6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189203525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1189203525
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.246349509
Short name T290
Test name
Test status
Simulation time 1928825679 ps
CPU time 30.02 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 217316 kb
Host smart-37cc6392-8a66-4ed8-9c02-644d9bd7c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246349509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.246349509
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3032143176
Short name T742
Test name
Test status
Simulation time 4837544946 ps
CPU time 13.5 seconds
Started Jul 09 05:29:59 PM PDT 24
Finished Jul 09 05:30:14 PM PDT 24
Peak memory 217512 kb
Host smart-e117c83a-5149-4671-ba9b-3400d5a17609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032143176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3032143176
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2039871814
Short name T532
Test name
Test status
Simulation time 48345719 ps
CPU time 0.81 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:03 PM PDT 24
Peak memory 206928 kb
Host smart-062207df-2ab8-40dd-a6bd-b326553019bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039871814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2039871814
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1465700365
Short name T1012
Test name
Test status
Simulation time 59415983 ps
CPU time 0.69 seconds
Started Jul 09 05:30:04 PM PDT 24
Finished Jul 09 05:30:05 PM PDT 24
Peak memory 206572 kb
Host smart-a1eecb18-5198-4ffd-9f04-70bc2361915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465700365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1465700365
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2251616141
Short name T367
Test name
Test status
Simulation time 6714847947 ps
CPU time 15.47 seconds
Started Jul 09 05:30:03 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 233916 kb
Host smart-a9d828f4-e5f0-487d-b9f6-f03ea0f7d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251616141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2251616141
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3912877334
Short name T487
Test name
Test status
Simulation time 59445807 ps
CPU time 0.76 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 206380 kb
Host smart-21005c26-43fd-4ca5-ad9c-b363db927bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912877334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3912877334
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2220260247
Short name T660
Test name
Test status
Simulation time 286445215 ps
CPU time 2.81 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 225468 kb
Host smart-9b8859c5-2300-4bb5-bc9b-f14fbb735d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220260247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2220260247
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2624145333
Short name T13
Test name
Test status
Simulation time 60254328 ps
CPU time 0.78 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 207788 kb
Host smart-c3dc1804-3ca7-49ab-9dad-989f2d673cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624145333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2624145333
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2125283767
Short name T345
Test name
Test status
Simulation time 19386545443 ps
CPU time 75.35 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:31:23 PM PDT 24
Peak memory 252748 kb
Host smart-bbe8955c-a02b-443e-bb19-bd5d72de83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125283767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2125283767
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1187991154
Short name T722
Test name
Test status
Simulation time 31583989276 ps
CPU time 41.87 seconds
Started Jul 09 05:30:14 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 218672 kb
Host smart-7b9f41ba-f1a8-4960-96d8-41273502eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187991154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1187991154
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3002004106
Short name T685
Test name
Test status
Simulation time 30578195505 ps
CPU time 204.02 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:33:32 PM PDT 24
Peak memory 257880 kb
Host smart-3c3fc596-fff6-44fc-ae1a-4ddbfa3fa264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002004106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3002004106
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3719289884
Short name T731
Test name
Test status
Simulation time 246892364 ps
CPU time 3.73 seconds
Started Jul 09 05:30:03 PM PDT 24
Finished Jul 09 05:30:08 PM PDT 24
Peak memory 225588 kb
Host smart-324841cf-98a6-45ce-a8d9-83076db7b2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719289884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3719289884
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4017921532
Short name T846
Test name
Test status
Simulation time 39370983678 ps
CPU time 26 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 233884 kb
Host smart-88c3e7b6-e2fc-4bfa-875b-e9e34a228f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017921532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4017921532
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1671730098
Short name T639
Test name
Test status
Simulation time 3092858135 ps
CPU time 10.23 seconds
Started Jul 09 05:30:01 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 236924 kb
Host smart-27ebbfa9-ac13-4492-a222-f8dc13f7c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671730098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1671730098
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1832247682
Short name T678
Test name
Test status
Simulation time 1023654928 ps
CPU time 7.89 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 225572 kb
Host smart-7c85b663-60c3-4fbf-954e-13233a06e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832247682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1832247682
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.543200599
Short name T465
Test name
Test status
Simulation time 3050786955 ps
CPU time 9.05 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 219852 kb
Host smart-beabf391-12cf-41c8-b8ff-78523fee135e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=543200599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.543200599
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2702065389
Short name T261
Test name
Test status
Simulation time 18941880756 ps
CPU time 308.84 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:35:17 PM PDT 24
Peak memory 271024 kb
Host smart-9c94b6cb-590a-42e0-a88f-545ab362dfa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702065389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2702065389
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2121063864
Short name T391
Test name
Test status
Simulation time 480547232 ps
CPU time 6.07 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:14 PM PDT 24
Peak memory 217496 kb
Host smart-468cb33e-38ec-4f09-9cf9-cebc09f50446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121063864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2121063864
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.66376943
Short name T481
Test name
Test status
Simulation time 1631465239 ps
CPU time 4.79 seconds
Started Jul 09 05:30:04 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 217280 kb
Host smart-9047c429-f060-47f7-ba1e-ab4304b0c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66376943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.66376943
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.419474931
Short name T299
Test name
Test status
Simulation time 10700640 ps
CPU time 0.66 seconds
Started Jul 09 05:30:14 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 206476 kb
Host smart-e27b70d4-400f-4300-8cdb-0fcaedcb3209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419474931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.419474931
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2642262451
Short name T27
Test name
Test status
Simulation time 45045092 ps
CPU time 0.84 seconds
Started Jul 09 05:30:02 PM PDT 24
Finished Jul 09 05:30:04 PM PDT 24
Peak memory 206976 kb
Host smart-15581634-3b7f-4c72-90e2-2a16cf7f97bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642262451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2642262451
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.482855004
Short name T491
Test name
Test status
Simulation time 814670303 ps
CPU time 5.1 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 225528 kb
Host smart-732d9ef4-1e32-4f75-aa27-ab070984e92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482855004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.482855004
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3720139667
Short name T446
Test name
Test status
Simulation time 99297473 ps
CPU time 0.67 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 205668 kb
Host smart-fa1b5ce4-6242-4de3-bb12-82e97c00448b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720139667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3720139667
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.246907309
Short name T988
Test name
Test status
Simulation time 2885116502 ps
CPU time 10.27 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:19 PM PDT 24
Peak memory 225656 kb
Host smart-ae201b45-bc17-4b2c-bdc8-ff7a052f0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246907309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.246907309
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.414718922
Short name T637
Test name
Test status
Simulation time 19598784 ps
CPU time 0.79 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:09 PM PDT 24
Peak memory 207476 kb
Host smart-0c12ab5d-46eb-4e9c-b2c6-886665fc9a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414718922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.414718922
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1676747301
Short name T568
Test name
Test status
Simulation time 87304296049 ps
CPU time 57.51 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:31:06 PM PDT 24
Peak memory 250224 kb
Host smart-c76c3d2a-0798-4ee0-b01d-034ce925e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676747301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1676747301
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.30697859
Short name T669
Test name
Test status
Simulation time 29618032197 ps
CPU time 121.14 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:32:11 PM PDT 24
Peak memory 268356 kb
Host smart-093b623f-c5be-4f41-8691-2334a9db6f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30697859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.30697859
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2000822822
Short name T405
Test name
Test status
Simulation time 6315440462 ps
CPU time 20.19 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 234520 kb
Host smart-02c16942-efee-4f24-af4e-b9af881e7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000822822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2000822822
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3623469701
Short name T40
Test name
Test status
Simulation time 1656943735 ps
CPU time 25.18 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 225576 kb
Host smart-4d0056d5-049a-4e15-b821-ab32981c65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623469701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3623469701
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1899982199
Short name T552
Test name
Test status
Simulation time 177196301 ps
CPU time 4.79 seconds
Started Jul 09 05:30:05 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 233776 kb
Host smart-9b3e69fb-9642-4053-a974-4a68708ec666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899982199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1899982199
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4032982709
Short name T774
Test name
Test status
Simulation time 559259463 ps
CPU time 9.42 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 233708 kb
Host smart-71ea2ed3-9924-42d4-9e43-556ec15aa889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032982709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4032982709
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3433375593
Short name T1006
Test name
Test status
Simulation time 345021061 ps
CPU time 2.53 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 225460 kb
Host smart-91edb778-bc4e-4497-a7fa-f3c72d9e6d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433375593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3433375593
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.939155385
Short name T310
Test name
Test status
Simulation time 4363064494 ps
CPU time 8.25 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 225576 kb
Host smart-ec426fb2-9f50-425e-9dc3-bdeb9f5e1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939155385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.939155385
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.722580066
Short name T57
Test name
Test status
Simulation time 230898211 ps
CPU time 5.06 seconds
Started Jul 09 05:30:05 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 224040 kb
Host smart-b4067255-78ba-4294-942e-8b305d21e7e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=722580066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.722580066
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2308126869
Short name T573
Test name
Test status
Simulation time 6070047773 ps
CPU time 38.86 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 217476 kb
Host smart-a397cd46-8960-4ea7-81ed-0d21ba0f47fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308126869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2308126869
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2460700866
Short name T600
Test name
Test status
Simulation time 8695523918 ps
CPU time 7.2 seconds
Started Jul 09 05:30:07 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 217412 kb
Host smart-2a05e916-7d60-4c2e-987c-cea6ab060ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460700866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2460700866
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.614073372
Short name T744
Test name
Test status
Simulation time 330364688 ps
CPU time 1.87 seconds
Started Jul 09 05:30:06 PM PDT 24
Finished Jul 09 05:30:08 PM PDT 24
Peak memory 217308 kb
Host smart-0918a2c3-538f-4fcf-ad0c-669b8a884ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614073372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.614073372
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1878630788
Short name T392
Test name
Test status
Simulation time 55164452 ps
CPU time 0.89 seconds
Started Jul 09 05:30:05 PM PDT 24
Finished Jul 09 05:30:07 PM PDT 24
Peak memory 206948 kb
Host smart-086a13a1-404b-44c5-9c62-3b1938c1b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878630788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1878630788
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1846199721
Short name T95
Test name
Test status
Simulation time 8267856028 ps
CPU time 22.97 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 233892 kb
Host smart-096a3d8e-97d9-492c-b7e6-48ea346349b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846199721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1846199721
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.637898052
Short name T917
Test name
Test status
Simulation time 15772657 ps
CPU time 0.71 seconds
Started Jul 09 05:30:11 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 206404 kb
Host smart-95a03b6b-d6a9-4f04-a74a-b377144d0096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637898052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.637898052
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2944581371
Short name T658
Test name
Test status
Simulation time 5014015263 ps
CPU time 15.52 seconds
Started Jul 09 05:30:12 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 225664 kb
Host smart-80453fb3-31b9-457c-aec0-c3721efaa62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944581371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2944581371
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1391547717
Short name T442
Test name
Test status
Simulation time 17370530 ps
CPU time 0.79 seconds
Started Jul 09 05:30:11 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 207540 kb
Host smart-81c9c9a2-0790-4f59-8a13-10c121d9f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391547717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1391547717
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1227282156
Short name T614
Test name
Test status
Simulation time 4514939761 ps
CPU time 39.4 seconds
Started Jul 09 05:30:08 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 241952 kb
Host smart-9c35592f-dbc3-4357-bb38-12c92e94153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227282156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1227282156
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3411770525
Short name T831
Test name
Test status
Simulation time 32681048332 ps
CPU time 366.47 seconds
Started Jul 09 05:30:11 PM PDT 24
Finished Jul 09 05:36:18 PM PDT 24
Peak memory 253680 kb
Host smart-cc27de27-6a71-4f78-82b5-ca601e4c608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411770525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3411770525
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3104755982
Short name T1011
Test name
Test status
Simulation time 13050926504 ps
CPU time 108.11 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:32:00 PM PDT 24
Peak memory 249620 kb
Host smart-339ce541-8ebc-4231-8618-600c87fcee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104755982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3104755982
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1440889572
Short name T270
Test name
Test status
Simulation time 2255788281 ps
CPU time 21.89 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 238204 kb
Host smart-7be4c611-6ac3-48ba-8d5a-3143bf8fb9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440889572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1440889572
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.116697488
Short name T971
Test name
Test status
Simulation time 16507352 ps
CPU time 0.78 seconds
Started Jul 09 05:30:12 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 216928 kb
Host smart-0c2a5fc6-911c-4139-b8bc-600c0618509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116697488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.116697488
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2666443255
Short name T792
Test name
Test status
Simulation time 226636725 ps
CPU time 5.08 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:16 PM PDT 24
Peak memory 233804 kb
Host smart-cc387878-fc9e-4ea5-a3ed-fbed99a4f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666443255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2666443255
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2837328162
Short name T839
Test name
Test status
Simulation time 1638706552 ps
CPU time 13.13 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 241708 kb
Host smart-5a358178-4b0c-441f-98f6-bd69e868181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837328162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2837328162
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.488905142
Short name T761
Test name
Test status
Simulation time 687511664 ps
CPU time 4.84 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 225620 kb
Host smart-fb52bc79-cf2a-4963-b07d-7c3bca0e45a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488905142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.488905142
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2938293869
Short name T429
Test name
Test status
Simulation time 4375046234 ps
CPU time 5.1 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 233876 kb
Host smart-da4e7af1-66a6-431e-9836-1d0993fe2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938293869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2938293869
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1107754125
Short name T161
Test name
Test status
Simulation time 609240543 ps
CPU time 9.87 seconds
Started Jul 09 05:30:16 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 223020 kb
Host smart-1ebbaed2-5e72-4969-af64-3b9beaa902c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1107754125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1107754125
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4226123751
Short name T389
Test name
Test status
Simulation time 45999401 ps
CPU time 1.08 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 208064 kb
Host smart-34ef491b-e17e-4030-bc9f-1235a82dbdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226123751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4226123751
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4089325621
Short name T545
Test name
Test status
Simulation time 2934859175 ps
CPU time 3.27 seconds
Started Jul 09 05:30:15 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 217464 kb
Host smart-47e01a2c-c285-4980-b4f0-94449318ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089325621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4089325621
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.195576901
Short name T302
Test name
Test status
Simulation time 35968267768 ps
CPU time 12.87 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 217484 kb
Host smart-a04c4803-c091-4965-b65f-f0e6a28e5bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195576901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.195576901
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3939689470
Short name T325
Test name
Test status
Simulation time 140664469 ps
CPU time 0.97 seconds
Started Jul 09 05:30:15 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 207984 kb
Host smart-389241df-c120-4d13-81f7-adb61bccf2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939689470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3939689470
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3850839505
Short name T946
Test name
Test status
Simulation time 157526855 ps
CPU time 1 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:30:12 PM PDT 24
Peak memory 206944 kb
Host smart-5e4b5021-660a-4041-91c9-6c8980f94ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850839505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3850839505
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2921468404
Short name T752
Test name
Test status
Simulation time 7863822637 ps
CPU time 31.65 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:43 PM PDT 24
Peak memory 242012 kb
Host smart-11f18592-f360-44c8-bd7d-600760d10e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921468404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2921468404
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1194025780
Short name T654
Test name
Test status
Simulation time 21601426 ps
CPU time 0.7 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 206356 kb
Host smart-9f6b260b-2b7d-43c5-a5c0-6cc162269e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194025780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1194025780
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1846154688
Short name T74
Test name
Test status
Simulation time 2043996861 ps
CPU time 5.79 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 233684 kb
Host smart-d00b9bd5-0dce-4ab5-885a-88f3a0667576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846154688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1846154688
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2366604926
Short name T327
Test name
Test status
Simulation time 98947880 ps
CPU time 0.79 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 207840 kb
Host smart-c651df74-0a79-4546-af8f-64669c74df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366604926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2366604926
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2582276438
Short name T77
Test name
Test status
Simulation time 3566223001 ps
CPU time 25.6 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 254000 kb
Host smart-8f2dcecf-d2d7-4ffe-9762-c19e8204319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582276438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2582276438
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.758084316
Short name T771
Test name
Test status
Simulation time 66470242049 ps
CPU time 144.39 seconds
Started Jul 09 05:30:14 PM PDT 24
Finished Jul 09 05:32:39 PM PDT 24
Peak memory 255376 kb
Host smart-2a1f4f44-d441-4d7b-91c5-899f9b84a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758084316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.758084316
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2422286679
Short name T690
Test name
Test status
Simulation time 42159356211 ps
CPU time 370.31 seconds
Started Jul 09 05:30:14 PM PDT 24
Finished Jul 09 05:36:30 PM PDT 24
Peak memory 266176 kb
Host smart-d6296cfa-e00c-4126-9638-cc8919ef603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422286679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2422286679
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1753783894
Short name T647
Test name
Test status
Simulation time 1794582386 ps
CPU time 4.43 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 225544 kb
Host smart-7e20f179-0bef-41bf-b61c-3303dcf2f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753783894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1753783894
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3815425987
Short name T796
Test name
Test status
Simulation time 2293886128 ps
CPU time 31.04 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:42 PM PDT 24
Peak memory 254780 kb
Host smart-7bd8e76a-cbd7-4114-b475-326dbeece1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815425987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3815425987
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1963636199
Short name T455
Test name
Test status
Simulation time 2816384825 ps
CPU time 9.97 seconds
Started Jul 09 05:30:15 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 233880 kb
Host smart-3ffccf7e-b9d8-48e4-ab18-2f9939ddbe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963636199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1963636199
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2030018626
Short name T820
Test name
Test status
Simulation time 3855361864 ps
CPU time 39.98 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 241484 kb
Host smart-4489317e-20b3-4c10-936c-d7080c7fdcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030018626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2030018626
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.371885919
Short name T548
Test name
Test status
Simulation time 398858693 ps
CPU time 3.22 seconds
Started Jul 09 05:30:16 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 233660 kb
Host smart-09a6d7ba-5928-4872-91e9-a4a4c812a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371885919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.371885919
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.490851411
Short name T677
Test name
Test status
Simulation time 7346003793 ps
CPU time 14.28 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 233820 kb
Host smart-62a5e48d-4d35-4c10-bd12-fb50504d3edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490851411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.490851411
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.185073379
Short name T551
Test name
Test status
Simulation time 529179544 ps
CPU time 6.49 seconds
Started Jul 09 05:30:15 PM PDT 24
Finished Jul 09 05:30:22 PM PDT 24
Peak memory 221560 kb
Host smart-6ed3f71b-40a5-40ce-a3e2-a8da605bfacc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=185073379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.185073379
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4143960415
Short name T166
Test name
Test status
Simulation time 139742581 ps
CPU time 1.03 seconds
Started Jul 09 05:30:14 PM PDT 24
Finished Jul 09 05:30:16 PM PDT 24
Peak memory 207764 kb
Host smart-54f4fdf7-3fe3-4df9-9cd5-68651fc8b7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143960415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4143960415
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.848324090
Short name T626
Test name
Test status
Simulation time 1213159844 ps
CPU time 2.94 seconds
Started Jul 09 05:30:15 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 219608 kb
Host smart-6eeddfcb-620e-4389-bc9a-2adbe6b52d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848324090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.848324090
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3800403449
Short name T300
Test name
Test status
Simulation time 20401452430 ps
CPU time 16.02 seconds
Started Jul 09 05:30:10 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 217452 kb
Host smart-a21cf263-356e-4710-abf8-99f6036fc134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800403449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3800403449
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2848780752
Short name T679
Test name
Test status
Simulation time 88197892 ps
CPU time 2.36 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 217396 kb
Host smart-62a04898-8f3c-4dac-b607-3a1031188fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848780752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2848780752
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1689281237
Short name T485
Test name
Test status
Simulation time 46048893 ps
CPU time 0.87 seconds
Started Jul 09 05:30:09 PM PDT 24
Finished Jul 09 05:30:11 PM PDT 24
Peak memory 207964 kb
Host smart-da86e146-bfd2-434c-8091-d1c38d187e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689281237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1689281237
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2197821539
Short name T544
Test name
Test status
Simulation time 249680404 ps
CPU time 2.99 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:17 PM PDT 24
Peak memory 233752 kb
Host smart-9cc6e922-27fb-4563-9985-e33941e6830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197821539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2197821539
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4233090688
Short name T323
Test name
Test status
Simulation time 27747612 ps
CPU time 0.73 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:22 PM PDT 24
Peak memory 206352 kb
Host smart-00610d32-4dfe-4162-a64c-410525d9f54b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233090688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4233090688
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2049121207
Short name T428
Test name
Test status
Simulation time 37064259 ps
CPU time 2.52 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 233384 kb
Host smart-af5152e5-7e1f-4e2d-ab16-5fa52b2d4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049121207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2049121207
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2414399552
Short name T146
Test name
Test status
Simulation time 43764693 ps
CPU time 0.78 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 206456 kb
Host smart-b2140c66-7b66-493d-b790-a5c861bb13cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414399552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2414399552
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4286014772
Short name T550
Test name
Test status
Simulation time 20887625901 ps
CPU time 41.92 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:31:09 PM PDT 24
Peak memory 251348 kb
Host smart-24f3fffa-866b-4fa3-8708-ff7ee7c90f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286014772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4286014772
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3200000586
Short name T904
Test name
Test status
Simulation time 14421048694 ps
CPU time 115.44 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:32:18 PM PDT 24
Peak memory 244732 kb
Host smart-3f7c1358-e040-40e9-bc70-4d666c057c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200000586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3200000586
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4214796785
Short name T76
Test name
Test status
Simulation time 32373006522 ps
CPU time 303.93 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:35:31 PM PDT 24
Peak memory 253428 kb
Host smart-ed1355a7-9006-44ac-b3e3-873ba6047ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214796785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4214796785
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2327722515
Short name T662
Test name
Test status
Simulation time 1407889783 ps
CPU time 17.62 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:35 PM PDT 24
Peak memory 238508 kb
Host smart-a33c5497-0692-4d22-aec3-452d78283b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327722515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2327722515
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.872086263
Short name T231
Test name
Test status
Simulation time 537558896 ps
CPU time 6.06 seconds
Started Jul 09 05:30:26 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 225464 kb
Host smart-aac82348-ca6c-43cf-ace7-9e37719e30a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872086263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.872086263
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3381304430
Short name T825
Test name
Test status
Simulation time 4477945595 ps
CPU time 31.37 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 239308 kb
Host smart-e043e947-cd71-4f07-b22d-9a26c0d663ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381304430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3381304430
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2559876995
Short name T561
Test name
Test status
Simulation time 11942737073 ps
CPU time 17.87 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 225720 kb
Host smart-fb8c0cf9-1153-4fc9-b27c-ee1fcd86fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559876995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2559876995
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.805122833
Short name T467
Test name
Test status
Simulation time 2949811743 ps
CPU time 8.8 seconds
Started Jul 09 05:30:16 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 233784 kb
Host smart-ff77a7ae-bf56-4128-95e7-3387ae737826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805122833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.805122833
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2259501184
Short name T903
Test name
Test status
Simulation time 461099897 ps
CPU time 3.69 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 221128 kb
Host smart-04bec279-cd6b-4077-b6f5-fe96d94e957d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259501184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2259501184
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4059936217
Short name T151
Test name
Test status
Simulation time 4980337045 ps
CPU time 60.12 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:31:14 PM PDT 24
Peak memory 258028 kb
Host smart-71be1ce0-9eaf-4e7b-8fef-5ab02437a2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059936217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4059936217
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.826257846
Short name T721
Test name
Test status
Simulation time 6376201181 ps
CPU time 29.51 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 217484 kb
Host smart-62f8594d-8638-43e2-9062-0c67efcafbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826257846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.826257846
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.503299276
Short name T787
Test name
Test status
Simulation time 12262504964 ps
CPU time 15.72 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 217344 kb
Host smart-498f20ca-8436-42f9-babd-e96259890b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503299276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.503299276
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.484674517
Short name T852
Test name
Test status
Simulation time 911261581 ps
CPU time 1.89 seconds
Started Jul 09 05:30:13 PM PDT 24
Finished Jul 09 05:30:16 PM PDT 24
Peak memory 217244 kb
Host smart-ed79e412-1d40-4c4c-9d44-58409b691690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484674517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.484674517
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3624875637
Short name T651
Test name
Test status
Simulation time 357659633 ps
CPU time 0.83 seconds
Started Jul 09 05:30:18 PM PDT 24
Finished Jul 09 05:30:19 PM PDT 24
Peak memory 206960 kb
Host smart-1bd41050-25c9-4286-9a73-495eae41b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624875637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3624875637
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3587689052
Short name T576
Test name
Test status
Simulation time 301674309 ps
CPU time 3.15 seconds
Started Jul 09 05:30:11 PM PDT 24
Finished Jul 09 05:30:15 PM PDT 24
Peak memory 233812 kb
Host smart-1105247d-98e2-4122-b950-1e993554f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587689052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3587689052
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1608337779
Short name T965
Test name
Test status
Simulation time 93979145 ps
CPU time 0.79 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:18 PM PDT 24
Peak memory 206280 kb
Host smart-3bb6a3b4-9810-47c8-9360-7f06f800772f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608337779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1608337779
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3697154783
Short name T634
Test name
Test status
Simulation time 4579784762 ps
CPU time 13.88 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:35 PM PDT 24
Peak memory 233868 kb
Host smart-7a626990-7b9a-4162-a8ad-b7bfe408c61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697154783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3697154783
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3064686579
Short name T306
Test name
Test status
Simulation time 41085863 ps
CPU time 0.79 seconds
Started Jul 09 05:30:19 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 207468 kb
Host smart-015c93de-d5ff-4ac3-923d-95af23a72f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064686579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3064686579
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4149235226
Short name T192
Test name
Test status
Simulation time 7327116316 ps
CPU time 94.52 seconds
Started Jul 09 05:30:18 PM PDT 24
Finished Jul 09 05:31:53 PM PDT 24
Peak memory 262088 kb
Host smart-ee9f6a90-0de0-46e2-9d5f-9c8271ae8dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149235226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4149235226
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.394677816
Short name T712
Test name
Test status
Simulation time 2472660748 ps
CPU time 20.56 seconds
Started Jul 09 05:30:19 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 233808 kb
Host smart-6182894b-25c5-4315-adf4-f4f074856640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394677816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.394677816
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.691026313
Short name T671
Test name
Test status
Simulation time 15524262424 ps
CPU time 45.11 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:31:06 PM PDT 24
Peak memory 252352 kb
Host smart-1747a0e6-cf14-4520-a09b-a1064cf3551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691026313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.691026313
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2948061963
Short name T275
Test name
Test status
Simulation time 338962869 ps
CPU time 11.47 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 233820 kb
Host smart-2656350b-d265-4ec9-a535-ff96027739c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948061963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2948061963
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3911259214
Short name T254
Test name
Test status
Simulation time 57179628503 ps
CPU time 412.24 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:37:14 PM PDT 24
Peak memory 268884 kb
Host smart-7ee1059a-32eb-450f-a5bf-5b042b32ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911259214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3911259214
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3815331284
Short name T624
Test name
Test status
Simulation time 5372158739 ps
CPU time 16.22 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 233868 kb
Host smart-5f5e3401-fdea-449c-bc1e-856a312b683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815331284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3815331284
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3217243306
Short name T565
Test name
Test status
Simulation time 111469134 ps
CPU time 3.19 seconds
Started Jul 09 05:30:16 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 225592 kb
Host smart-17e9ca52-60c5-4a93-b364-40913c2b94a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217243306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3217243306
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2525747245
Short name T495
Test name
Test status
Simulation time 214896850 ps
CPU time 2.38 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:23 PM PDT 24
Peak memory 225504 kb
Host smart-de61966f-6cfc-4863-9ded-1f0828235483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525747245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2525747245
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2990444429
Short name T687
Test name
Test status
Simulation time 7251859288 ps
CPU time 12.09 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 225688 kb
Host smart-33a669f2-32cf-4530-9c20-6ceb45efaf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990444429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2990444429
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3442714345
Short name T746
Test name
Test status
Simulation time 142018348 ps
CPU time 3.95 seconds
Started Jul 09 05:30:17 PM PDT 24
Finished Jul 09 05:30:22 PM PDT 24
Peak memory 220408 kb
Host smart-d88877fc-4daa-41c6-9de5-a8385eced0ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3442714345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3442714345
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4258040163
Short name T22
Test name
Test status
Simulation time 15425136532 ps
CPU time 123.56 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:32:28 PM PDT 24
Peak memory 255916 kb
Host smart-03337dcf-81f6-4aec-9e5e-77154d949cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258040163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4258040163
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3358361523
Short name T284
Test name
Test status
Simulation time 273655068 ps
CPU time 2.72 seconds
Started Jul 09 05:30:16 PM PDT 24
Finished Jul 09 05:30:19 PM PDT 24
Peak memory 217436 kb
Host smart-4635ac18-3846-438c-9e6d-e909a7cb4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358361523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3358361523
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4288571852
Short name T692
Test name
Test status
Simulation time 689479568 ps
CPU time 3.14 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 217340 kb
Host smart-0c04a56e-e2b5-4c4b-8370-d7f574ad3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288571852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4288571852
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4042629156
Short name T320
Test name
Test status
Simulation time 48103129 ps
CPU time 0.93 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 207932 kb
Host smart-2238bf05-b450-48fd-8044-bec3bae9e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042629156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4042629156
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1402955892
Short name T865
Test name
Test status
Simulation time 128811064 ps
CPU time 0.95 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 207980 kb
Host smart-e6abbd87-7892-45b6-84b1-5197f527cfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402955892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1402955892
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2434955343
Short name T380
Test name
Test status
Simulation time 2558572547 ps
CPU time 12.29 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 239740 kb
Host smart-257c833b-ea3c-450b-958b-50109fd04f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434955343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2434955343
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1960369002
Short name T979
Test name
Test status
Simulation time 24375740 ps
CPU time 0.76 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 205828 kb
Host smart-e3253045-50f7-4def-a61e-b616dd114489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960369002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1960369002
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4141637601
Short name T233
Test name
Test status
Simulation time 5870001608 ps
CPU time 7.61 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 233860 kb
Host smart-dd4f1749-0720-4131-a189-72d20a0debf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141637601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4141637601
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1676081281
Short name T337
Test name
Test status
Simulation time 16368218 ps
CPU time 0.76 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 207840 kb
Host smart-0c786983-a6e7-4062-a73e-ace6011dd5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676081281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1676081281
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.986670181
Short name T423
Test name
Test status
Simulation time 80545458491 ps
CPU time 128.32 seconds
Started Jul 09 05:30:28 PM PDT 24
Finished Jul 09 05:32:37 PM PDT 24
Peak memory 250232 kb
Host smart-0ddbac0b-42ad-4a24-8439-65e209a30937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986670181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.986670181
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1347909299
Short name T218
Test name
Test status
Simulation time 30333379400 ps
CPU time 251.77 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:34:34 PM PDT 24
Peak memory 250292 kb
Host smart-a43ffd6a-4270-45aa-bd12-de13f5ea4fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347909299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1347909299
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2267380732
Short name T766
Test name
Test status
Simulation time 1864234077 ps
CPU time 30.01 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 233812 kb
Host smart-fb19b537-c5a2-48ad-804f-190e2ec00020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267380732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2267380732
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3872394625
Short name T963
Test name
Test status
Simulation time 2043942209 ps
CPU time 38.91 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:31:05 PM PDT 24
Peak memory 243152 kb
Host smart-1b74d225-da95-4b65-831b-68d068d61a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872394625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3872394625
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2506785406
Short name T332
Test name
Test status
Simulation time 1027577663 ps
CPU time 9.7 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:32 PM PDT 24
Peak memory 225524 kb
Host smart-75bb7b3b-54ce-4aa7-8f01-88c9279207d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506785406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2506785406
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1114784223
Short name T589
Test name
Test status
Simulation time 423900183 ps
CPU time 5.29 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 233660 kb
Host smart-e44e35af-dedd-44bd-ae49-536588202c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114784223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1114784223
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3611952624
Short name T540
Test name
Test status
Simulation time 31960660 ps
CPU time 2.52 seconds
Started Jul 09 05:30:31 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 233388 kb
Host smart-b6796658-191f-4ec7-8038-a5cf298bb7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611952624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3611952624
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.87809979
Short name T517
Test name
Test status
Simulation time 183554829 ps
CPU time 3.17 seconds
Started Jul 09 05:30:30 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 225420 kb
Host smart-173d49d9-b91e-4b81-bf8e-d195d3929e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87809979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.87809979
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2183485161
Short name T435
Test name
Test status
Simulation time 514726978 ps
CPU time 5.58 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 224104 kb
Host smart-7f86310b-b376-4d16-91c6-8f9c56399ad2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2183485161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2183485161
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.483202735
Short name T52
Test name
Test status
Simulation time 2093476029 ps
CPU time 5.72 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 217364 kb
Host smart-bc3f8dbf-176b-46c1-a580-6c56303264c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483202735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.483202735
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4151554258
Short name T482
Test name
Test status
Simulation time 257977271 ps
CPU time 2.47 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 217288 kb
Host smart-ae8af0d6-16a7-45b6-bd4c-ff56a1c8c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151554258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4151554258
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4073132782
Short name T907
Test name
Test status
Simulation time 309816223 ps
CPU time 1.33 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 208904 kb
Host smart-853f4ebf-f71f-427b-b1db-17989aad8c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073132782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4073132782
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.18842503
Short name T537
Test name
Test status
Simulation time 76201596 ps
CPU time 0.84 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 208000 kb
Host smart-74cff665-fc04-4f7c-b1ab-db64c37b4167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18842503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.18842503
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3737631246
Short name T427
Test name
Test status
Simulation time 2372575681 ps
CPU time 8.92 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 233864 kb
Host smart-58a0871d-9031-4a62-8c19-e587cc6d1177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737631246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3737631246
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2944414483
Short name T968
Test name
Test status
Simulation time 668862536 ps
CPU time 2.91 seconds
Started Jul 09 05:30:31 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 225508 kb
Host smart-5c2aeb61-a77e-43f1-b5b5-12488cac6424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944414483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2944414483
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.303072660
Short name T459
Test name
Test status
Simulation time 20667444 ps
CPU time 0.81 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 207752 kb
Host smart-8b4d6765-82a4-41f4-a38f-939f893407fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303072660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.303072660
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3741900175
Short name T202
Test name
Test status
Simulation time 448435192349 ps
CPU time 190.44 seconds
Started Jul 09 05:30:28 PM PDT 24
Finished Jul 09 05:33:39 PM PDT 24
Peak memory 250696 kb
Host smart-60a0b9fb-c9d5-4476-8216-a9719e88de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741900175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3741900175
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2484582728
Short name T656
Test name
Test status
Simulation time 21524481224 ps
CPU time 80.54 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:31:54 PM PDT 24
Peak memory 258532 kb
Host smart-2f2a773c-cbe6-4eff-b6fc-a144c4f35ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484582728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2484582728
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2458176393
Short name T266
Test name
Test status
Simulation time 10865958831 ps
CPU time 86.82 seconds
Started Jul 09 05:30:28 PM PDT 24
Finished Jul 09 05:31:56 PM PDT 24
Peak memory 251412 kb
Host smart-9b035622-e937-405f-b27e-ed9a9e61765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458176393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2458176393
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4133823042
Short name T271
Test name
Test status
Simulation time 3737355849 ps
CPU time 29.62 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:31:05 PM PDT 24
Peak memory 240432 kb
Host smart-a238956a-4ead-436d-81b9-f87960ab351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133823042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4133823042
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.975755204
Short name T808
Test name
Test status
Simulation time 3798619177 ps
CPU time 15.5 seconds
Started Jul 09 05:30:31 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 242220 kb
Host smart-deadcebd-2ce6-4313-bb97-428e66c538e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975755204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.975755204
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3903465714
Short name T822
Test name
Test status
Simulation time 120269378 ps
CPU time 4.24 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 230660 kb
Host smart-5a385eb1-85ca-46b3-8b1c-b14af30a3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903465714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3903465714
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3177775638
Short name T81
Test name
Test status
Simulation time 5167123808 ps
CPU time 27.07 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 233760 kb
Host smart-91bdec65-5ea3-44c1-99dc-945d584602d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177775638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3177775638
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4017977471
Short name T653
Test name
Test status
Simulation time 32937865 ps
CPU time 2.4 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 233364 kb
Host smart-0f24524f-8a68-4592-b49d-c5d63c1fea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017977471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4017977471
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2393710556
Short name T301
Test name
Test status
Simulation time 135597243 ps
CPU time 2.35 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 233364 kb
Host smart-e6254f81-4666-4652-bc8f-bdbee8997203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393710556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2393710556
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3031922664
Short name T1005
Test name
Test status
Simulation time 324652021 ps
CPU time 4.12 seconds
Started Jul 09 05:30:29 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 224012 kb
Host smart-573e4541-577a-4ba3-a0cb-925dbff00d95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3031922664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3031922664
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3508208163
Short name T409
Test name
Test status
Simulation time 9282567784 ps
CPU time 62.68 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:31:35 PM PDT 24
Peak memory 254172 kb
Host smart-53727c46-827f-44e7-bc77-1e47d64f78cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508208163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3508208163
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4126850225
Short name T277
Test name
Test status
Simulation time 2123374197 ps
CPU time 17.59 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:43 PM PDT 24
Peak memory 217340 kb
Host smart-0905d863-62d7-49f4-a6d7-4554829f09df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126850225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4126850225
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2551234460
Short name T705
Test name
Test status
Simulation time 8238538344 ps
CPU time 14.58 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:42 PM PDT 24
Peak memory 217496 kb
Host smart-4fb7d959-8415-4aea-9876-2d8aa28b0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551234460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2551234460
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.839177198
Short name T1003
Test name
Test status
Simulation time 81288894 ps
CPU time 1.81 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 217292 kb
Host smart-8d23158b-b7ee-44f9-98b2-439f9e9eb53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839177198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.839177198
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2533268454
Short name T399
Test name
Test status
Simulation time 33708017 ps
CPU time 0.79 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 206964 kb
Host smart-c0a709ec-0b4d-4fe9-a014-e290754714f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533268454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2533268454
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1034101716
Short name T572
Test name
Test status
Simulation time 2108304542 ps
CPU time 5.46 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 225552 kb
Host smart-eefcfe9c-121f-49b1-9b54-6986843fb5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034101716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1034101716
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1445857774
Short name T1023
Test name
Test status
Simulation time 14406591 ps
CPU time 0.72 seconds
Started Jul 09 05:30:43 PM PDT 24
Finished Jul 09 05:30:44 PM PDT 24
Peak memory 206740 kb
Host smart-7e80cc60-de0c-42e8-a9b4-00c2af5c08ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445857774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1445857774
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.944124865
Short name T445
Test name
Test status
Simulation time 127939231 ps
CPU time 2.53 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 233756 kb
Host smart-3bc715f3-9e15-4e5e-a478-7ad632cd0f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944124865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.944124865
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1414914544
Short name T292
Test name
Test status
Simulation time 20752609 ps
CPU time 0.75 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 206284 kb
Host smart-6c42bd43-27af-4563-ba4a-841fe0ea0d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414914544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1414914544
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2286576228
Short name T229
Test name
Test status
Simulation time 36634027977 ps
CPU time 113.89 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:32:38 PM PDT 24
Peak memory 258364 kb
Host smart-8ef7d6fd-e3a6-40b2-9d9b-97c4865682f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286576228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2286576228
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4277983955
Short name T253
Test name
Test status
Simulation time 17328980816 ps
CPU time 205.22 seconds
Started Jul 09 05:30:41 PM PDT 24
Finished Jul 09 05:34:06 PM PDT 24
Peak memory 266108 kb
Host smart-011bde4a-0e7d-4e02-b57c-9c2bfa74ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277983955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4277983955
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.919945694
Short name T291
Test name
Test status
Simulation time 14167852298 ps
CPU time 39.5 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:31:28 PM PDT 24
Peak memory 218644 kb
Host smart-9b2bf5c8-662e-47e0-aa55-dca3c1974336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919945694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.919945694
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2356018999
Short name T498
Test name
Test status
Simulation time 2549015790 ps
CPU time 25.41 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:31:17 PM PDT 24
Peak memory 233844 kb
Host smart-3b2decfa-22c2-40fb-bd4f-2eddfb5c47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356018999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2356018999
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4065851512
Short name T533
Test name
Test status
Simulation time 233161546 ps
CPU time 5.16 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 233744 kb
Host smart-0036c7ae-b375-4d27-9ce5-4397bc2140be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065851512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4065851512
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4196633429
Short name T106
Test name
Test status
Simulation time 89881727822 ps
CPU time 56.09 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:31:41 PM PDT 24
Peak memory 233840 kb
Host smart-87d97d2b-996d-48d2-a346-c0b752128dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196633429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4196633429
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2203274272
Short name T931
Test name
Test status
Simulation time 6070772590 ps
CPU time 18.97 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:31:09 PM PDT 24
Peak memory 233788 kb
Host smart-94a9ab70-7073-4b4c-89a9-a332475511cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203274272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2203274272
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1857747849
Short name T954
Test name
Test status
Simulation time 576140211 ps
CPU time 5.28 seconds
Started Jul 09 05:30:41 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 233712 kb
Host smart-542b4b0e-3b76-4da1-8270-8268e3ce545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857747849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1857747849
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2926938416
Short name T1014
Test name
Test status
Simulation time 285037166 ps
CPU time 5.69 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 220344 kb
Host smart-5a5704d8-fa5a-42a9-81b1-d369b0f71740
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926938416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2926938416
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.216035299
Short name T422
Test name
Test status
Simulation time 8774726935 ps
CPU time 134.2 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:33:03 PM PDT 24
Peak memory 266720 kb
Host smart-70c4bf38-1bab-49cf-aef8-0cbea7da5590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216035299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.216035299
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.823838413
Short name T708
Test name
Test status
Simulation time 4390012930 ps
CPU time 27.92 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:31:01 PM PDT 24
Peak memory 218768 kb
Host smart-568aa27f-ec9f-42c8-941d-9f25068f03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823838413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.823838413
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1651642697
Short name T764
Test name
Test status
Simulation time 943524159 ps
CPU time 2.88 seconds
Started Jul 09 05:30:43 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 217328 kb
Host smart-d26299ca-fe87-406d-b7ac-caf1ba64c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651642697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1651642697
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1258753343
Short name T441
Test name
Test status
Simulation time 909197609 ps
CPU time 5.22 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 217200 kb
Host smart-f6109419-8029-4c7e-9b14-09b6204242b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258753343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1258753343
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1867192532
Short name T368
Test name
Test status
Simulation time 145868365 ps
CPU time 0.83 seconds
Started Jul 09 05:30:35 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 206984 kb
Host smart-253c9128-6389-4a9d-9926-525da2d33925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867192532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1867192532
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2393007048
Short name T520
Test name
Test status
Simulation time 1767102193 ps
CPU time 10.39 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 241948 kb
Host smart-d998059c-dc32-49fa-8cca-d73a3ca9c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393007048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2393007048
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.792710389
Short name T608
Test name
Test status
Simulation time 23619103 ps
CPU time 0.75 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:33 PM PDT 24
Peak memory 206272 kb
Host smart-cf978ed2-51c8-4a78-9b70-201190601729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792710389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.792710389
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.395266759
Short name T652
Test name
Test status
Simulation time 11854025463 ps
CPU time 10.11 seconds
Started Jul 09 05:28:29 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 233784 kb
Host smart-ceaef142-6df1-44d9-b23f-5b3234d4a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395266759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.395266759
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3851815321
Short name T303
Test name
Test status
Simulation time 39179103 ps
CPU time 0.81 seconds
Started Jul 09 05:28:25 PM PDT 24
Finished Jul 09 05:28:26 PM PDT 24
Peak memory 207524 kb
Host smart-ce29e470-0fab-469f-962e-6a51ce4390f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851815321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3851815321
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1896402748
Short name T800
Test name
Test status
Simulation time 2960916776 ps
CPU time 16.66 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 239716 kb
Host smart-55da104e-37e1-4622-9df2-36851884acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896402748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1896402748
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3518695195
Short name T733
Test name
Test status
Simulation time 163270708926 ps
CPU time 335.57 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:34:04 PM PDT 24
Peak memory 252996 kb
Host smart-d89b67e9-e4fa-4366-bd3c-55ac485807f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518695195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3518695195
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3434037790
Short name T31
Test name
Test status
Simulation time 22813399435 ps
CPU time 258.89 seconds
Started Jul 09 05:28:33 PM PDT 24
Finished Jul 09 05:32:52 PM PDT 24
Peak memory 258604 kb
Host smart-7bab6d6a-776d-4901-8f3c-561d81115b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434037790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3434037790
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1132620810
Short name T276
Test name
Test status
Simulation time 3584626306 ps
CPU time 13.62 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 233956 kb
Host smart-9146f266-0690-45c0-a127-9b4a8ebcc25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132620810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1132620810
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1132170161
Short name T967
Test name
Test status
Simulation time 36848805681 ps
CPU time 42.71 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 250264 kb
Host smart-9038260f-5a52-4c9d-887f-5ad26ab6b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132170161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1132170161
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3890928464
Short name T425
Test name
Test status
Simulation time 699911961 ps
CPU time 5.03 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:28:36 PM PDT 24
Peak memory 225448 kb
Host smart-a43755f5-bc81-4867-8b2e-98eef6f95201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890928464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3890928464
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2336217047
Short name T387
Test name
Test status
Simulation time 8146240865 ps
CPU time 55.64 seconds
Started Jul 09 05:28:28 PM PDT 24
Finished Jul 09 05:29:24 PM PDT 24
Peak memory 240912 kb
Host smart-04c4c9fa-69fd-4655-80e1-67a5d8a95379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336217047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2336217047
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.797681938
Short name T887
Test name
Test status
Simulation time 26975433 ps
CPU time 1 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:25 PM PDT 24
Peak memory 218960 kb
Host smart-1f6bf753-3a5d-4f54-8ad4-e2fb5c5e8197
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797681938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.797681938
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1739495507
Short name T1010
Test name
Test status
Simulation time 208892822 ps
CPU time 2.91 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:28 PM PDT 24
Peak memory 233700 kb
Host smart-021b6ed7-7c84-4ed1-a97b-613490bb2dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739495507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1739495507
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.634513956
Short name T826
Test name
Test status
Simulation time 93291733 ps
CPU time 3.03 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:27 PM PDT 24
Peak memory 225520 kb
Host smart-1f07311e-d312-45eb-83f1-a82d6ba171c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634513956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.634513956
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1359130155
Short name T1007
Test name
Test status
Simulation time 11230528857 ps
CPU time 13.84 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:28:45 PM PDT 24
Peak memory 219952 kb
Host smart-7cfeeea2-5ef5-4b16-9a83-6de05e6a66fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359130155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1359130155
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3023912598
Short name T526
Test name
Test status
Simulation time 46896627723 ps
CPU time 161.58 seconds
Started Jul 09 05:28:29 PM PDT 24
Finished Jul 09 05:31:11 PM PDT 24
Peak memory 266876 kb
Host smart-83f69bc7-ab7c-4317-ab69-db8be5de63ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023912598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3023912598
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1596166107
Short name T622
Test name
Test status
Simulation time 2900672138 ps
CPU time 21.11 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 217436 kb
Host smart-852965f1-7d0b-4076-8a5d-ca19e05dbe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596166107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1596166107
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3057106863
Short name T358
Test name
Test status
Simulation time 4566545007 ps
CPU time 2.02 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:35 PM PDT 24
Peak memory 208952 kb
Host smart-614b44f1-8eab-47cf-87fc-d35a1f0716c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057106863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3057106863
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2862489194
Short name T673
Test name
Test status
Simulation time 1167674169 ps
CPU time 1.38 seconds
Started Jul 09 05:28:24 PM PDT 24
Finished Jul 09 05:28:26 PM PDT 24
Peak memory 209148 kb
Host smart-c4efc5a4-7e40-46be-83f8-e9b17ba8063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862489194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2862489194
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.465999273
Short name T843
Test name
Test status
Simulation time 48301816 ps
CPU time 0.92 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:28:27 PM PDT 24
Peak memory 208000 kb
Host smart-7969b937-ecda-4203-b01f-a49f45184b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465999273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.465999273
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4256680077
Short name T350
Test name
Test status
Simulation time 122501266 ps
CPU time 2.74 seconds
Started Jul 09 05:28:30 PM PDT 24
Finished Jul 09 05:28:33 PM PDT 24
Peak memory 233772 kb
Host smart-ba2daa9c-1dc7-4ecf-bc34-fa2dda7b2c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256680077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4256680077
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1187013591
Short name T64
Test name
Test status
Simulation time 14022530 ps
CPU time 0.72 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:33 PM PDT 24
Peak memory 206348 kb
Host smart-f3c4c26d-5d58-4c93-a246-d8e92beee546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187013591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
187013591
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.733858997
Short name T503
Test name
Test status
Simulation time 4476380946 ps
CPU time 13.75 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 233876 kb
Host smart-37ed46ed-849e-4a59-9c9c-db9006821b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733858997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.733858997
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1734030597
Short name T313
Test name
Test status
Simulation time 21719359 ps
CPU time 0.79 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:28:37 PM PDT 24
Peak memory 207744 kb
Host smart-38d90974-6b4c-4775-bef8-928460b02087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734030597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1734030597
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.750550206
Short name T180
Test name
Test status
Simulation time 7694540362 ps
CPU time 66.82 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:29:40 PM PDT 24
Peak memory 256244 kb
Host smart-5675a202-ba1e-4a5d-9a0a-9fb10e5e2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750550206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.750550206
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1822982226
Short name T421
Test name
Test status
Simulation time 31341609397 ps
CPU time 117.72 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 255504 kb
Host smart-e66f95fc-bf67-493f-9fb3-0c22cc37e263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822982226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1822982226
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3495055948
Short name T90
Test name
Test status
Simulation time 12736395365 ps
CPU time 40.19 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 233948 kb
Host smart-8f4d599e-270d-42ec-8292-9a590a7232ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495055948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3495055948
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2167576201
Short name T448
Test name
Test status
Simulation time 48638025571 ps
CPU time 77.96 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:30:00 PM PDT 24
Peak memory 239584 kb
Host smart-4c43a4ea-5967-4ea5-8cbe-d4d83aa25f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167576201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2167576201
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3330563321
Short name T632
Test name
Test status
Simulation time 2329333422 ps
CPU time 4.12 seconds
Started Jul 09 05:28:25 PM PDT 24
Finished Jul 09 05:28:30 PM PDT 24
Peak memory 233848 kb
Host smart-a0929a3a-4859-4e33-8831-2457a04b5293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330563321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3330563321
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2440532367
Short name T709
Test name
Test status
Simulation time 24955510059 ps
CPU time 51.6 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:29:23 PM PDT 24
Peak memory 233844 kb
Host smart-646d8461-c563-4e61-b5d6-2f135670673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440532367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2440532367
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.561136616
Short name T330
Test name
Test status
Simulation time 60576173 ps
CPU time 1.07 seconds
Started Jul 09 05:28:29 PM PDT 24
Finished Jul 09 05:28:31 PM PDT 24
Peak memory 217592 kb
Host smart-e7d984ed-272b-4cdf-9647-8fca34370b52
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561136616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.561136616
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3882298297
Short name T951
Test name
Test status
Simulation time 2400325094 ps
CPU time 9.35 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 225560 kb
Host smart-d94350de-d48c-4b62-b6fc-150ed19fb686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882298297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3882298297
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3794450844
Short name T936
Test name
Test status
Simulation time 226692756 ps
CPU time 4.74 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:28:32 PM PDT 24
Peak memory 233624 kb
Host smart-03f2ebdc-c021-4fb1-94f6-fb5e06af8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794450844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3794450844
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2841239925
Short name T780
Test name
Test status
Simulation time 315710809 ps
CPU time 3.69 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 224196 kb
Host smart-df2b1682-748b-4a25-96ff-b224efa4480c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841239925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2841239925
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3121656418
Short name T617
Test name
Test status
Simulation time 3209392032 ps
CPU time 10.87 seconds
Started Jul 09 05:28:27 PM PDT 24
Finished Jul 09 05:28:39 PM PDT 24
Peak memory 217396 kb
Host smart-7e903125-87ea-49a2-b6e7-d8b53d52cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121656418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3121656418
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3968991398
Short name T522
Test name
Test status
Simulation time 390490301 ps
CPU time 3.46 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 217240 kb
Host smart-64549759-348a-4aef-8e87-149cd303eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968991398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3968991398
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.380322901
Short name T348
Test name
Test status
Simulation time 137492690 ps
CPU time 1.09 seconds
Started Jul 09 05:28:26 PM PDT 24
Finished Jul 09 05:28:28 PM PDT 24
Peak memory 208428 kb
Host smart-ead5d82f-c967-457e-95e0-3132c0e0767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380322901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.380322901
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2526416589
Short name T920
Test name
Test status
Simulation time 77182797 ps
CPU time 0.75 seconds
Started Jul 09 05:28:29 PM PDT 24
Finished Jul 09 05:28:30 PM PDT 24
Peak memory 206888 kb
Host smart-5cdf24a0-5024-4fef-a0ca-f5f6c7d7518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526416589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2526416589
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2724399304
Short name T9
Test name
Test status
Simulation time 27309524588 ps
CPU time 21.2 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 233824 kb
Host smart-32bde5b4-ccf1-4d8d-8748-b8ca13b0a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724399304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2724399304
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.783667161
Short name T294
Test name
Test status
Simulation time 23011358 ps
CPU time 0.73 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:38 PM PDT 24
Peak memory 206316 kb
Host smart-ff69bb08-e647-46e9-b5e2-ab5b2e0fd975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783667161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.783667161
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.875444470
Short name T492
Test name
Test status
Simulation time 2940665387 ps
CPU time 6.41 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 233772 kb
Host smart-c896600a-bab7-4d52-93d2-3e404272ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875444470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.875444470
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1750867699
Short name T793
Test name
Test status
Simulation time 15882702 ps
CPU time 0.81 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 207440 kb
Host smart-e9aa2e5e-d1e9-472d-8b60-3a786eadee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750867699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1750867699
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3518622666
Short name T844
Test name
Test status
Simulation time 24071439575 ps
CPU time 174.32 seconds
Started Jul 09 05:28:34 PM PDT 24
Finished Jul 09 05:31:29 PM PDT 24
Peak memory 249832 kb
Host smart-94990401-508e-4b67-8ab6-a8a09d29fe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518622666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3518622666
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.525354349
Short name T875
Test name
Test status
Simulation time 15469297245 ps
CPU time 95.29 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:30:13 PM PDT 24
Peak memory 252064 kb
Host smart-6866f18b-de24-41e6-b975-361951fe9737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525354349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.525354349
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.317596218
Short name T208
Test name
Test status
Simulation time 2205554019 ps
CPU time 11.68 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 242548 kb
Host smart-3a1e7bb9-b2cf-49a2-8127-9d9d12402eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317596218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
317596218
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.49928904
Short name T489
Test name
Test status
Simulation time 645806120 ps
CPU time 7.87 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 225536 kb
Host smart-226f49c6-7ed1-4714-9d7c-ceaf375f07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49928904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.49928904
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2483444785
Short name T784
Test name
Test status
Simulation time 10292739814 ps
CPU time 65.11 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:29:44 PM PDT 24
Peak memory 256612 kb
Host smart-a535122b-93d3-466a-ba71-25eb3f31a2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483444785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2483444785
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.420510624
Short name T197
Test name
Test status
Simulation time 18951381234 ps
CPU time 20.99 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 225580 kb
Host smart-8d006171-1217-4797-be98-ee4c4e18c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420510624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.420510624
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1753846501
Short name T830
Test name
Test status
Simulation time 2002280856 ps
CPU time 24.67 seconds
Started Jul 09 05:28:31 PM PDT 24
Finished Jul 09 05:28:56 PM PDT 24
Peak memory 233604 kb
Host smart-0ead9938-4c35-47a2-adaa-4ce468df1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753846501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1753846501
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1686573820
Short name T700
Test name
Test status
Simulation time 94423857 ps
CPU time 1 seconds
Started Jul 09 05:28:35 PM PDT 24
Finished Jul 09 05:28:36 PM PDT 24
Peak memory 217656 kb
Host smart-49a22681-0e57-4032-bce7-27a05a77ee4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686573820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1686573820
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.267483280
Short name T257
Test name
Test status
Simulation time 5829537616 ps
CPU time 20.24 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 234576 kb
Host smart-3d5cdfa9-1209-4a03-8230-7be58899fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267483280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
267483280
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2418239421
Short name T564
Test name
Test status
Simulation time 2998979262 ps
CPU time 4.46 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 225548 kb
Host smart-4e6abf93-d23c-41f7-afd3-d2a9f1f8a4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418239421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2418239421
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1498573994
Short name T997
Test name
Test status
Simulation time 704107554 ps
CPU time 7.02 seconds
Started Jul 09 05:28:34 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 221192 kb
Host smart-5021675e-9e3f-4e58-b124-3603bd690df0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498573994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1498573994
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3729306953
Short name T153
Test name
Test status
Simulation time 40132332326 ps
CPU time 405.8 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:35:30 PM PDT 24
Peak memory 266304 kb
Host smart-5d3edd49-e2b5-41e9-bd7e-7335f3d32909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729306953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3729306953
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2343894611
Short name T281
Test name
Test status
Simulation time 1727504105 ps
CPU time 26.3 seconds
Started Jul 09 05:28:33 PM PDT 24
Finished Jul 09 05:29:00 PM PDT 24
Peak memory 221316 kb
Host smart-80b10d4b-329c-4713-8a7f-50e49295ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343894611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2343894611
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.603715547
Short name T921
Test name
Test status
Simulation time 2291944913 ps
CPU time 2.33 seconds
Started Jul 09 05:28:32 PM PDT 24
Finished Jul 09 05:28:35 PM PDT 24
Peak memory 208944 kb
Host smart-173d4879-5ea8-465c-b02d-e9a68c5fa3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603715547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.603715547
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1999184646
Short name T758
Test name
Test status
Simulation time 121489166 ps
CPU time 1.42 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:28:43 PM PDT 24
Peak memory 217308 kb
Host smart-7716c105-5336-477b-acc7-1a3dbcc441e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999184646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1999184646
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1808232740
Short name T508
Test name
Test status
Simulation time 88352008 ps
CPU time 0.95 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:28:38 PM PDT 24
Peak memory 206924 kb
Host smart-9d28c4bf-41ce-4ac7-943c-a47e1db86fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808232740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1808232740
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.964404484
Short name T342
Test name
Test status
Simulation time 43664075668 ps
CPU time 40.46 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:29:18 PM PDT 24
Peak memory 252756 kb
Host smart-e43c9fcf-c3e2-47c0-b14f-311b9ce863df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964404484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.964404484
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1324886015
Short name T437
Test name
Test status
Simulation time 44490177 ps
CPU time 0.72 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 205832 kb
Host smart-8d3e3a17-08dc-46d3-9dde-005d5d73c372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324886015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
324886015
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1195329348
Short name T854
Test name
Test status
Simulation time 99401710 ps
CPU time 2.3 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 225028 kb
Host smart-15edb1e1-d71e-4c52-ac0f-efd34718ef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195329348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1195329348
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1506198846
Short name T883
Test name
Test status
Simulation time 21085007 ps
CPU time 0.73 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 207512 kb
Host smart-dcad5db1-8925-440b-821b-f70aa8d43cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506198846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1506198846
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4276999818
Short name T863
Test name
Test status
Simulation time 5902066508 ps
CPU time 39.38 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 252252 kb
Host smart-ada190a3-fa7f-4c9f-ae8d-037346d61d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276999818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4276999818
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1217380350
Short name T891
Test name
Test status
Simulation time 8548384598 ps
CPU time 46.81 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:29:27 PM PDT 24
Peak memory 252888 kb
Host smart-b4aaa597-ca7f-4bab-ba62-a72671720f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217380350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1217380350
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2067122979
Short name T925
Test name
Test status
Simulation time 2675892934 ps
CPU time 31.83 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 238840 kb
Host smart-4d395383-1945-46a9-bc4d-15a9c28edebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067122979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2067122979
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3510395510
Short name T214
Test name
Test status
Simulation time 8728038591 ps
CPU time 58.22 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:29:38 PM PDT 24
Peak memory 235912 kb
Host smart-ac720d5d-3b8d-44b7-a2b3-f009113be4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510395510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3510395510
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4106829116
Short name T196
Test name
Test status
Simulation time 449953226 ps
CPU time 5.9 seconds
Started Jul 09 05:28:34 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 225456 kb
Host smart-8669f9e5-e57c-4f4e-a1ec-793ef9d54f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106829116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4106829116
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.214014415
Short name T506
Test name
Test status
Simulation time 33354253 ps
CPU time 2.58 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 233432 kb
Host smart-5f3c71d1-172c-4101-a516-f9755d0e4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214014415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.214014415
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2225978953
Short name T401
Test name
Test status
Simulation time 27709294 ps
CPU time 1.09 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 217568 kb
Host smart-f9480ee1-66cc-46b5-844e-df885a1c9a6f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225978953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2225978953
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4057544640
Short name T46
Test name
Test status
Simulation time 1260822905 ps
CPU time 5.83 seconds
Started Jul 09 05:28:42 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 225508 kb
Host smart-3d2243e1-3ad8-40a8-995b-bb34fc3b74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057544640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4057544640
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.378963732
Short name T371
Test name
Test status
Simulation time 1845082879 ps
CPU time 7.49 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 233792 kb
Host smart-b5504976-0c7c-4609-98cb-26e32ec0cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378963732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.378963732
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2489208452
Short name T933
Test name
Test status
Simulation time 676878077 ps
CPU time 5.21 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 221100 kb
Host smart-4405210a-1b62-44a0-bb44-9cc10b5a3d0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489208452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2489208452
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2407497793
Short name T186
Test name
Test status
Simulation time 249945943476 ps
CPU time 610.84 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:38:48 PM PDT 24
Peak memory 258592 kb
Host smart-d0cce635-3dd6-45ac-92ce-4738e4dcf445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407497793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2407497793
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4201200959
Short name T713
Test name
Test status
Simulation time 5649603907 ps
CPU time 19.98 seconds
Started Jul 09 05:28:41 PM PDT 24
Finished Jul 09 05:29:02 PM PDT 24
Peak memory 217580 kb
Host smart-0b958b12-9543-40af-806a-81101fcf52b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201200959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4201200959
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2053470354
Short name T507
Test name
Test status
Simulation time 7426909225 ps
CPU time 12.13 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 217456 kb
Host smart-a048c265-84f3-4683-89a2-de1ec47200b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053470354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2053470354
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2602211499
Short name T870
Test name
Test status
Simulation time 69122431 ps
CPU time 0.82 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:55 PM PDT 24
Peak memory 206996 kb
Host smart-9ca91d16-1677-4dcd-bc0b-4a3063bcb599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602211499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2602211499
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1567930842
Short name T905
Test name
Test status
Simulation time 107370074 ps
CPU time 1.01 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 208000 kb
Host smart-9c0ed8d4-94f0-4132-96cd-414e896ef88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567930842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1567930842
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.833919765
Short name T807
Test name
Test status
Simulation time 13985018209 ps
CPU time 22.51 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 236960 kb
Host smart-2a8237d7-b3da-44b3-a87d-73f1fcbc175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833919765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.833919765
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1051073199
Short name T67
Test name
Test status
Simulation time 53855206 ps
CPU time 0.71 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 206316 kb
Host smart-697b8a00-512a-4285-a5c9-580777c10494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051073199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
051073199
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3249047085
Short name T328
Test name
Test status
Simulation time 167142712 ps
CPU time 3.02 seconds
Started Jul 09 05:28:44 PM PDT 24
Finished Jul 09 05:28:48 PM PDT 24
Peak memory 225516 kb
Host smart-8cbe2928-8e47-4047-a37f-c84b4d4ac301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249047085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3249047085
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1995674973
Short name T357
Test name
Test status
Simulation time 65397878 ps
CPU time 0.76 seconds
Started Jul 09 05:28:48 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 207856 kb
Host smart-8e4cdb74-c779-46ca-b481-bee8f9ceb685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995674973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1995674973
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2678094024
Short name T699
Test name
Test status
Simulation time 1706525701 ps
CPU time 18.23 seconds
Started Jul 09 05:28:45 PM PDT 24
Finished Jul 09 05:29:04 PM PDT 24
Peak memory 237676 kb
Host smart-b2096a8f-fec9-43f4-b669-6a9e9df0b726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678094024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2678094024
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1531212816
Short name T832
Test name
Test status
Simulation time 86104670459 ps
CPU time 206.25 seconds
Started Jul 09 05:28:35 PM PDT 24
Finished Jul 09 05:32:02 PM PDT 24
Peak memory 250396 kb
Host smart-39a760b4-3299-4337-b08e-4ef63c3e186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531212816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1531212816
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2585781976
Short name T850
Test name
Test status
Simulation time 17905989978 ps
CPU time 126.05 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:30:45 PM PDT 24
Peak memory 269940 kb
Host smart-46814b66-5e5f-4a34-a3dd-2b0c6ed51c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585781976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2585781976
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3751222797
Short name T319
Test name
Test status
Simulation time 41220605 ps
CPU time 2.54 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 233692 kb
Host smart-fdb91b8f-d966-4a53-b19e-ab74e1d8f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751222797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3751222797
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3058040499
Short name T265
Test name
Test status
Simulation time 95079274177 ps
CPU time 157.4 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:31:16 PM PDT 24
Peak memory 274764 kb
Host smart-2a0d6608-b31b-415b-a591-8faa226896b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058040499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3058040499
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3131585205
Short name T216
Test name
Test status
Simulation time 891468959 ps
CPU time 4.49 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 233772 kb
Host smart-f8aeacd0-4330-43de-9b7a-df7e2c111c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131585205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3131585205
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3462814517
Short name T317
Test name
Test status
Simulation time 7127270803 ps
CPU time 19.69 seconds
Started Jul 09 05:28:43 PM PDT 24
Finished Jul 09 05:29:03 PM PDT 24
Peak memory 233784 kb
Host smart-fa4d4bbb-0036-4236-a6ac-de1dad24fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462814517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3462814517
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.982256025
Short name T785
Test name
Test status
Simulation time 90724554 ps
CPU time 1 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:49 PM PDT 24
Peak memory 218952 kb
Host smart-129ea1a0-d126-4d8c-82b7-5cbbb6e9290f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982256025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.982256025
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.874553850
Short name T735
Test name
Test status
Simulation time 15640535085 ps
CPU time 13.14 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:51 PM PDT 24
Peak memory 225584 kb
Host smart-df960240-5d4f-4ef8-a7de-5f9772539d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874553850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
874553850
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1292931646
Short name T524
Test name
Test status
Simulation time 70823749 ps
CPU time 2.56 seconds
Started Jul 09 05:28:47 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 233696 kb
Host smart-de148034-5315-4661-86a3-61f5a9deb544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292931646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1292931646
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2623583420
Short name T618
Test name
Test status
Simulation time 1102665392 ps
CPU time 5.85 seconds
Started Jul 09 05:28:46 PM PDT 24
Finished Jul 09 05:28:53 PM PDT 24
Peak memory 223516 kb
Host smart-c81b0898-065f-4653-8e48-aa99ddd4371d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2623583420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2623583420
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2891407221
Short name T628
Test name
Test status
Simulation time 116410680 ps
CPU time 1 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:28:41 PM PDT 24
Peak memory 207804 kb
Host smart-5c860694-8887-4b55-b28f-aca966c13e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891407221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2891407221
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2952195115
Short name T471
Test name
Test status
Simulation time 23795591164 ps
CPU time 31.4 seconds
Started Jul 09 05:28:39 PM PDT 24
Finished Jul 09 05:29:12 PM PDT 24
Peak memory 217504 kb
Host smart-88d25d12-f24e-48ea-89a9-a55cee6f2373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952195115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2952195115
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3593992823
Short name T848
Test name
Test status
Simulation time 273806701 ps
CPU time 1.89 seconds
Started Jul 09 05:28:37 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 217048 kb
Host smart-92a27f20-ac92-40dd-9898-a719c9cf7850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593992823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3593992823
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1360532275
Short name T861
Test name
Test status
Simulation time 1863257519 ps
CPU time 3.37 seconds
Started Jul 09 05:28:33 PM PDT 24
Finished Jul 09 05:28:37 PM PDT 24
Peak memory 217360 kb
Host smart-2d47438c-febc-4e84-8eb5-09ead736a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360532275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1360532275
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.260979371
Short name T335
Test name
Test status
Simulation time 119387145 ps
CPU time 0.77 seconds
Started Jul 09 05:28:38 PM PDT 24
Finished Jul 09 05:28:40 PM PDT 24
Peak memory 206788 kb
Host smart-ca6a31f4-1275-445b-ab8c-ab67fddf3188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260979371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.260979371
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3588463436
Short name T232
Test name
Test status
Simulation time 3231770437 ps
CPU time 14.08 seconds
Started Jul 09 05:28:36 PM PDT 24
Finished Jul 09 05:28:50 PM PDT 24
Peak memory 241920 kb
Host smart-037aa0b2-895b-4940-8949-8a7f5c2bf78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588463436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3588463436
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%