Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2585248	1			T1	1		T2	2096		T3	1
all_values[1]	2585248	1			T1	1		T2	2096		T3	1
all_values[2]	2585248	1			T1	1		T2	2096		T3	1
all_values[3]	2585248	1			T1	1		T2	2096		T3	1
all_values[4]	2585248	1			T1	1		T2	2096		T3	1
all_values[5]	2585248	1			T1	1		T2	2096		T3	1
all_values[6]	2585248	1			T1	1		T2	2096		T3	1
all_values[7]	2585248	1			T1	1		T2	2096		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20158572

1

T1

8

T2

16768

T3

8

auto[1]

523412

1

T13

75

T15

74

T52

2321

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20655288

1

T1

8

T2

16768

T3

8

auto[1]

26696

1

T6

127

T13

59

T15

37

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2486401	1			T1	1		T2	2096		T3	1
all_values[0]	auto[0]	auto[1]	12587	1			T6	93		T13	2		T15	1
all_values[0]	auto[1]	auto[0]	85726	1			T13	3		T15	10		T52	417
all_values[0]	auto[1]	auto[1]	534	1			T13	7		T15	3		T52	46
all_values[1]	auto[0]	auto[0]	2485152	1			T1	1		T2	2096		T3	1
all_values[1]	auto[0]	auto[1]	8194	1			T6	30		T13	8		T15	2
all_values[1]	auto[1]	auto[0]	91490	1			T13	4		T15	6		T52	447
all_values[1]	auto[1]	auto[1]	412	1			T13	5		T52	18		T17	2
all_values[2]	auto[0]	auto[0]	2521772	1			T1	1		T2	2096		T3	1
all_values[2]	auto[0]	auto[1]	2955	1			T6	4		T13	4		T15	3
all_values[2]	auto[1]	auto[0]	60320	1			T13	6		T15	5		T52	463
all_values[2]	auto[1]	auto[1]	201	1			T13	2		T15	2		T17	2
all_values[3]	auto[0]	auto[0]	2473819	1			T1	1		T2	2096		T3	1
all_values[3]	auto[0]	auto[1]	187	1			T15	2		T17	1		T18	4
all_values[3]	auto[1]	auto[0]	111038	1			T13	8		T15	9		T52	2
all_values[3]	auto[1]	auto[1]	204	1			T13	3		T15	2		T17	4
all_values[4]	auto[0]	auto[0]	2541335	1			T1	1		T2	2096		T3	1
all_values[4]	auto[0]	auto[1]	148	1			T13	2		T52	1		T19	2
all_values[4]	auto[1]	auto[0]	43566	1			T13	6		T15	8		T52	464
all_values[4]	auto[1]	auto[1]	199	1			T13	7		T15	6		T17	2
all_values[5]	auto[0]	auto[0]	2494296	1			T1	1		T2	2096		T3	1
all_values[5]	auto[0]	auto[1]	157	1			T13	2		T15	5		T52	1
all_values[5]	auto[1]	auto[0]	90621	1			T13	9		T15	1		T52	463
all_values[5]	auto[1]	auto[1]	174	1			T13	2		T15	3		T17	5
all_values[6]	auto[0]	auto[0]	2562870	1			T1	1		T2	2096		T3	1
all_values[6]	auto[0]	auto[1]	193	1			T13	7		T15	2		T17	4
all_values[6]	auto[1]	auto[0]	21985	1			T13	2		T15	6		T17	1
all_values[6]	auto[1]	auto[1]	200	1			T13	2		T15	2		T17	1
all_values[7]	auto[0]	auto[0]	2568346	1			T1	1		T2	2096		T3	1
all_values[7]	auto[0]	auto[1]	160	1			T13	2		T17	3		T18	7
all_values[7]	auto[1]	auto[0]	16551	1			T13	5		T15	7		T17	3
all_values[7]	auto[1]	auto[1]	191	1			T13	4		T15	4		T52	1