Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34327	1			T1	2		T2	171		T5	2
auto[SpiFlashAddrCfg]	7914	1			T1	2		T2	27		T5	6
auto[SpiFlashAddr3b]	9235	1			T1	2		T2	21		T3	4
auto[SpiFlashAddr4b]	7576	1			T2	36		T3	6		T6	48

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33117

1

T1

6

T2

88

T3

10

auto[1]

25935

1

T2

167

T6

240

T7

64

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31704

1

T1

2

T2

139

T3

4

auto[1]

27348

1

T1

4

T2

116

T3

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39198	1			T1	2		T2	190		T5	6
values[1]	1061	1			T2	4		T6	7		T7	1
values[2]	1472	1			T2	5		T6	16		T7	5
values[3]	1456	1			T2	8		T6	9		T7	6
values[4]	1523	1			T2	2		T6	16		T7	11
values[5]	1533	1			T2	10		T3	4		T6	7
values[6]	1437	1			T2	5		T5	6		T6	9
values[7]	1472	1			T2	1		T6	9		T7	11
values[8]	9900	1			T1	4		T2	30		T3	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29312

1

T1

6

T2

255

T3

10

auto[1]

29740

1

T6

310

T7

160

T8

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55752

1

T1

6

T2

247

T3

10

write

3300

1

T2

8

T6

30

T7

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19321

1

T1

2

T2

64

T3

6

valids[0x1]

39731

1

T1

4

T2

191

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1617	1			T2	6		T6	16		T7	4
internal_process_ops[0x5a]	1639	1			T2	2		T5	4		T6	8
internal_process_ops[0x05]	20167	1			T2	121		T6	338		T7	5
internal_process_ops[0x35]	1606	1			T1	2		T2	5		T6	6
internal_process_ops[0x15]	1677	1			T2	7		T5	2		T6	17
internal_process_ops[0x03]	1083	1			T1	2		T2	9		T6	1
internal_process_ops[0x0b]	1075	1			T2	7		T3	4		T6	4
internal_process_ops[0x3b]	1041	1			T2	5		T3	4		T6	8
internal_process_ops[0x6b]	1102	1			T2	7		T3	2		T5	4
internal_process_ops[0xbb]	1127	1			T2	6		T6	4		T7	2
internal_process_ops[0xeb]	1003	1			T1	2		T2	1		T5	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57484

1

T1

6

T2

251

T3

10

auto[1]

1568

1

T2

4

T6

13

T7

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56631

1

T1

6

T2

250

T3

10

auto[1]

2421

1

T2

5

T6

24

T7

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9528

1

T1

2

T2

45

T5

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5755

1

T2

125

T6

128

T22

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2149

1

T1

2

T2

9

T5

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1848

1

T2

16

T6

9

T40

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2457

1

T1

2

T2

10

T3

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2168

1

T2

9

T6

12

T40

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1981

1

T2

18

T3

6

T6

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1848

1

T2

15

T6

3

T22

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

115

1

T6

3

T42

4

T71

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T2

1

T6

1

T42

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T40

1

T42

1

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T6

2

T42

1

T51

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T2

1

T40

1

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

75

1

T40

6

T42

1

T52

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T2

1

T6

2

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T42

1

T50

4

T43

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

100

1

T10

2

T40

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T2

2

T6

1

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

100

1

T40

2

T42

3

T43

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

122

1

T6

3

T40

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

131

1

T2

2

T40

6

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T42

2

T34

2

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T40

1

T42

1

T52

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

84

1

T2

1

T34

4

T154

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10386

1

T6

174

T7

40

T49

9

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7805

1

T6

28

T7

17

T49

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1604

1

T6

14

T7

18

T8

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1540

1

T6

11

T7

13

T49

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1898

1

T6

23

T7

21

T49

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1856

1

T6

9

T7

17

T49

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1476

1

T6

8

T7

15

T8

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1453

1

T6

25

T7

9

T49

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

153

1

T6

1

T56

1

T17

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T31

3

T41

1

T33

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

96

1

T41

2

T33

1

T56

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

108

1

T7

4

T31

1

T65

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T6

2

T31

1

T65

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T6

1

T56

2

T94

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T7

2

T33

3

T155

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T6

1

T49

1

T33

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T6

5

T7

1

T31

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T6

1

T33

3

T56

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T6

1

T49

1

T33

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

128

1

T6

2

T7

2

T65

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T7

1

T56

1

T17

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T94

3

T156

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

109

1

T6

3

T31

1

T155

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T6

1

T65

3

T94

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3757	1			T2	25		T6	19		T9	2
auto[0]	values[0]	valids[0x1]	14533	1			T1	2		T2	165		T5	6
auto[0]	values[1]	valids[0x1]	523	1			T2	4		T6	3		T22	2
auto[0]	values[2]	valids[0x0]	488	1			T2	3		T6	9		T11	4
auto[0]	values[2]	valids[0x1]	321	1			T2	2		T6	2		T40	3
auto[0]	values[3]	valids[0x0]	511	1			T2	2		T6	1		T40	3
auto[0]	values[3]	valids[0x1]	331	1			T2	6		T6	1		T11	4
auto[0]	values[4]	valids[0x0]	537	1			T2	2		T6	4		T40	9
auto[0]	values[4]	valids[0x1]	297	1			T80	4		T42	2		T51	2
auto[0]	values[5]	valids[0x0]	583	1			T2	5		T3	4		T6	1
auto[0]	values[5]	valids[0x1]	292	1			T2	5		T40	2		T42	7
auto[0]	values[6]	valids[0x0]	555	1			T2	4		T5	6		T6	2
auto[0]	values[6]	valids[0x1]	297	1			T2	1		T10	4		T11	4
auto[0]	values[7]	valids[0x0]	492	1			T6	1		T79	2		T80	2
auto[0]	values[7]	valids[0x1]	306	1			T2	1		T6	1		T10	2
auto[0]	values[8]	valids[0x0]	3431	1			T1	2		T2	23		T3	2
auto[0]	values[8]	valids[0x1]	2058	1			T1	2		T2	7		T3	4
auto[1]	values[0]	valids[0x0]	4078	1			T6	37		T7	39		T49	9
auto[1]	values[0]	valids[0x1]	16830	1			T6	185		T7	37		T49	22
auto[1]	values[1]	valids[0x1]	538	1			T6	4		T7	1		T31	3
auto[1]	values[2]	valids[0x0]	393	1			T6	5		T7	1		T45	1
auto[1]	values[2]	valids[0x1]	270	1			T7	4		T49	1		T31	4
auto[1]	values[3]	valids[0x0]	367	1			T6	3		T7	5		T31	2
auto[1]	values[3]	valids[0x1]	247	1			T6	4		T7	1		T49	4
auto[1]	values[4]	valids[0x0]	421	1			T6	6		T7	4		T41	1
auto[1]	values[4]	valids[0x1]	268	1			T6	6		T7	7		T31	1
auto[1]	values[5]	valids[0x0]	405	1			T6	3		T7	3		T49	2
auto[1]	values[5]	valids[0x1]	253	1			T6	3		T7	2		T41	2
auto[1]	values[6]	valids[0x0]	364	1			T6	5		T7	1		T49	1
auto[1]	values[6]	valids[0x1]	221	1			T6	2		T7	2		T31	2
auto[1]	values[7]	valids[0x0]	374	1			T6	6		T7	8		T8	4
auto[1]	values[7]	valids[0x1]	300	1			T6	1		T7	3		T8	2
auto[1]	values[8]	valids[0x0]	2565	1			T6	24		T7	28		T49	5
auto[1]	values[8]	valids[0x1]	1846	1			T6	16		T7	14		T8	1