Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3474873

1

T1

3468

T2

9072

T3

12432

auto[1]

28752

1

T2

115

T6

326

T7

47

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979972

1

T1

3468

T2

36

T3

12432

auto[1]

2523653

1

T2

9151

T5

1138

T6

16920

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	694910	1			T1	8		T2	4618		T3	974
auto[524288:1048575]	419232	1			T2	3139		T3	228		T5	200
auto[1048576:1572863]	441002	1			T1	70		T2	516		T3	4428
auto[1572864:2097151]	354814	1			T1	454		T2	435		T5	292
auto[2097152:2621439]	403267	1			T1	977		T2	32		T3	275
auto[2621440:3145727]	394990	1			T1	495		T2	60		T5	702
auto[3145728:3670015]	395862	1			T1	986		T2	386		T3	6525
auto[3670016:4194303]	399548	1			T1	478		T2	1		T3	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2556866

1

T1

80

T2

9185

T3

64

auto[1]

946759

1

T1

3388

T2

2

T3

12368

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3065502

1

T1

3468

T2

4032

T3

12432

auto[1]

438123

1

T2

5155

T6

3391

T7

1346

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	242312	1			T1	8		T2	4		T3	974
auto[0]	auto[0]	auto[0:524287]	auto[1]	403034	1			T2	2919		T5	1131		T6	482
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104565	1			T2	1		T3	228		T5	200
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	249276	1			T2	129		T6	1413		T7	1859
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	135039	1			T1	70		T2	3		T3	4428
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232208	1			T2	513		T6	4015		T7	890
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75816	1			T1	454		T2	8		T5	292
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	217944	1			T2	2		T6	2821		T7	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	93699	1			T1	977		T3	275		T5	2470
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	266667	1			T6	264		T7	1		T40	513
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	108732	1			T1	495		T2	3		T5	700
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	229081	1			T2	10		T5	2		T6	384
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	100671	1			T1	986		T2	2		T3	6525
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	245193	1			T2	384		T6	2958		T7	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	98102	1			T1	478		T2	1		T3	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	239240	1			T5	5		T6	960		T40	3369
auto[0]	auto[1]	auto[0:524287]	auto[0]	3536	1			T2	2		T6	2		T33	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	42235	1			T2	1691		T6	1		T33	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	669	1			T2	3		T6	3		T7	14
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	61793	1			T2	3002		T6	2		T7	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3094	1			T7	25		T40	5		T33	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	67974	1			T7	5		T40	256		T33	770
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	888	1			T2	3		T7	2		T42	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54753	1			T2	385		T49	256		T42	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3402	1			T2	1		T7	6		T40	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	36158	1			T2	6		T7	1016		T40	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	591	1			T6	3		T7	8		T40	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52639	1			T6	2		T40	256		T42	2396
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1331	1			T49	1		T31	1		T33	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	45561	1			T33	513		T42	256		T43	258
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3521	1			T6	3		T7	3		T49	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55149	1			T6	3316		T49	250		T40	2565
auto[1]	auto[0]	auto[0:524287]	auto[0]	556	1			T2	1		T6	1		T40	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2581	1			T2	1		T6	49		T33	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	374	1			T2	1		T6	2		T40	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1575	1			T2	3		T6	13		T40	42
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	390	1			T6	2		T7	3		T40	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1790	1			T6	4		T40	34		T42	60
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	459	1			T6	5		T40	1		T41	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4209	1			T6	128		T40	5		T41	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	433	1			T6	3		T40	1		T43	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2461	1			T6	36		T43	43		T34	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	388	1			T2	1		T6	4		T7	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3162	1			T2	46		T6	19		T49	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	323	1			T7	3		T40	1		T31	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2243	1			T40	2		T31	3		T41	74
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	398	1			T6	1		T7	20		T33	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2581	1			T7	1		T33	6		T42	69
auto[1]	auto[1]	auto[0:524287]	auto[0]	69	1			T6	1		T7	3		T42	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	587	1			T6	17		T42	23		T65	126
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	118	1			T6	2		T43	2		T18	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	862	1			T6	24		T43	12		T18	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	90	1			T7	2		T33	2		T42	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	417	1			T33	2		T42	61		T182	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	102	1			T2	1		T7	6		T42	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	643	1			T2	36		T42	19		T17	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	85	1			T2	1		T40	2		T41	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	362	1			T2	24		T40	14		T41	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	67	1			T6	2		T19	1		T223	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	330	1			T6	4		T19	3		T20	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T33	1		T43	2		T17	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	462	1			T33	15		T43	27		T17	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	74	1			T6	1		T155	3		T17	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	483	1			T6	8		T35	5		T19	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2107630	1			T1	80		T2	3979		T3	64
auto[0]	auto[0]	auto[1]	933949	1			T1	3388		T3	12368		T5	10300
auto[0]	auto[1]	auto[0]	421263	1			T2	5092		T6	3332		T7	1335
auto[0]	auto[1]	auto[1]	12031	1			T2	1		T40	2		T41	1
auto[1]	auto[0]	auto[0]	23264	1			T2	52		T6	261		T7	33
auto[1]	auto[0]	auto[1]	659	1			T2	1		T6	6		T7	3
auto[1]	auto[1]	auto[0]	4709	1			T2	62		T6	57		T7	11
auto[1]	auto[1]	auto[1]	120	1			T6	2		T40	1		T42	2