Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2585248	1			T1	1		T2	2096		T3	1
all_pins[1]	2585248	1			T1	1		T2	2096		T3	1
all_pins[2]	2585248	1			T1	1		T2	2096		T3	1
all_pins[3]	2585248	1			T1	1		T2	2096		T3	1
all_pins[4]	2585248	1			T1	1		T2	2096		T3	1
all_pins[5]	2585248	1			T1	1		T2	2096		T3	1
all_pins[6]	2585248	1			T1	1		T2	2096		T3	1
all_pins[7]	2585248	1			T1	1		T2	2096		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20657244	1			T1	8		T2	16768		T3	8
values[0x1]	24740	1			T13	32		T15	22		T52	172
transitions[0x0=>0x1]	24113	1			T13	27		T15	19		T52	152
transitions[0x1=>0x0]	24125	1			T13	27		T15	19		T52	153

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2584664	1			T1	1		T2	2096		T3	1
all_pins[0]	values[0x1]	584	1			T13	7		T15	3		T52	51
all_pins[0]	transitions[0x0=>0x1]	331	1			T13	6		T15	3		T52	32
all_pins[0]	transitions[0x1=>0x0]	208	1			T13	4		T52	2		T17	1
all_pins[1]	values[0x0]	2584787	1			T1	1		T2	2096		T3	1
all_pins[1]	values[0x1]	461	1			T13	5		T52	21		T17	2
all_pins[1]	transitions[0x0=>0x1]	387	1			T13	4		T52	21		T17	2
all_pins[1]	transitions[0x1=>0x0]	134	1			T13	1		T15	2		T17	2
all_pins[2]	values[0x0]	2585040	1			T1	1		T2	2096		T3	1
all_pins[2]	values[0x1]	208	1			T13	2		T15	2		T17	2
all_pins[2]	transitions[0x0=>0x1]	148	1			T13	1		T15	2		T17	1
all_pins[2]	transitions[0x1=>0x0]	144	1			T13	2		T15	2		T17	3
all_pins[3]	values[0x0]	2585044	1			T1	1		T2	2096		T3	1
all_pins[3]	values[0x1]	204	1			T13	3		T15	2		T17	4
all_pins[3]	transitions[0x0=>0x1]	148	1			T13	2		T15	1		T17	2
all_pins[3]	transitions[0x1=>0x0]	143	1			T13	6		T15	5		T18	3
all_pins[4]	values[0x0]	2585049	1			T1	1		T2	2096		T3	1
all_pins[4]	values[0x1]	199	1			T13	7		T15	6		T17	2
all_pins[4]	transitions[0x0=>0x1]	152	1			T13	6		T15	5		T18	3
all_pins[4]	transitions[0x1=>0x0]	1364	1			T13	1		T15	2		T52	99
all_pins[5]	values[0x0]	2583837	1			T1	1		T2	2096		T3	1
all_pins[5]	values[0x1]	1411	1			T13	2		T15	3		T52	99
all_pins[5]	transitions[0x0=>0x1]	1364	1			T13	2		T15	2		T52	99
all_pins[5]	transitions[0x1=>0x0]	21435	1			T13	2		T15	1		T18	5
all_pins[6]	values[0x0]	2563766	1			T1	1		T2	2096		T3	1
all_pins[6]	values[0x1]	21482	1			T13	2		T15	2		T17	1
all_pins[6]	transitions[0x0=>0x1]	21434	1			T13	2		T15	2		T17	1
all_pins[6]	transitions[0x1=>0x0]	143	1			T13	4		T15	4		T52	1
all_pins[7]	values[0x0]	2585057	1			T1	1		T2	2096		T3	1
all_pins[7]	values[0x1]	191	1			T13	4		T15	4		T52	1
all_pins[7]	transitions[0x0=>0x1]	149	1			T13	4		T15	4		T17	1
all_pins[7]	transitions[0x1=>0x0]	554	1			T13	7		T15	3		T52	51