Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16900

1

T1

6

T2

88

T3

10

auto[1]

12412

1

T2

167

T6

159

T22

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3640	1			T2	193		T3	10		T10	10
values[1]	3459	1			T2	40		T6	121		T42	90
values[2]	4056	1			T40	40		T42	34		T125	16
values[3]	2870	1			T1	6		T80	18		T40	83
values[4]	3900	1			T6	94		T9	2		T11	18
values[5]	3560	1			T40	77		T42	75		T123	14
values[6]	3972	1			T6	20		T40	130		T43	45
values[7]	3855	1			T2	22		T5	16		T6	61

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3372	1			T2	71		T40	57		T42	54
values[1]	3808	1			T1	6		T11	18		T22	4
values[2]	3614	1			T2	42		T6	215		T9	2
values[3]	3800	1			T2	102		T40	40		T42	75
values[4]	3646	1			T2	20		T3	10		T5	16
values[5]	3761	1			T6	20		T10	10		T40	57
values[6]	3801	1			T2	20		T80	18		T40	20
values[7]	3510	1			T6	61		T79	16		T40	110

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	256	1			T2	17		T34	9		T19	12
auto[0]	values[0]	values[1]	342	1			T55	2		T42	120		T43	34
auto[0]	values[0]	values[2]	207	1			T2	9		T34	15		T181	14
auto[0]	values[0]	values[3]	338	1			T2	19		T43	9		T224	16
auto[0]	values[0]	values[4]	80	1			T3	10		T68	10		T208	18
auto[0]	values[0]	values[5]	234	1			T10	10		T202	12		T206	12
auto[0]	values[0]	values[6]	165	1			T71	33		T18	23		T192	13
auto[0]	values[0]	values[7]	439	1			T43	47		T35	12		T181	10
auto[0]	values[1]	values[0]	202	1			T34	11		T19	8		T182	35
auto[0]	values[1]	values[1]	422	1			T154	23		T53	27		T19	17
auto[0]	values[1]	values[2]	319	1			T6	99		T43	13		T34	14
auto[0]	values[1]	values[3]	166	1			T42	11		T213	2		T214	16
auto[0]	values[1]	values[4]	205	1			T2	14		T42	9		T164	15
auto[0]	values[1]	values[5]	286	1			T42	11		T44	20		T185	8
auto[0]	values[1]	values[6]	178	1			T2	13		T52	34		T201	26
auto[0]	values[1]	values[7]	345	1			T34	32		T53	11		T18	18
auto[0]	values[2]	values[0]	210	1			T42	27		T19	12		T20	8
auto[0]	values[2]	values[1]	215	1			T18	30		T19	14		T165	21
auto[0]	values[2]	values[2]	313	1			T40	11		T52	12		T19	9
auto[0]	values[2]	values[3]	147	1			T40	9		T53	22		T176	10
auto[0]	values[2]	values[4]	328	1			T43	32		T34	16		T53	14
auto[0]	values[2]	values[5]	281	1			T18	45		T163	13		T201	20
auto[0]	values[2]	values[6]	572	1			T43	53		T35	17		T53	13
auto[0]	values[2]	values[7]	130	1			T125	16		T163	16		T205	15
auto[0]	values[3]	values[0]	212	1			T35	16		T206	5		T160	12
auto[0]	values[3]	values[1]	166	1			T1	6		T35	11		T18	15
auto[0]	values[3]	values[2]	158	1			T225	16		T18	10		T182	9
auto[0]	values[3]	values[3]	231	1			T40	11		T35	15		T165	12
auto[0]	values[3]	values[4]	198	1			T40	19		T154	7		T35	17
auto[0]	values[3]	values[5]	206	1			T219	4		T19	9		T181	13
auto[0]	values[3]	values[6]	182	1			T80	18		T168	5		T206	7
auto[0]	values[3]	values[7]	158	1			T40	12		T42	41		T226	2
auto[0]	values[4]	values[0]	266	1			T42	10		T227	2		T179	6
auto[0]	values[4]	values[1]	389	1			T11	18		T34	16		T18	61
auto[0]	values[4]	values[2]	221	1			T6	15		T9	2		T43	13
auto[0]	values[4]	values[3]	268	1			T228	2		T164	17		T171	8
auto[0]	values[4]	values[4]	357	1			T42	156		T229	8		T168	7
auto[0]	values[4]	values[5]	316	1			T42	12		T19	20		T176	11
auto[0]	values[4]	values[6]	293	1			T18	14		T168	11		T19	12
auto[0]	values[4]	values[7]	151	1			T79	16		T206	10		T174	11
auto[0]	values[5]	values[0]	244	1			T40	51		T35	28		T181	17
auto[0]	values[5]	values[1]	235	1			T34	14		T230	4		T182	21
auto[0]	values[5]	values[2]	304	1			T154	12		T188	16		T181	12
auto[0]	values[5]	values[3]	422	1			T42	47		T189	8		T154	8
auto[0]	values[5]	values[4]	271	1			T231	16		T207	10		T232	20
auto[0]	values[5]	values[5]	216	1			T40	13		T43	4		T19	10
auto[0]	values[5]	values[6]	226	1			T42	5		T123	14		T233	2
auto[0]	values[5]	values[7]	272	1			T43	23		T34	12		T201	23
auto[0]	values[6]	values[0]	212	1			T43	14		T53	16		T165	11
auto[0]	values[6]	values[1]	366	1			T195	8		T187	22		T206	11
auto[0]	values[6]	values[2]	330	1			T40	16		T43	13		T34	25
auto[0]	values[6]	values[3]	253	1			T18	11		T208	13		T234	16
auto[0]	values[6]	values[4]	332	1			T34	15		T176	35		T165	11
auto[0]	values[6]	values[5]	366	1			T6	11		T40	31		T35	15
auto[0]	values[6]	values[6]	303	1			T69	22		T235	4		T192	9
auto[0]	values[6]	values[7]	168	1			T40	22		T72	22		T182	26
auto[0]	values[7]	values[0]	309	1			T236	4		T201	12		T237	8
auto[0]	values[7]	values[1]	209	1			T178	10		T238	2		T191	27
auto[0]	values[7]	values[2]	277	1			T2	16		T40	13		T182	33
auto[0]	values[7]	values[3]	345	1			T35	16		T19	29		T164	14
auto[0]	values[7]	values[4]	239	1			T5	16		T42	12		T35	40
auto[0]	values[7]	values[5]	145	1			T43	9		T154	16		T201	13
auto[0]	values[7]	values[6]	248	1			T40	14		T42	13		T154	10
auto[0]	values[7]	values[7]	456	1			T6	12		T143	14		T43	13
auto[1]	values[0]	values[0]	217	1			T2	54		T34	11		T19	12
auto[1]	values[0]	values[1]	136	1			T42	5		T43	9		T34	11
auto[1]	values[0]	values[2]	145	1			T2	11		T34	5		T212	14
auto[1]	values[0]	values[3]	351	1			T2	83		T43	39		T182	7
auto[1]	values[0]	values[4]	112	1			T239	12		T208	11		T176	50
auto[1]	values[0]	values[5]	121	1			T206	11		T166	5		T215	10
auto[1]	values[0]	values[6]	323	1			T18	173		T192	13		T184	9
auto[1]	values[0]	values[7]	174	1			T43	5		T35	11		T181	10
auto[1]	values[1]	values[0]	133	1			T34	9		T19	12		T182	27
auto[1]	values[1]	values[1]	202	1			T154	17		T53	24		T19	3
auto[1]	values[1]	values[2]	157	1			T6	22		T43	23		T34	6
auto[1]	values[1]	values[3]	117	1			T42	9		T50	14		T201	12
auto[1]	values[1]	values[4]	164	1			T2	6		T42	11		T164	5
auto[1]	values[1]	values[5]	198	1			T42	39		T19	16		T176	11
auto[1]	values[1]	values[6]	75	1			T2	7		T52	5		T201	9
auto[1]	values[1]	values[7]	290	1			T34	24		T53	9		T18	91
auto[1]	values[2]	values[0]	218	1			T42	7		T19	8		T20	13
auto[1]	values[2]	values[1]	222	1			T18	15		T19	6		T165	21
auto[1]	values[2]	values[2]	250	1			T40	9		T52	19		T19	11
auto[1]	values[2]	values[3]	120	1			T40	11		T53	8		T176	10
auto[1]	values[2]	values[4]	338	1			T43	13		T34	4		T53	12
auto[1]	values[2]	values[5]	328	1			T18	11		T163	7		T201	71
auto[1]	values[2]	values[6]	302	1			T43	4		T35	4		T53	7
auto[1]	values[2]	values[7]	82	1			T163	4		T205	5		T240	19
auto[1]	values[3]	values[0]	243	1			T241	6		T35	8		T206	20
auto[1]	values[3]	values[1]	88	1			T35	9		T18	16		T205	9
auto[1]	values[3]	values[2]	196	1			T18	10		T182	11		T184	9
auto[1]	values[3]	values[3]	214	1			T40	9		T35	5		T165	27
auto[1]	values[3]	values[4]	121	1			T40	7		T154	13		T35	7
auto[1]	values[3]	values[5]	193	1			T19	24		T181	7		T218	14
auto[1]	values[3]	values[6]	204	1			T168	15		T209	24		T206	13
auto[1]	values[3]	values[7]	100	1			T40	25		T42	9		T166	9
auto[1]	values[4]	values[0]	220	1			T42	10		T51	24		T187	11
auto[1]	values[4]	values[1]	241	1			T34	12		T18	9		T168	7
auto[1]	values[4]	values[2]	201	1			T6	79		T43	7		T35	12
auto[1]	values[4]	values[3]	149	1			T164	3		T171	12		T184	9
auto[1]	values[4]	values[4]	194	1			T42	15		T168	13		T208	11
auto[1]	values[4]	values[5]	255	1			T42	8		T19	8		T176	9
auto[1]	values[4]	values[6]	226	1			T18	6		T168	52		T19	11
auto[1]	values[4]	values[7]	153	1			T206	15		T174	9		T166	7
auto[1]	values[5]	values[0]	97	1			T40	6		T35	22		T181	3
auto[1]	values[5]	values[1]	250	1			T34	6		T182	6		T203	59
auto[1]	values[5]	values[2]	149	1			T154	8		T181	11		T182	9
auto[1]	values[5]	values[3]	220	1			T42	8		T154	12		T35	3
auto[1]	values[5]	values[4]	134	1			T242	20		T207	11		T243	10
auto[1]	values[5]	values[5]	230	1			T40	7		T43	29		T19	10
auto[1]	values[5]	values[6]	157	1			T42	15		T53	11		T160	8
auto[1]	values[5]	values[7]	133	1			T43	9		T34	10		T201	14
auto[1]	values[6]	values[0]	144	1			T43	6		T53	8		T165	9
auto[1]	values[6]	values[1]	244	1			T187	18		T206	9		T160	5
auto[1]	values[6]	values[2]	175	1			T40	4		T43	12		T34	28
auto[1]	values[6]	values[3]	166	1			T18	9		T208	7		T164	12
auto[1]	values[6]	values[4]	339	1			T34	5		T176	15		T165	9
auto[1]	values[6]	values[5]	226	1			T6	9		T40	6		T35	7
auto[1]	values[6]	values[6]	153	1			T192	11		T182	11		T203	9
auto[1]	values[6]	values[7]	195	1			T40	51		T182	17		T163	6
auto[1]	values[7]	values[0]	189	1			T201	8		T244	12		T237	12
auto[1]	values[7]	values[1]	81	1			T22	4		T191	6		T245	18
auto[1]	values[7]	values[2]	212	1			T2	6		T40	7		T182	18
auto[1]	values[7]	values[3]	293	1			T35	9		T19	7		T164	6
auto[1]	values[7]	values[4]	234	1			T42	105		T35	10		T203	11
auto[1]	values[7]	values[5]	160	1			T43	73		T154	7		T201	7
auto[1]	values[7]	values[6]	194	1			T40	6		T42	41		T154	10
auto[1]	values[7]	values[7]	264	1			T6	49		T43	7		T19	8