Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	385	1			T1	2		T3	2		T6	2
auto[ReadAddrCrossIntoMailbox]	279	1			T6	1		T79	4		T40	5
auto[ReadAddrCrossOutOfMailbox]	325	1			T6	1		T79	2		T40	4
auto[ReadAddrCrossAllMailbox]	230	1			T3	2		T6	2		T79	6
auto[ReadAddrOutsideMailbox]	3609	1			T1	2		T2	35		T3	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2322

1

T1

2

T2

21

T3

5

auto[1]

2506

1

T1

2

T2

14

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	821	1			T1	2		T2	9		T6	1
read_ops[0x0b]	810	1			T2	7		T3	4		T6	1
read_ops[0x3b]	794	1			T2	5		T3	4		T6	4
read_ops[0x6b]	825	1			T2	7		T3	2		T5	4
read_ops[0xbb]	841	1			T2	6		T6	3		T79	2
read_ops[0xeb]	737	1			T1	2		T2	1		T5	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T1	1		T154	1		T19	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T1	1		T42	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T79	1		T154	1		T216	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T79	1		T42	3		T34	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T79	1		T40	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T79	1		T154	2		T35	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T79	1		T187	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T79	1		T19	1		T182	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T2	4		T6	1		T11	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T2	5		T11	1		T40	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T40	1		T43	1		T154	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T42	1		T34	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T18	1		T168	1		T246	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T40	1		T42	1		T168	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T34	1		T208	1		T176	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T40	2		T42	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T35	1		T208	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T40	1		T52	1		T207	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T2	6		T3	2		T6	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T2	1		T3	2		T10	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T3	1		T42	1		T34	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T3	1		T6	1		T53	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T40	1		T43	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T53	1		T176	1		T192	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T43	1		T154	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T35	1		T18	1		T181	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T79	2		T43	2		T187	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T79	2		T40	1		T18	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T2	2		T3	1		T79	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T2	3		T3	1		T6	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T40	1		T34	1		T178	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T178	1		T168	1		T176	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T40	1		T34	2		T154	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T18	1		T181	1		T190	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T6	1		T35	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T42	1		T18	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T3	1		T6	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T3	1		T207	1		T247	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T2	5		T5	2		T40	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	341	1			T2	2		T5	2		T6	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T42	2		T34	1		T35	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T6	1		T185	1		T208	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T34	1		T18	1		T19	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T40	2		T154	2		T18	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T42	1		T34	2		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T40	1		T53	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T35	1		T19	1		T208	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T154	1		T216	1		T201	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	326	1			T2	4		T6	1		T79	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T2	2		T6	1		T79	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T248	1		T187	1		T165	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T40	1		T19	1		T248	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T6	1		T79	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T79	1		T52	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T168	1		T176	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T43	1		T34	1		T19	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T154	1		T208	1		T181	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T6	1		T40	1		T154	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T1	1		T5	3		T40	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T1	1		T2	1		T5	3