Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3307	1			T6	94		T79	16		T40	20
values[1]	3433	1			T6	61		T40	37		T42	34
values[2]	3589	1			T6	82		T55	2		T40	53
values[3]	4170	1			T2	62		T6	20		T40	94
values[4]	3430	1			T2	153		T3	10		T6	39
values[5]	3642	1			T2	40		T5	16		T22	4
values[6]	4204	1			T1	6		T10	10		T40	60
values[7]	3537	1			T9	2		T80	18		T40	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3712	1			T2	82		T40	37		T42	50
values[1]	4055	1			T2	20		T6	61		T22	4
values[2]	4117	1			T6	39		T40	40		T42	55
values[3]	3253	1			T2	71		T40	40		T42	90
values[4]	3764	1			T1	6		T2	20		T3	10
values[5]	3474	1			T6	176		T40	26		T42	94
values[6]	3659	1			T2	20		T5	16		T6	20
values[7]	3278	1			T2	42		T80	18		T40	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28576

1

T1

6

T2

251

T3

10

auto[1]

736

1

T2

4

T6

7

T40

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	231	1			T229	8		T35	20		T164	18
auto[0]	values[0]	values[1]	510	1			T187	44		T182	20		T201	19
auto[0]	values[0]	values[2]	539	1			T40	20		T34	20		T68	10
auto[0]	values[0]	values[3]	226	1			T154	20		T176	21		T60	33
auto[0]	values[0]	values[4]	309	1			T35	23		T203	43		T207	20
auto[0]	values[0]	values[5]	636	1			T6	94		T43	98		T19	19
auto[0]	values[0]	values[6]	335	1			T79	16		T53	26		T165	19
auto[0]	values[0]	values[7]	419	1			T35	43		T188	16		T190	27
auto[0]	values[1]	values[0]	415	1			T40	37		T43	82		T154	23
auto[0]	values[1]	values[1]	513	1			T6	60		T42	34		T43	19
auto[0]	values[1]	values[2]	416	1			T208	30		T235	4		T214	16
auto[0]	values[1]	values[3]	559	1			T43	50		T178	10		T202	12
auto[0]	values[1]	values[4]	232	1			T225	16		T249	10		T172	20
auto[0]	values[1]	values[5]	408	1			T18	107		T164	20		T250	12
auto[0]	values[1]	values[6]	359	1			T43	20		T179	6		T165	22
auto[0]	values[1]	values[7]	444	1			T168	53		T251	4		T207	20
auto[0]	values[2]	values[0]	525	1			T252	8		T210	10		T253	4
auto[0]	values[2]	values[1]	442	1			T69	22		T168	63		T246	4
auto[0]	values[2]	values[2]	426	1			T19	24		T254	10		T207	20
auto[0]	values[2]	values[3]	429	1			T42	49		T123	14		T35	20
auto[0]	values[2]	values[4]	381	1			T55	2		T42	20		T53	20
auto[0]	values[2]	values[5]	304	1			T6	78		T43	24		T230	4
auto[0]	values[2]	values[6]	497	1			T40	53		T203	20		T201	20
auto[0]	values[2]	values[7]	498	1			T43	32		T34	20		T185	8
auto[0]	values[3]	values[0]	390	1			T71	33		T34	20		T19	24
auto[0]	values[3]	values[1]	558	1			T42	20		T44	20		T34	20
auto[0]	values[3]	values[2]	625	1			T213	2		T35	26		T18	20
auto[0]	values[3]	values[3]	386	1			T35	20		T208	34		T207	25
auto[0]	values[3]	values[4]	824	1			T40	37		T34	35		T18	55
auto[0]	values[3]	values[5]	339	1			T42	20		T34	20		T154	20
auto[0]	values[3]	values[6]	602	1			T2	20		T6	20		T40	54
auto[0]	values[3]	values[7]	359	1			T2	41		T163	19		T184	40
auto[0]	values[4]	values[0]	649	1			T2	81		T181	136		T255	18
auto[0]	values[4]	values[1]	335	1			T35	49		T211	20		T256	6
auto[0]	values[4]	values[2]	476	1			T6	37		T42	53		T34	22
auto[0]	values[4]	values[3]	353	1			T2	69		T40	19		T42	20
auto[0]	values[4]	values[4]	444	1			T3	10		T18	20		T19	20
auto[0]	values[4]	values[5]	296	1			T34	22		T18	31		T168	18
auto[0]	values[4]	values[6]	350	1			T11	18		T35	19		T19	20
auto[0]	values[4]	values[7]	433	1			T40	20		T19	24		T187	40
auto[0]	values[5]	values[0]	467	1			T42	49		T43	32		T154	20
auto[0]	values[5]	values[1]	285	1			T2	20		T22	4		T160	20
auto[0]	values[5]	values[2]	427	1			T40	20		T18	45		T257	12
auto[0]	values[5]	values[3]	513	1			T72	22		T34	24		T189	8
auto[0]	values[5]	values[4]	570	1			T2	20		T143	14		T18	68
auto[0]	values[5]	values[5]	419	1			T42	54		T258	16		T181	20
auto[0]	values[5]	values[6]	536	1			T5	16		T50	8		T168	20
auto[0]	values[5]	values[7]	333	1			T40	20		T42	116		T248	2
auto[0]	values[6]	values[0]	322	1			T43	44		T53	20		T259	8
auto[0]	values[6]	values[1]	950	1			T40	20		T42	149		T34	18
auto[0]	values[6]	values[2]	674	1			T203	22		T171	51		T184	20
auto[0]	values[6]	values[3]	394	1			T40	18		T42	18		T43	20
auto[0]	values[6]	values[4]	419	1			T1	6		T10	10		T18	19
auto[0]	values[6]	values[5]	545	1			T34	19		T53	29		T19	31
auto[0]	values[6]	values[6]	492	1			T40	20		T154	17		T183	16
auto[0]	values[6]	values[7]	310	1			T220	20		T218	14		T260	4
auto[0]	values[7]	values[0]	637	1			T43	80		T35	19		T208	28
auto[0]	values[7]	values[1]	346	1			T168	18		T176	20		T160	20
auto[0]	values[7]	values[2]	430	1			T187	23		T192	63		T211	27
auto[0]	values[7]	values[3]	314	1			T164	20		T160	19		T174	20
auto[0]	values[7]	values[4]	517	1			T52	29		T53	38		T19	23
auto[0]	values[7]	values[5]	419	1			T40	25		T42	20		T176	84
auto[0]	values[7]	values[6]	396	1			T9	2		T241	6		T52	39
auto[0]	values[7]	values[7]	389	1			T80	18		T51	18		T35	30
auto[1]	values[0]	values[0]	8	1			T35	2		T164	2		T255	1
auto[1]	values[0]	values[1]	23	1			T187	2		T201	1		T261	2
auto[1]	values[0]	values[2]	19	1			T154	5		T182	2		T211	2
auto[1]	values[0]	values[3]	11	1			T176	2		T60	5		T240	1
auto[1]	values[0]	values[4]	5	1			T35	1		T262	3		T263	1
auto[1]	values[0]	values[5]	24	1			T43	2		T19	1		T160	1
auto[1]	values[0]	values[6]	9	1			T165	1		T166	3		T264	4
auto[1]	values[0]	values[7]	3	1			T35	1		T265	2		-	-
auto[1]	values[1]	values[0]	6	1			T208	5		T184	1		-	-
auto[1]	values[1]	values[1]	14	1			T6	1		T43	1		T34	4
auto[1]	values[1]	values[2]	15	1			T208	3		T182	1		T215	2
auto[1]	values[1]	values[3]	10	1			T43	2		T184	2		T177	1
auto[1]	values[1]	values[4]	5	1			T266	2		T205	1		T267	2
auto[1]	values[1]	values[5]	6	1			T18	2		T255	1		T205	2
auto[1]	values[1]	values[6]	7	1			T182	2		T211	1		T268	1
auto[1]	values[1]	values[7]	24	1			T168	2		T207	1		T184	1
auto[1]	values[2]	values[0]	10	1			T266	3		T265	1		T269	1
auto[1]	values[2]	values[1]	10	1			T163	1		T266	2		T222	1
auto[1]	values[2]	values[2]	15	1			T19	2		T60	3		T270	1
auto[1]	values[2]	values[3]	10	1			T42	1		T35	1		T182	1
auto[1]	values[2]	values[4]	5	1			T177	1		T271	1		T272	2
auto[1]	values[2]	values[5]	10	1			T6	4		T43	1		T172	1
auto[1]	values[2]	values[6]	13	1			T273	5		T243	1		T274	2
auto[1]	values[2]	values[7]	14	1			T197	2		T199	2		T152	2
auto[1]	values[3]	values[0]	1	1			T275	1		-	-		-	-
auto[1]	values[3]	values[1]	21	1			T34	1		T209	4		T176	5
auto[1]	values[3]	values[2]	9	1			T193	2		T269	3		T177	1
auto[1]	values[3]	values[3]	5	1			T207	1		T152	1		T63	2
auto[1]	values[3]	values[4]	13	1			T18	1		T181	2		T163	1
auto[1]	values[3]	values[5]	11	1			T197	2		T276	1		T263	4
auto[1]	values[3]	values[6]	13	1			T40	3		T42	1		T166	1
auto[1]	values[3]	values[7]	14	1			T2	1		T163	1		T277	2
auto[1]	values[4]	values[0]	14	1			T2	1		T181	1		T255	2
auto[1]	values[4]	values[1]	14	1			T35	1		T256	2		T278	2
auto[1]	values[4]	values[2]	11	1			T6	2		T42	2		T171	2
auto[1]	values[4]	values[3]	11	1			T2	2		T40	1		T181	1
auto[1]	values[4]	values[4]	8	1			T181	1		T182	2		T172	1
auto[1]	values[4]	values[5]	19	1			T34	1		T168	2		T192	4
auto[1]	values[4]	values[6]	5	1			T35	1		T182	1		T191	1
auto[1]	values[4]	values[7]	12	1			T207	1		T163	2		T279	6
auto[1]	values[5]	values[0]	11	1			T42	1		T43	1		T191	2
auto[1]	values[5]	values[1]	10	1			T205	3		T270	1		T222	1
auto[1]	values[5]	values[2]	7	1			T164	1		T211	1		T184	2
auto[1]	values[5]	values[3]	18	1			T34	6		T53	1		T197	4
auto[1]	values[5]	values[4]	10	1			T18	2		T197	1		T163	1
auto[1]	values[5]	values[5]	4	1			T198	1		T263	1		T280	1
auto[1]	values[5]	values[6]	21	1			T50	6		T181	1		T281	2
auto[1]	values[5]	values[7]	11	1			T42	1		T184	2		T282	2
auto[1]	values[6]	values[0]	15	1			T43	4		T283	4		T271	1
auto[1]	values[6]	values[1]	18	1			T42	2		T34	2		T176	2
auto[1]	values[6]	values[2]	15	1			T203	1		T191	1		T240	2
auto[1]	values[6]	values[3]	7	1			T40	2		T42	2		T18	1
auto[1]	values[6]	values[4]	5	1			T18	1		T271	3		T275	1
auto[1]	values[6]	values[5]	21	1			T34	1		T53	1		T19	2
auto[1]	values[6]	values[6]	11	1			T154	3		T182	1		T203	1
auto[1]	values[6]	values[7]	6	1			T284	2		T130	1		T285	1
auto[1]	values[7]	values[0]	11	1			T43	1		T35	1		T208	1
auto[1]	values[7]	values[1]	6	1			T168	2		T286	2		T287	2
auto[1]	values[7]	values[2]	13	1			T187	1		T192	4		T211	2
auto[1]	values[7]	values[3]	7	1			T160	1		T288	4		T267	2
auto[1]	values[7]	values[4]	17	1			T52	2		T163	3		T184	1
auto[1]	values[7]	values[5]	13	1			T40	1		T20	1		T206	4
auto[1]	values[7]	values[6]	13	1			T207	2		T184	5		T199	1
auto[1]	values[7]	values[7]	9	1			T51	6		T164	2		T184	1