Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_prev_wr_en	2	0	2	100.00	100	1	1	2
cp_wr_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	4	0	4	100.00	100	1	1	0

Summary for Variable cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_prev_wr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2308

1

T2

10

T6

18

T7

12

auto[1]

704

1

T2

3

T6

4

T7

3

---

Summary for Variable cp_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1470

1

T2

6

T6

14

T7

8

auto[1]

1542

1

T2

7

T6

8

T7

7

---

Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_wr_en

cp_prev_wr_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1155

1

T2

5

T6

11

T7

7

auto[0]

auto[1]

315

1

T2

1

T6

3

T7

1

auto[1]

auto[0]

1153

1

T2

5

T6

7

T7

5

auto[1]

auto[1]

389

1

T2

2

T6

1

T7

2