Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	767	1			T13	17		T15	14		T52	4
all_values[1]	767	1			T13	17		T15	14		T52	4
all_values[2]	767	1			T13	17		T15	14		T52	4
all_values[3]	767	1			T13	17		T15	14		T52	4
all_values[4]	767	1			T13	17		T15	14		T52	4
all_values[5]	767	1			T13	17		T15	14		T52	4
all_values[6]	767	1			T13	17		T15	14		T52	4
all_values[7]	767	1			T13	17		T15	14		T52	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3226

1

T13

66

T15

50

T52

18

auto[1]

2910

1

T13

70

T15

62

T52

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T13

49

T15

51

T52

15

auto[1]

3705

1

T13

87

T15

61

T52

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3514

1

T13

72

T15

67

T52

21

auto[1]

2622

1

T13

64

T15

45

T52

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	145	1			T13	3		T15	2		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	77	1			T52	1		T17	1		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	154	1			T13	1		T15	4		T20	9
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T13	2		T15	2		T52	1
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T13	3		T15	1		T52	2
all_values[0]	auto[1]	auto[1]	auto[1]	144	1			T13	8		T15	5		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T15	6		T18	1		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T13	3		T15	1		T17	2
all_values[1]	auto[0]	auto[1]	auto[0]	125	1			T13	1		T15	2		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T13	4		T52	2		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T13	4		T15	5		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T13	5		T52	2		T17	1
all_values[2]	auto[0]	auto[0]	auto[0]	148	1			T13	3		T15	3		T52	1
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T13	3		T15	1		T17	1
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T13	2		T15	2		T52	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T15	2		T17	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T13	4		T15	1		T52	2
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T13	4		T15	5		T18	5
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T13	6		T15	2		T52	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T15	1		T18	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	106	1			T13	5		T15	5		T52	2
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T13	1		T15	2		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	160	1			T13	1		T15	2		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	169	1			T13	4		T15	2		T52	1
all_values[4]	auto[0]	auto[0]	auto[0]	171	1			T13	2		T15	2		T17	2
all_values[4]	auto[0]	auto[0]	auto[1]	51	1			T52	1		T153	3		T146	2
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T13	3		T15	3		T52	1
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T13	4		T15	3		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	158	1			T13	4		T15	1		T52	1
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T13	4		T15	5		T52	1
all_values[5]	auto[0]	auto[0]	auto[0]	227	1			T13	6		T15	5		T52	2
all_values[5]	auto[0]	auto[1]	auto[0]	209	1			T13	7		T15	1		T52	1
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T13	2		T15	3		T52	1
all_values[5]	auto[1]	auto[1]	auto[1]	166	1			T13	2		T15	5		T17	5
all_values[6]	auto[0]	auto[0]	auto[0]	153	1			T13	4		T15	3		T52	4
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T13	2		T15	1		T17	1
all_values[6]	auto[0]	auto[1]	auto[0]	109	1			T13	1		T15	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T13	1		T15	1		T18	3
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T13	6		T15	2		T17	3
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T13	3		T15	5		T17	2
all_values[7]	auto[0]	auto[0]	auto[0]	179	1			T13	5		T15	8		T52	2
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T13	1		T17	2		T18	3
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T15	1		T17	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T13	1		T15	2		T52	1
all_values[7]	auto[1]	auto[0]	auto[1]	170	1			T13	4		T17	4		T18	6
all_values[7]	auto[1]	auto[1]	auto[1]	160	1			T13	6		T15	3		T52	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal