Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1736

1

T4

5

T6

4

T25

13

auto[1]

1702

1

T4

6

T6

4

T25

13

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T6

8

T28

19

T31

11

auto[1]

1482

1

T4

11

T25

26

T26

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2694

1

T4

11

T6

3

T25

26

auto[1]

744

1

T6

5

T28

9

T31

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	681	1			T4	3		T6	1		T25	4
valid[1]	666	1			T4	1		T6	2		T25	2
valid[2]	699	1			T4	2		T6	3		T25	7
valid[3]	713	1			T6	2		T25	7		T26	1
valid[4]	679	1			T4	5		T25	6		T28	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	103	1			T28	1		T33	1		T52	1
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T25	1		T27	2		T29	1
auto[0]	auto[0]	valid[1]	auto[0]	119	1			T28	3		T33	1		T52	1
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T4	1		T27	3		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T6	1		T31	1		T295	2
auto[0]	auto[0]	valid[2]	auto[1]	160	1			T4	1		T25	6		T27	1
auto[0]	auto[0]	valid[3]	auto[0]	144	1			T6	1		T28	2		T31	1
auto[0]	auto[0]	valid[3]	auto[1]	140	1			T25	3		T29	1		T32	7
auto[0]	auto[0]	valid[4]	auto[0]	116	1			T31	1		T33	3		T58	2
auto[0]	auto[0]	valid[4]	auto[1]	147	1			T4	3		T25	3		T29	2
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T28	3		T52	1		T56	1
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T4	3		T25	3		T27	1
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T31	1		T34	3		T56	2
auto[0]	auto[1]	valid[1]	auto[1]	125	1			T25	2		T27	1		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T6	1		T28	1		T31	1
auto[0]	auto[1]	valid[2]	auto[1]	141	1			T4	1		T25	1		T29	2
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T31	2		T34	2		T56	1
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T25	4		T26	1		T27	1
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T56	1		T58	1		T299	1
auto[0]	auto[1]	valid[4]	auto[1]	143	1			T4	2		T25	3		T29	2
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T28	1		T33	2		T34	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T6	2		T34	1		T56	1
auto[1]	auto[0]	valid[2]	auto[0]	78	1			T28	1		T33	1		T34	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T28	2		T56	1		T295	2
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T28	2		T34	1		T36	1
auto[1]	auto[1]	valid[0]	auto[0]	73	1			T6	1		T31	1		T33	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T28	1		T31	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T6	1		T33	2		T299	2
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T6	1		T28	2		T31	2
auto[1]	auto[1]	valid[4]	auto[0]	78	1			T33	1		T295	1		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal