Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49862

1

T6

190

T28

412

T30

12

auto[1]

16056

1

T4

11

T25

393

T26

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47588

1

T4

11

T6

119

T25

393

auto[1]

18330

1

T6

71

T28

159

T30

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33804	1			T4	11		T6	103		T25	199
others[1]	5598	1			T6	23		T25	28		T27	17
others[2]	5657	1			T6	16		T25	30		T27	9
others[3]	6292	1			T6	14		T25	46		T27	15
interest[1]	3609	1			T6	12		T25	20		T27	6
interest[4]	22100	1			T4	11		T6	70		T25	126
interest[64]	10958	1			T6	22		T25	70		T27	27

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15995	1			T6	66		T28	124		T30	2
auto[0]	auto[0]	others[1]	2755	1			T6	14		T28	28		T31	19
auto[0]	auto[0]	others[2]	2679	1			T6	10		T28	10		T30	1
auto[0]	auto[0]	others[3]	3066	1			T6	9		T28	31		T30	1
auto[0]	auto[0]	interest[1]	1739	1			T6	4		T28	17		T31	6
auto[0]	auto[0]	interest[4]	10376	1			T6	44		T28	81		T31	55
auto[0]	auto[0]	interest[64]	5298	1			T6	16		T28	43		T30	2
auto[0]	auto[1]	others[0]	8428	1			T4	11		T25	199		T26	1
auto[0]	auto[1]	others[1]	1289	1			T25	28		T27	17		T29	16
auto[0]	auto[1]	others[2]	1405	1			T25	30		T27	9		T29	16
auto[0]	auto[1]	others[3]	1444	1			T25	46		T27	15		T29	20
auto[0]	auto[1]	interest[1]	874	1			T25	20		T27	6		T29	11
auto[0]	auto[1]	interest[4]	5595	1			T4	11		T25	126		T26	1
auto[0]	auto[1]	interest[64]	2616	1			T25	70		T27	27		T29	34
auto[1]	auto[0]	others[0]	9381	1			T6	37		T28	84		T30	3
auto[1]	auto[0]	others[1]	1554	1			T6	9		T28	11		T30	1
auto[1]	auto[0]	others[2]	1573	1			T6	6		T28	13		T31	14
auto[1]	auto[0]	others[3]	1782	1			T6	5		T28	15		T31	12
auto[1]	auto[0]	interest[1]	996	1			T6	8		T28	12		T30	1
auto[1]	auto[0]	interest[4]	6129	1			T6	26		T28	55		T30	2
auto[1]	auto[0]	interest[64]	3044	1			T6	6		T28	24		T30	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal