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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T115 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1999192198 Jul 10 06:01:32 PM PDT 24 Jul 10 06:01:35 PM PDT 24 310118203 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3663410245 Jul 10 06:01:32 PM PDT 24 Jul 10 06:01:35 PM PDT 24 44622369 ps
T1025 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.134549994 Jul 10 06:02:06 PM PDT 24 Jul 10 06:02:07 PM PDT 24 32166107 ps
T1026 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3973249467 Jul 10 06:01:58 PM PDT 24 Jul 10 06:02:01 PM PDT 24 39059398 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2283687711 Jul 10 06:01:47 PM PDT 24 Jul 10 06:02:03 PM PDT 24 3291373431 ps
T108 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.729215222 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:57 PM PDT 24 1167691316 ps
T1027 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3014513213 Jul 10 06:02:01 PM PDT 24 Jul 10 06:02:06 PM PDT 24 291955072 ps
T145 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3033024793 Jul 10 06:01:37 PM PDT 24 Jul 10 06:01:42 PM PDT 24 2663378465 ps
T109 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.946366743 Jul 10 06:01:43 PM PDT 24 Jul 10 06:02:05 PM PDT 24 850953156 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3000337762 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:49 PM PDT 24 21357418 ps
T116 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4096898775 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:50 PM PDT 24 93107299 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3337928096 Jul 10 06:01:36 PM PDT 24 Jul 10 06:01:38 PM PDT 24 30407622 ps
T117 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3280059887 Jul 10 06:01:51 PM PDT 24 Jul 10 06:01:55 PM PDT 24 37968030 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2409982082 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:41 PM PDT 24 29032818 ps
T102 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4160892806 Jul 10 06:01:42 PM PDT 24 Jul 10 06:01:48 PM PDT 24 112221040 ps
T1030 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2035930417 Jul 10 06:01:58 PM PDT 24 Jul 10 06:02:00 PM PDT 24 65705058 ps
T103 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4174220449 Jul 10 06:01:48 PM PDT 24 Jul 10 06:01:52 PM PDT 24 38310185 ps
T1031 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1782084412 Jul 10 06:01:52 PM PDT 24 Jul 10 06:01:55 PM PDT 24 13772460 ps
T157 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1175258252 Jul 10 06:01:40 PM PDT 24 Jul 10 06:01:48 PM PDT 24 1512467066 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3654719350 Jul 10 06:01:46 PM PDT 24 Jul 10 06:01:48 PM PDT 24 15382732 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2619364587 Jul 10 06:01:30 PM PDT 24 Jul 10 06:01:32 PM PDT 24 38223372 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.577871425 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:55 PM PDT 24 17411877 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1199448437 Jul 10 06:01:42 PM PDT 24 Jul 10 06:01:47 PM PDT 24 518007370 ps
T1034 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3562760629 Jul 10 06:02:00 PM PDT 24 Jul 10 06:02:02 PM PDT 24 31576138 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1353119553 Jul 10 06:01:29 PM PDT 24 Jul 10 06:01:31 PM PDT 24 87773535 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4200592625 Jul 10 06:01:49 PM PDT 24 Jul 10 06:02:14 PM PDT 24 1050993358 ps
T106 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4177106432 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:43 PM PDT 24 49622483 ps
T1035 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1493417848 Jul 10 06:02:03 PM PDT 24 Jul 10 06:02:05 PM PDT 24 43700482 ps
T1036 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.954296834 Jul 10 06:01:44 PM PDT 24 Jul 10 06:01:52 PM PDT 24 302266220 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2331293827 Jul 10 06:01:33 PM PDT 24 Jul 10 06:01:36 PM PDT 24 28151961 ps
T121 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2535131662 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:51 PM PDT 24 86028661 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1134246513 Jul 10 06:01:35 PM PDT 24 Jul 10 06:01:38 PM PDT 24 18898713 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2776336851 Jul 10 06:01:40 PM PDT 24 Jul 10 06:01:42 PM PDT 24 96644488 ps
T1039 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1728513250 Jul 10 06:01:41 PM PDT 24 Jul 10 06:01:43 PM PDT 24 13181260 ps
T1040 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2966928248 Jul 10 06:02:01 PM PDT 24 Jul 10 06:02:04 PM PDT 24 37056597 ps
T1041 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2256443509 Jul 10 06:01:46 PM PDT 24 Jul 10 06:01:49 PM PDT 24 41013248 ps
T1042 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2094327400 Jul 10 06:01:58 PM PDT 24 Jul 10 06:02:00 PM PDT 24 44968966 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1207045781 Jul 10 06:01:27 PM PDT 24 Jul 10 06:01:36 PM PDT 24 357499333 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4210786888 Jul 10 06:01:41 PM PDT 24 Jul 10 06:01:44 PM PDT 24 490172757 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2498080976 Jul 10 06:01:54 PM PDT 24 Jul 10 06:01:59 PM PDT 24 145890261 ps
T105 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1719297304 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:44 PM PDT 24 143950827 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1091445321 Jul 10 06:01:32 PM PDT 24 Jul 10 06:01:36 PM PDT 24 66817371 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.365258004 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:42 PM PDT 24 150125523 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.192997425 Jul 10 06:02:01 PM PDT 24 Jul 10 06:02:22 PM PDT 24 388207705 ps
T1049 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1214267545 Jul 10 06:01:50 PM PDT 24 Jul 10 06:01:56 PM PDT 24 422097247 ps
T159 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1302450275 Jul 10 06:01:46 PM PDT 24 Jul 10 06:02:02 PM PDT 24 4050342936 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4227098569 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:54 PM PDT 24 89818802 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1548593019 Jul 10 06:01:41 PM PDT 24 Jul 10 06:01:42 PM PDT 24 12360124 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3816670730 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:43 PM PDT 24 233877439 ps
T1053 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2514269603 Jul 10 06:02:02 PM PDT 24 Jul 10 06:02:03 PM PDT 24 125991520 ps
T1054 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3061140766 Jul 10 06:02:04 PM PDT 24 Jul 10 06:02:06 PM PDT 24 18371553 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3599894024 Jul 10 06:01:31 PM PDT 24 Jul 10 06:01:39 PM PDT 24 1350404624 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.753810847 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:40 PM PDT 24 35538800 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3391678242 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:53 PM PDT 24 169055425 ps
T1058 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1102945249 Jul 10 06:02:04 PM PDT 24 Jul 10 06:02:06 PM PDT 24 42253465 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2276086915 Jul 10 06:01:57 PM PDT 24 Jul 10 06:02:00 PM PDT 24 75738625 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1280957583 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:51 PM PDT 24 60834268 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4040048888 Jul 10 06:01:33 PM PDT 24 Jul 10 06:01:38 PM PDT 24 269685414 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1596997201 Jul 10 06:01:51 PM PDT 24 Jul 10 06:01:54 PM PDT 24 50133331 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.622996598 Jul 10 06:01:35 PM PDT 24 Jul 10 06:01:51 PM PDT 24 1110263407 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2359521601 Jul 10 06:01:33 PM PDT 24 Jul 10 06:01:38 PM PDT 24 376531207 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3417208298 Jul 10 06:01:48 PM PDT 24 Jul 10 06:01:57 PM PDT 24 106293422 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.670704382 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:58 PM PDT 24 199290493 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3537558992 Jul 10 06:01:43 PM PDT 24 Jul 10 06:01:46 PM PDT 24 61137229 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4005566096 Jul 10 06:01:45 PM PDT 24 Jul 10 06:01:48 PM PDT 24 52884126 ps
T104 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.704639888 Jul 10 06:01:43 PM PDT 24 Jul 10 06:01:49 PM PDT 24 814441696 ps
T1069 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1502650456 Jul 10 06:02:02 PM PDT 24 Jul 10 06:02:04 PM PDT 24 11381193 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.150338679 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:51 PM PDT 24 370505032 ps
T1071 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4217914418 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:58 PM PDT 24 869105111 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3400049749 Jul 10 06:01:45 PM PDT 24 Jul 10 06:01:47 PM PDT 24 56143766 ps
T1073 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1823542871 Jul 10 06:01:59 PM PDT 24 Jul 10 06:02:02 PM PDT 24 24184626 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2038321708 Jul 10 06:01:31 PM PDT 24 Jul 10 06:01:35 PM PDT 24 60407985 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2558578720 Jul 10 06:01:59 PM PDT 24 Jul 10 06:02:04 PM PDT 24 439345583 ps
T1076 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3034579973 Jul 10 06:02:03 PM PDT 24 Jul 10 06:02:05 PM PDT 24 18396740 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.740315882 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:50 PM PDT 24 100850954 ps
T1078 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1189610784 Jul 10 06:01:54 PM PDT 24 Jul 10 06:02:00 PM PDT 24 252312126 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2506018988 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:52 PM PDT 24 14864073 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3996175455 Jul 10 06:01:58 PM PDT 24 Jul 10 06:02:00 PM PDT 24 49407895 ps
T1081 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1588952589 Jul 10 06:01:40 PM PDT 24 Jul 10 06:01:43 PM PDT 24 105593829 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1047644422 Jul 10 06:01:32 PM PDT 24 Jul 10 06:01:43 PM PDT 24 2522157094 ps
T1083 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2945331862 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:53 PM PDT 24 36564494 ps
T1084 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3201164997 Jul 10 06:01:54 PM PDT 24 Jul 10 06:01:58 PM PDT 24 36574943 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.829968335 Jul 10 06:01:31 PM PDT 24 Jul 10 06:01:35 PM PDT 24 990315185 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.600827104 Jul 10 06:01:25 PM PDT 24 Jul 10 06:01:30 PM PDT 24 68437148 ps
T1087 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.750474224 Jul 10 06:02:05 PM PDT 24 Jul 10 06:02:07 PM PDT 24 10805272 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3611260987 Jul 10 06:01:31 PM PDT 24 Jul 10 06:01:33 PM PDT 24 13084852 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1441495455 Jul 10 06:01:37 PM PDT 24 Jul 10 06:01:59 PM PDT 24 315800612 ps
T1090 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3675918335 Jul 10 06:02:00 PM PDT 24 Jul 10 06:02:02 PM PDT 24 24291314 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3221226438 Jul 10 06:01:41 PM PDT 24 Jul 10 06:01:44 PM PDT 24 302189507 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.44024660 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:51 PM PDT 24 20300528 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2599516438 Jul 10 06:01:27 PM PDT 24 Jul 10 06:01:32 PM PDT 24 489863685 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3008744457 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:43 PM PDT 24 60700870 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4081841154 Jul 10 06:01:54 PM PDT 24 Jul 10 06:02:04 PM PDT 24 4095298200 ps
T1096 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3798814903 Jul 10 06:01:45 PM PDT 24 Jul 10 06:01:48 PM PDT 24 81528357 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.497939242 Jul 10 06:01:42 PM PDT 24 Jul 10 06:01:44 PM PDT 24 108105032 ps
T1098 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1697723770 Jul 10 06:01:59 PM PDT 24 Jul 10 06:02:01 PM PDT 24 39641882 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.743947413 Jul 10 06:01:40 PM PDT 24 Jul 10 06:02:21 PM PDT 24 2742340019 ps
T1100 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4093975776 Jul 10 06:02:00 PM PDT 24 Jul 10 06:02:02 PM PDT 24 33859506 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.582700673 Jul 10 06:01:45 PM PDT 24 Jul 10 06:01:47 PM PDT 24 18711909 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.584797331 Jul 10 06:01:57 PM PDT 24 Jul 10 06:02:16 PM PDT 24 290338198 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1382966343 Jul 10 06:01:27 PM PDT 24 Jul 10 06:01:31 PM PDT 24 387084878 ps
T1104 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.320615981 Jul 10 06:02:00 PM PDT 24 Jul 10 06:02:02 PM PDT 24 25952913 ps
T1105 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1469727279 Jul 10 06:02:03 PM PDT 24 Jul 10 06:02:05 PM PDT 24 13339231 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3243973517 Jul 10 06:01:29 PM PDT 24 Jul 10 06:01:32 PM PDT 24 100761935 ps
T1107 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.996866404 Jul 10 06:02:01 PM PDT 24 Jul 10 06:02:07 PM PDT 24 69056614 ps
T1108 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3040092101 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:53 PM PDT 24 110570103 ps
T1109 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.130100591 Jul 10 06:02:02 PM PDT 24 Jul 10 06:02:04 PM PDT 24 12893500 ps
T158 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3386111689 Jul 10 06:01:55 PM PDT 24 Jul 10 06:02:21 PM PDT 24 1074316639 ps
T1110 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3226204967 Jul 10 06:01:58 PM PDT 24 Jul 10 06:02:00 PM PDT 24 36201062 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1672976849 Jul 10 06:01:27 PM PDT 24 Jul 10 06:01:32 PM PDT 24 1000103732 ps
T1112 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3285307131 Jul 10 06:01:59 PM PDT 24 Jul 10 06:02:02 PM PDT 24 29223783 ps
T1113 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.573792160 Jul 10 06:02:04 PM PDT 24 Jul 10 06:02:06 PM PDT 24 13679853 ps
T1114 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1188235437 Jul 10 06:02:18 PM PDT 24 Jul 10 06:02:20 PM PDT 24 20925812 ps
T1115 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1042131802 Jul 10 06:01:50 PM PDT 24 Jul 10 06:01:53 PM PDT 24 48996005 ps
T1116 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2102169434 Jul 10 06:02:07 PM PDT 24 Jul 10 06:02:08 PM PDT 24 17909939 ps
T89 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2424604260 Jul 10 06:01:33 PM PDT 24 Jul 10 06:01:36 PM PDT 24 565965448 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3884860628 Jul 10 06:01:46 PM PDT 24 Jul 10 06:01:51 PM PDT 24 575099725 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1989522969 Jul 10 06:01:43 PM PDT 24 Jul 10 06:01:49 PM PDT 24 328802000 ps
T1119 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1338943644 Jul 10 06:01:55 PM PDT 24 Jul 10 06:02:00 PM PDT 24 166010430 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4120276736 Jul 10 06:01:34 PM PDT 24 Jul 10 06:01:37 PM PDT 24 59705823 ps
T1121 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2210827647 Jul 10 06:01:41 PM PDT 24 Jul 10 06:01:44 PM PDT 24 53291412 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1157667493 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:51 PM PDT 24 72460901 ps
T1123 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2091562480 Jul 10 06:01:54 PM PDT 24 Jul 10 06:01:59 PM PDT 24 108280450 ps
T1124 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2854480827 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:56 PM PDT 24 15770829 ps
T1125 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3011912393 Jul 10 06:02:06 PM PDT 24 Jul 10 06:02:08 PM PDT 24 35383856 ps
T1126 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.527443187 Jul 10 06:02:04 PM PDT 24 Jul 10 06:02:06 PM PDT 24 13339890 ps
T1127 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.94616059 Jul 10 06:01:47 PM PDT 24 Jul 10 06:01:52 PM PDT 24 63009446 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1377237719 Jul 10 06:01:36 PM PDT 24 Jul 10 06:01:44 PM PDT 24 309490558 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3189112552 Jul 10 06:01:52 PM PDT 24 Jul 10 06:02:09 PM PDT 24 574702548 ps
T1130 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.208947044 Jul 10 06:02:02 PM PDT 24 Jul 10 06:02:04 PM PDT 24 16642955 ps
T1131 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1805617635 Jul 10 06:01:29 PM PDT 24 Jul 10 06:01:47 PM PDT 24 297388333 ps
T1132 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.875318220 Jul 10 06:01:51 PM PDT 24 Jul 10 06:01:55 PM PDT 24 60992620 ps
T1133 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3805344564 Jul 10 06:01:49 PM PDT 24 Jul 10 06:01:52 PM PDT 24 19554880 ps
T1134 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4018256309 Jul 10 06:01:32 PM PDT 24 Jul 10 06:01:34 PM PDT 24 13211047 ps
T1135 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1422685863 Jul 10 06:01:35 PM PDT 24 Jul 10 06:02:02 PM PDT 24 3734818812 ps
T1136 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2507740052 Jul 10 06:02:02 PM PDT 24 Jul 10 06:02:04 PM PDT 24 22115091 ps
T1137 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4235430405 Jul 10 06:01:55 PM PDT 24 Jul 10 06:02:00 PM PDT 24 43709219 ps
T1138 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.322246950 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:57 PM PDT 24 156542670 ps
T1139 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1298966470 Jul 10 06:01:51 PM PDT 24 Jul 10 06:01:55 PM PDT 24 34845370 ps
T1140 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2581274470 Jul 10 06:01:43 PM PDT 24 Jul 10 06:01:46 PM PDT 24 149325643 ps
T1141 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2643896857 Jul 10 06:02:00 PM PDT 24 Jul 10 06:02:04 PM PDT 24 85386757 ps
T1142 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3565138881 Jul 10 06:01:37 PM PDT 24 Jul 10 06:01:41 PM PDT 24 48320252 ps
T1143 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4060472027 Jul 10 06:02:05 PM PDT 24 Jul 10 06:02:07 PM PDT 24 12979123 ps
T1144 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3943484165 Jul 10 06:01:52 PM PDT 24 Jul 10 06:01:56 PM PDT 24 790272340 ps
T1145 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3539180528 Jul 10 06:01:38 PM PDT 24 Jul 10 06:01:40 PM PDT 24 107937980 ps
T1146 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2167880617 Jul 10 06:01:33 PM PDT 24 Jul 10 06:01:36 PM PDT 24 27199253 ps
T1147 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4143302442 Jul 10 06:01:53 PM PDT 24 Jul 10 06:01:57 PM PDT 24 85693590 ps
T1148 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1543143410 Jul 10 06:02:03 PM PDT 24 Jul 10 06:02:05 PM PDT 24 14394443 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3106099544 Jul 10 06:01:34 PM PDT 24 Jul 10 06:01:44 PM PDT 24 304350610 ps

Test location /workspace/coverage/default/12.spi_device_stress_all.2221744558
Short name T6
Test name
Test status
Simulation time 47525696532 ps
CPU time 165.95 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:45:15 PM PDT 24
Peak memory 269856 kb
Host smart-685fceba-b467-45f1-b38b-d83372808d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221744558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2221744558
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3169420881
Short name T18
Test name
Test status
Simulation time 18351204152 ps
CPU time 177.69 seconds
Started Jul 10 05:42:51 PM PDT 24
Finished Jul 10 05:45:50 PM PDT 24
Peak memory 284076 kb
Host smart-ac2120ef-c67e-4f14-a293-e004c666e3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169420881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3169420881
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3223115150
Short name T7
Test name
Test status
Simulation time 9130124176 ps
CPU time 30.39 seconds
Started Jul 10 05:46:01 PM PDT 24
Finished Jul 10 05:46:32 PM PDT 24
Peak memory 250240 kb
Host smart-3b5ba702-adcb-46a1-92c3-2ca52a510240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223115150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3223115150
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2755236162
Short name T33
Test name
Test status
Simulation time 3229118004 ps
CPU time 60.48 seconds
Started Jul 10 05:45:42 PM PDT 24
Finished Jul 10 05:46:43 PM PDT 24
Peak memory 250384 kb
Host smart-870d5a9b-b06b-4da3-bde5-c2ff612f2dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755236162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2755236162
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.71675703
Short name T110
Test name
Test status
Simulation time 1249032622 ps
CPU time 15.1 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 216324 kb
Host smart-24e2f8dd-49e1-409f-ae5c-e4981ad989f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71675703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.71675703
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.822414270
Short name T34
Test name
Test status
Simulation time 72096326086 ps
CPU time 326.81 seconds
Started Jul 10 05:41:24 PM PDT 24
Finished Jul 10 05:46:52 PM PDT 24
Peak memory 275160 kb
Host smart-f3976fe8-86c8-4730-ba2f-6b6dc31aa6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822414270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
822414270
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4138682907
Short name T75
Test name
Test status
Simulation time 39176434 ps
CPU time 0.78 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 217052 kb
Host smart-e531272d-0e20-49e6-9307-77e0274bc15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138682907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4138682907
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2131116140
Short name T182
Test name
Test status
Simulation time 145835127660 ps
CPU time 981.07 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:58:05 PM PDT 24
Peak memory 273508 kb
Host smart-d51d7ae7-8ffd-401f-bc71-5ad87575ffaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131116140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2131116140
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.319447251
Short name T184
Test name
Test status
Simulation time 28534478231 ps
CPU time 461.37 seconds
Started Jul 10 05:43:12 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 305684 kb
Host smart-4694a7b1-531a-4f60-835d-680e66bfcdeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319447251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.319447251
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2139951977
Short name T95
Test name
Test status
Simulation time 173934883 ps
CPU time 6.35 seconds
Started Jul 10 06:01:31 PM PDT 24
Finished Jul 10 06:01:39 PM PDT 24
Peak memory 215824 kb
Host smart-3c45c5c9-bade-49c9-b98d-2570db1dffe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139951977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
139951977
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.763975540
Short name T16
Test name
Test status
Simulation time 38011486 ps
CPU time 1.04 seconds
Started Jul 10 05:41:17 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 236344 kb
Host smart-9c28381c-84ad-475a-b98a-acd05ecffa4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763975540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.763975540
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1393778412
Short name T46
Test name
Test status
Simulation time 7491669295 ps
CPU time 7.91 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:45:52 PM PDT 24
Peak memory 225688 kb
Host smart-2b18b4de-a625-4b70-a7c1-d111565d03dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393778412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1393778412
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3304670288
Short name T206
Test name
Test status
Simulation time 37517831572 ps
CPU time 255.34 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 266176 kb
Host smart-2a7c1c27-7963-46ca-a6d6-dc30561a0d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304670288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3304670288
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2085343267
Short name T35
Test name
Test status
Simulation time 148137709393 ps
CPU time 377.15 seconds
Started Jul 10 05:43:58 PM PDT 24
Finished Jul 10 05:50:16 PM PDT 24
Peak memory 267796 kb
Host smart-d1c17dd8-f38b-4e3f-bd50-cca4e151bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085343267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2085343267
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2168534966
Short name T163
Test name
Test status
Simulation time 50358593338 ps
CPU time 82.77 seconds
Started Jul 10 05:44:57 PM PDT 24
Finished Jul 10 05:46:21 PM PDT 24
Peak memory 266692 kb
Host smart-aaaa0981-9228-4849-9565-2f7cdf646362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168534966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2168534966
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1815970471
Short name T17
Test name
Test status
Simulation time 17310584385 ps
CPU time 211.84 seconds
Started Jul 10 05:46:12 PM PDT 24
Finished Jul 10 05:49:45 PM PDT 24
Peak memory 266056 kb
Host smart-a2a4cb8d-6388-4d16-be62-a2c311d7312f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815970471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1815970471
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2298442038
Short name T86
Test name
Test status
Simulation time 16713251 ps
CPU time 0.93 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:45 PM PDT 24
Peak memory 207096 kb
Host smart-22f88344-d5ea-4149-8914-3d13258e4b4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298442038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2298442038
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3986216420
Short name T191
Test name
Test status
Simulation time 12808823838 ps
CPU time 208.53 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:46:29 PM PDT 24
Peak memory 267132 kb
Host smart-8f19162d-05dd-4998-a455-56728e3d648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986216420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3986216420
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.494282001
Short name T40
Test name
Test status
Simulation time 67375124955 ps
CPU time 483 seconds
Started Jul 10 05:46:12 PM PDT 24
Finished Jul 10 05:54:16 PM PDT 24
Peak memory 264776 kb
Host smart-d3947093-b609-4ad6-aa76-130b9f974862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494282001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.494282001
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3242380349
Short name T412
Test name
Test status
Simulation time 55198007 ps
CPU time 1.03 seconds
Started Jul 10 05:41:15 PM PDT 24
Finished Jul 10 05:41:16 PM PDT 24
Peak memory 218964 kb
Host smart-2b3fae39-a24d-4f51-ae0c-e40708fc3e40
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242380349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3242380349
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3454631372
Short name T53
Test name
Test status
Simulation time 9562729125 ps
CPU time 78.12 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:43:41 PM PDT 24
Peak memory 250384 kb
Host smart-4a299ab4-9f68-428a-ab68-5350f04f34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454631372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3454631372
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3118515245
Short name T130
Test name
Test status
Simulation time 58240447155 ps
CPU time 550.15 seconds
Started Jul 10 05:41:47 PM PDT 24
Finished Jul 10 05:50:58 PM PDT 24
Peak memory 264772 kb
Host smart-5debfc12-e329-4d79-a3d1-688c1d8e7a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118515245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3118515245
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1119132179
Short name T205
Test name
Test status
Simulation time 73670588503 ps
CPU time 520.36 seconds
Started Jul 10 05:43:34 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 274548 kb
Host smart-2580d540-49d0-4b2f-a895-3909cb63677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119132179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1119132179
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4142094432
Short name T275
Test name
Test status
Simulation time 75808745716 ps
CPU time 516.86 seconds
Started Jul 10 05:44:37 PM PDT 24
Finished Jul 10 05:53:14 PM PDT 24
Peak memory 266392 kb
Host smart-dec0a506-b61d-44cc-b876-3fdea8f4d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142094432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4142094432
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.645948368
Short name T295
Test name
Test status
Simulation time 19766626290 ps
CPU time 33.31 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:44:12 PM PDT 24
Peak memory 217512 kb
Host smart-bc51e30f-a72b-4468-9f93-44bf6c3b0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645948368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.645948368
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3593554167
Short name T207
Test name
Test status
Simulation time 219361247380 ps
CPU time 423.38 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:53:11 PM PDT 24
Peak memory 257496 kb
Host smart-48d9f326-a123-4df0-9e17-87caa7c85e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593554167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3593554167
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3380454630
Short name T64
Test name
Test status
Simulation time 17641051 ps
CPU time 0.75 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:42:35 PM PDT 24
Peak memory 205732 kb
Host smart-24d087a3-5da1-4592-a5ff-4ac084f239ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380454630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3380454630
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4200592625
Short name T112
Test name
Test status
Simulation time 1050993358 ps
CPU time 23.07 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:02:14 PM PDT 24
Peak memory 215572 kb
Host smart-2f95d5ab-9467-409a-842a-010b572a1044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200592625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4200592625
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.27383027
Short name T177
Test name
Test status
Simulation time 255060980972 ps
CPU time 555.32 seconds
Started Jul 10 05:46:25 PM PDT 24
Finished Jul 10 05:55:41 PM PDT 24
Peak memory 271900 kb
Host smart-9235c31c-4bc5-40b2-a05a-41cd259451c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27383027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.27383027
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2646084103
Short name T20
Test name
Test status
Simulation time 26624796667 ps
CPU time 330.64 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 282512 kb
Host smart-d358b552-e802-407f-9310-9ee969e9c79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646084103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2646084103
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1961195088
Short name T288
Test name
Test status
Simulation time 51722279267 ps
CPU time 266.65 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 265464 kb
Host smart-6d0fec42-2ded-4093-bb96-5a2984ff4040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961195088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1961195088
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.704639888
Short name T104
Test name
Test status
Simulation time 814441696 ps
CPU time 4.41 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 215772 kb
Host smart-a68a5507-dbb3-49ab-b835-52f87a3b056c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704639888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.704639888
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1356637660
Short name T2
Test name
Test status
Simulation time 107213202075 ps
CPU time 137.03 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:45:30 PM PDT 24
Peak memory 254744 kb
Host smart-a8531158-b3cd-4791-b070-23f9668f94c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356637660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1356637660
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2485461682
Short name T287
Test name
Test status
Simulation time 13311904595 ps
CPU time 161.93 seconds
Started Jul 10 05:44:15 PM PDT 24
Finished Jul 10 05:46:59 PM PDT 24
Peak memory 257840 kb
Host smart-4bb36f0e-dfbe-432d-b390-28b4f8888074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485461682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2485461682
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2584121250
Short name T280
Test name
Test status
Simulation time 75991746533 ps
CPU time 284.23 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 274596 kb
Host smart-eda3a098-02cd-41e7-a091-228cfe7a1e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584121250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2584121250
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1610769617
Short name T67
Test name
Test status
Simulation time 597899401 ps
CPU time 9.65 seconds
Started Jul 10 05:43:13 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 225556 kb
Host smart-1bb7c8c5-577b-4963-83bf-6f03761be165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610769617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1610769617
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4047199868
Short name T293
Test name
Test status
Simulation time 196781557 ps
CPU time 9.92 seconds
Started Jul 10 05:46:27 PM PDT 24
Finished Jul 10 05:46:38 PM PDT 24
Peak memory 241916 kb
Host smart-f2032b43-bd68-4450-98f7-2bbb4b43e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047199868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4047199868
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3600570171
Short name T152
Test name
Test status
Simulation time 380343079448 ps
CPU time 683.61 seconds
Started Jul 10 05:42:04 PM PDT 24
Finished Jul 10 05:53:29 PM PDT 24
Peak memory 291396 kb
Host smart-2daf5234-6e19-442c-897b-9146898f6682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600570171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3600570171
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3715288185
Short name T160
Test name
Test status
Simulation time 2684994364 ps
CPU time 51.86 seconds
Started Jul 10 05:41:22 PM PDT 24
Finished Jul 10 05:42:14 PM PDT 24
Peak memory 250256 kb
Host smart-77f3fed1-01b1-465f-862b-36bfce218f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715288185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3715288185
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2503636799
Short name T179
Test name
Test status
Simulation time 545936001 ps
CPU time 4.73 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:04 PM PDT 24
Peak memory 233748 kb
Host smart-0c1e558e-481c-47b0-aa83-c2bd9e4f55fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503636799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2503636799
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2674162380
Short name T79
Test name
Test status
Simulation time 7891854215 ps
CPU time 29.21 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:52 PM PDT 24
Peak memory 241852 kb
Host smart-84e68f79-a505-4007-bb25-12d7791ca8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674162380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2674162380
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3386111689
Short name T158
Test name
Test status
Simulation time 1074316639 ps
CPU time 24.46 seconds
Started Jul 10 06:01:55 PM PDT 24
Finished Jul 10 06:02:21 PM PDT 24
Peak memory 215552 kb
Host smart-4abd2f2c-4d3c-48e6-9539-80d574f68bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386111689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3386111689
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1719297304
Short name T105
Test name
Test status
Simulation time 143950827 ps
CPU time 4.69 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215720 kb
Host smart-b4f1aac5-b4b5-4598-93c2-54cb1dbb6b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719297304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
719297304
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1737488030
Short name T311
Test name
Test status
Simulation time 1352496745 ps
CPU time 2.66 seconds
Started Jul 10 05:41:09 PM PDT 24
Finished Jul 10 05:41:13 PM PDT 24
Peak memory 217244 kb
Host smart-2c2e9f98-aad0-4352-a031-8abdd8a3fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737488030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1737488030
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.207707241
Short name T240
Test name
Test status
Simulation time 150319909561 ps
CPU time 362.73 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 253476 kb
Host smart-ed3bae2c-eed9-4521-8229-6af41c250455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207707241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.207707241
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1551708630
Short name T171
Test name
Test status
Simulation time 49140829150 ps
CPU time 411.62 seconds
Started Jul 10 05:42:53 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 257552 kb
Host smart-5549543e-b6b6-46a2-a27a-c34a7ec64e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551708630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1551708630
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.846960791
Short name T197
Test name
Test status
Simulation time 188252865631 ps
CPU time 393 seconds
Started Jul 10 05:43:08 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 264088 kb
Host smart-97d96026-0738-488a-b796-9f5312f0da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846960791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.846960791
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.468118773
Short name T443
Test name
Test status
Simulation time 6689118778 ps
CPU time 24.41 seconds
Started Jul 10 05:41:26 PM PDT 24
Finished Jul 10 05:41:51 PM PDT 24
Peak memory 217484 kb
Host smart-b4dd5182-2630-4b9e-8880-985cbb13f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468118773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.468118773
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2982403475
Short name T165
Test name
Test status
Simulation time 51877342799 ps
CPU time 88.17 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:44:51 PM PDT 24
Peak memory 242180 kb
Host smart-f0bd4afc-e050-4c33-b576-3d621f91f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982403475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2982403475
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1993157584
Short name T289
Test name
Test status
Simulation time 1023050300 ps
CPU time 8.19 seconds
Started Jul 10 05:45:12 PM PDT 24
Finished Jul 10 05:45:21 PM PDT 24
Peak memory 225560 kb
Host smart-7b6751d2-4bae-43d6-82ae-eeeafaf433ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993157584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1993157584
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2561347441
Short name T310
Test name
Test status
Simulation time 28918091509 ps
CPU time 286.46 seconds
Started Jul 10 05:41:57 PM PDT 24
Finished Jul 10 05:46:44 PM PDT 24
Peak memory 266772 kb
Host smart-10b0653b-441a-457c-a115-cfd2af42e3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561347441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2561347441
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1353119553
Short name T88
Test name
Test status
Simulation time 87773535 ps
CPU time 1.24 seconds
Started Jul 10 06:01:29 PM PDT 24
Finished Jul 10 06:01:31 PM PDT 24
Peak memory 207380 kb
Host smart-041896a9-26ae-483d-8af7-79b256550313
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353119553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1353119553
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1207045781
Short name T1043
Test name
Test status
Simulation time 357499333 ps
CPU time 7.55 seconds
Started Jul 10 06:01:27 PM PDT 24
Finished Jul 10 06:01:36 PM PDT 24
Peak memory 215552 kb
Host smart-f3055ff1-aa2a-49eb-993d-78a98fbff547
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207045781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1207045781
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.333101720
Short name T1022
Test name
Test status
Simulation time 420320368 ps
CPU time 12.89 seconds
Started Jul 10 06:01:30 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 215484 kb
Host smart-ab2020af-f897-4274-a848-b0ee1de4672c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333101720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.333101720
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3243973517
Short name T1106
Test name
Test status
Simulation time 100761935 ps
CPU time 2.18 seconds
Started Jul 10 06:01:29 PM PDT 24
Finished Jul 10 06:01:32 PM PDT 24
Peak memory 215616 kb
Host smart-26fed685-33af-4a9f-96fd-245ddb93ed21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243973517 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3243973517
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1382966343
Short name T1103
Test name
Test status
Simulation time 387084878 ps
CPU time 2.6 seconds
Started Jul 10 06:01:27 PM PDT 24
Finished Jul 10 06:01:31 PM PDT 24
Peak memory 215548 kb
Host smart-6e3cfc97-c601-46e2-bee0-bc4b3aaa7bc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382966343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
382966343
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4429737
Short name T1016
Test name
Test status
Simulation time 14592589 ps
CPU time 0.76 seconds
Started Jul 10 06:01:30 PM PDT 24
Finished Jul 10 06:01:31 PM PDT 24
Peak memory 203816 kb
Host smart-042796cb-ff4b-47fa-9cb5-268a76258100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4429737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4429737
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2619364587
Short name T119
Test name
Test status
Simulation time 38223372 ps
CPU time 1.47 seconds
Started Jul 10 06:01:30 PM PDT 24
Finished Jul 10 06:01:32 PM PDT 24
Peak memory 215252 kb
Host smart-1484fe42-732a-40c9-ad91-dd001d22ff4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619364587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2619364587
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1728513250
Short name T1039
Test name
Test status
Simulation time 13181260 ps
CPU time 0.72 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 203860 kb
Host smart-0cab43fe-5825-4864-9034-423f975fa84c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728513250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1728513250
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1672976849
Short name T1111
Test name
Test status
Simulation time 1000103732 ps
CPU time 4.15 seconds
Started Jul 10 06:01:27 PM PDT 24
Finished Jul 10 06:01:32 PM PDT 24
Peak memory 215552 kb
Host smart-faac90a0-05d1-4da8-b036-a51e1907456a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672976849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1672976849
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2599516438
Short name T1093
Test name
Test status
Simulation time 489863685 ps
CPU time 3.36 seconds
Started Jul 10 06:01:27 PM PDT 24
Finished Jul 10 06:01:32 PM PDT 24
Peak memory 215844 kb
Host smart-bbf86e18-96c8-49fe-b946-2ffd1aee18cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599516438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
599516438
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4145378325
Short name T97
Test name
Test status
Simulation time 1336925502 ps
CPU time 7.62 seconds
Started Jul 10 06:01:27 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 215552 kb
Host smart-677e0ed8-eedb-4e9f-b613-0678845930bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145378325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4145378325
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3599894024
Short name T1055
Test name
Test status
Simulation time 1350404624 ps
CPU time 8.1 seconds
Started Jul 10 06:01:31 PM PDT 24
Finished Jul 10 06:01:39 PM PDT 24
Peak memory 215580 kb
Host smart-341a74f2-1fa1-4199-bb2e-4d99ef4a0a9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599894024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3599894024
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.622996598
Short name T1063
Test name
Test status
Simulation time 1110263407 ps
CPU time 14.21 seconds
Started Jul 10 06:01:35 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 207404 kb
Host smart-dfbe6e8d-dd95-4a64-a346-39359647aa71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622996598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.622996598
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2424604260
Short name T89
Test name
Test status
Simulation time 565965448 ps
CPU time 1.24 seconds
Started Jul 10 06:01:33 PM PDT 24
Finished Jul 10 06:01:36 PM PDT 24
Peak memory 207344 kb
Host smart-32252883-057c-4b55-bb17-461c8f991bd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424604260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2424604260
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2167880617
Short name T1146
Test name
Test status
Simulation time 27199253 ps
CPU time 1.75 seconds
Started Jul 10 06:01:33 PM PDT 24
Finished Jul 10 06:01:36 PM PDT 24
Peak memory 216532 kb
Host smart-bc609473-043b-4a2d-9f10-3c97e8d26bdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167880617 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2167880617
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2038321708
Short name T1074
Test name
Test status
Simulation time 60407985 ps
CPU time 1.91 seconds
Started Jul 10 06:01:31 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 207296 kb
Host smart-adae60f2-d780-4ab7-81e8-7b9f98662885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038321708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
038321708
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2568906119
Short name T1017
Test name
Test status
Simulation time 61819262 ps
CPU time 0.84 seconds
Started Jul 10 06:01:29 PM PDT 24
Finished Jul 10 06:01:31 PM PDT 24
Peak memory 204200 kb
Host smart-cdf73619-feb5-4cc1-ae5d-af6f5b1f9c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568906119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
568906119
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4120276736
Short name T1120
Test name
Test status
Simulation time 59705823 ps
CPU time 1.37 seconds
Started Jul 10 06:01:34 PM PDT 24
Finished Jul 10 06:01:37 PM PDT 24
Peak memory 215464 kb
Host smart-529f61c4-d33f-4e8d-a875-a9d5a9a98f27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120276736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4120276736
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1134246513
Short name T1037
Test name
Test status
Simulation time 18898713 ps
CPU time 0.69 seconds
Started Jul 10 06:01:35 PM PDT 24
Finished Jul 10 06:01:38 PM PDT 24
Peak memory 204252 kb
Host smart-134f7dfb-d7f2-473d-b4f1-ace574de3483
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134246513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1134246513
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.829968335
Short name T1085
Test name
Test status
Simulation time 990315185 ps
CPU time 1.98 seconds
Started Jul 10 06:01:31 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 215480 kb
Host smart-00cd0083-884c-477b-8b66-24df289c43e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829968335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.829968335
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.600827104
Short name T1086
Test name
Test status
Simulation time 68437148 ps
CPU time 4.35 seconds
Started Jul 10 06:01:25 PM PDT 24
Finished Jul 10 06:01:30 PM PDT 24
Peak memory 215764 kb
Host smart-826ccc4e-ee7f-4c91-8f2a-7a8de92df43f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600827104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.600827104
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1805617635
Short name T1131
Test name
Test status
Simulation time 297388333 ps
CPU time 17.67 seconds
Started Jul 10 06:01:29 PM PDT 24
Finished Jul 10 06:01:47 PM PDT 24
Peak memory 215508 kb
Host smart-2863962b-8293-4c40-a1eb-8825319d3c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805617635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1805617635
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3884860628
Short name T1117
Test name
Test status
Simulation time 575099725 ps
CPU time 3.83 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 217736 kb
Host smart-5d6900c8-96e3-471b-b0e0-d59edd6dbd44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884860628 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3884860628
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2945331862
Short name T1083
Test name
Test status
Simulation time 36564494 ps
CPU time 2.41 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 215440 kb
Host smart-fd57e4cf-e7c6-452b-8d9f-2d46255e130f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945331862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2945331862
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2256443509
Short name T1041
Test name
Test status
Simulation time 41013248 ps
CPU time 0.78 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 204348 kb
Host smart-8511599d-8422-4eff-9e11-3c612ba226b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256443509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2256443509
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1042131802
Short name T1115
Test name
Test status
Simulation time 48996005 ps
CPU time 1.74 seconds
Started Jul 10 06:01:50 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 215892 kb
Host smart-de1ca7ae-aaa9-47cc-bd01-c68d1f63216b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042131802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1042131802
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3925086564
Short name T101
Test name
Test status
Simulation time 396538669 ps
CPU time 4.72 seconds
Started Jul 10 06:01:50 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 216688 kb
Host smart-b49475c4-34e2-4445-9277-934ce54e661c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925086564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3925086564
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1214267545
Short name T1049
Test name
Test status
Simulation time 422097247 ps
CPU time 4.19 seconds
Started Jul 10 06:01:50 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 218128 kb
Host smart-a19757b3-2f8a-4991-a3e3-c48676414749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214267545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1214267545
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4096898775
Short name T116
Test name
Test status
Simulation time 93107299 ps
CPU time 1.3 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 207324 kb
Host smart-e9a7cbda-9c27-4741-998a-174c4a542a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096898775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4096898775
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.44024660
Short name T1092
Test name
Test status
Simulation time 20300528 ps
CPU time 0.69 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 204296 kb
Host smart-383316ab-b143-4e4e-be64-87c6476b5c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44024660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.44024660
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4227098569
Short name T1050
Test name
Test status
Simulation time 89818802 ps
CPU time 2.94 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:54 PM PDT 24
Peak memory 215508 kb
Host smart-7866affd-d3c9-429c-864d-8e666d8a1c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227098569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4227098569
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.150338679
Short name T1070
Test name
Test status
Simulation time 370505032 ps
CPU time 2.78 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 215764 kb
Host smart-ea0f53be-b412-45d8-9076-a78172a8e69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150338679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.150338679
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2283687711
Short name T107
Test name
Test status
Simulation time 3291373431 ps
CPU time 15.08 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:02:03 PM PDT 24
Peak memory 216804 kb
Host smart-d9de4011-e7ef-44a3-b7d0-43acf1a40d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283687711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2283687711
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.740315882
Short name T1077
Test name
Test status
Simulation time 100850954 ps
CPU time 1.73 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 215668 kb
Host smart-dbdd2a46-6150-4292-9b62-697a430ea7f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740315882 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.740315882
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1596997201
Short name T1062
Test name
Test status
Simulation time 50133331 ps
CPU time 1.42 seconds
Started Jul 10 06:01:51 PM PDT 24
Finished Jul 10 06:01:54 PM PDT 24
Peak memory 207172 kb
Host smart-06e1f07a-bd26-4bf0-b721-47e58f2898d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596997201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1596997201
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3000337762
Short name T1028
Test name
Test status
Simulation time 21357418 ps
CPU time 0.74 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 204016 kb
Host smart-871850ab-afb1-4033-8b08-18779b02dde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000337762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3000337762
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.94616059
Short name T1127
Test name
Test status
Simulation time 63009446 ps
CPU time 3.76 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 215532 kb
Host smart-0344d339-1f4b-4e0b-aa47-7721abf6fdf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94616059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.94616059
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4174220449
Short name T103
Test name
Test status
Simulation time 38310185 ps
CPU time 2.33 seconds
Started Jul 10 06:01:48 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 215748 kb
Host smart-0db2d851-b73c-422d-8f28-55ac8cb38c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174220449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4174220449
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.729215222
Short name T108
Test name
Test status
Simulation time 1167691316 ps
CPU time 7.89 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 215604 kb
Host smart-71a0105c-9d11-45d0-a2e3-52189dea44f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729215222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.729215222
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2498080976
Short name T1045
Test name
Test status
Simulation time 145890261 ps
CPU time 3.57 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:01:59 PM PDT 24
Peak memory 217544 kb
Host smart-9364a830-f744-4a63-baca-c5fb9d45b2b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498080976 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2498080976
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2535131662
Short name T121
Test name
Test status
Simulation time 86028661 ps
CPU time 2.18 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 215468 kb
Host smart-0bc1223b-5a17-4f3a-ad40-2541d1e4649d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535131662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2535131662
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3805344564
Short name T1133
Test name
Test status
Simulation time 19554880 ps
CPU time 0.78 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 204036 kb
Host smart-ae49f2a0-954b-46ef-bb62-bb52b50609cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805344564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3805344564
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1280957583
Short name T1060
Test name
Test status
Simulation time 60834268 ps
CPU time 1.84 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 215484 kb
Host smart-bd86ed81-3d0d-4e75-ab2c-43fe7815c1ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280957583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1280957583
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1157667493
Short name T1122
Test name
Test status
Simulation time 72460901 ps
CPU time 1.37 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:51 PM PDT 24
Peak memory 215780 kb
Host smart-713dcf4a-7367-4e6b-b211-2c2d808aea8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157667493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1157667493
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.670704382
Short name T1066
Test name
Test status
Simulation time 199290493 ps
CPU time 3.54 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 217136 kb
Host smart-31ea48bd-4886-4a90-81b4-d274edb9bd73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670704382 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.670704382
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3280059887
Short name T117
Test name
Test status
Simulation time 37968030 ps
CPU time 2.27 seconds
Started Jul 10 06:01:51 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 215592 kb
Host smart-de4c3676-f047-4cac-bc69-7f67b56afd73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280059887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3280059887
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1782084412
Short name T1031
Test name
Test status
Simulation time 13772460 ps
CPU time 0.73 seconds
Started Jul 10 06:01:52 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 204060 kb
Host smart-f825d2ed-3d9a-49c8-90dd-346de1bad485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782084412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1782084412
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1338943644
Short name T1119
Test name
Test status
Simulation time 166010430 ps
CPU time 2.89 seconds
Started Jul 10 06:01:55 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 215560 kb
Host smart-15b65640-ab60-4329-9766-50515045c5b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338943644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1338943644
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4143302442
Short name T1147
Test name
Test status
Simulation time 85693590 ps
CPU time 2.69 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 215780 kb
Host smart-613d57b1-c7ce-475a-b8ed-e62fb4517d32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143302442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4143302442
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4081841154
Short name T1095
Test name
Test status
Simulation time 4095298200 ps
CPU time 8.26 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 215888 kb
Host smart-dc4af769-a105-433b-9f45-19df75539e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081841154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4081841154
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3891026730
Short name T99
Test name
Test status
Simulation time 56706094 ps
CPU time 2.06 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 215552 kb
Host smart-84d334cf-7520-466d-b74e-b97affc56447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891026730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3891026730
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3201164997
Short name T1084
Test name
Test status
Simulation time 36574943 ps
CPU time 1.93 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 215500 kb
Host smart-a551894b-db21-4009-85eb-9667e1c2ae9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201164997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3201164997
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2854480827
Short name T1124
Test name
Test status
Simulation time 15770829 ps
CPU time 0.76 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 204052 kb
Host smart-4b2fceeb-d34c-45f6-9c9e-065a270d7d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854480827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2854480827
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.9876933
Short name T144
Test name
Test status
Simulation time 449716109 ps
CPU time 2.84 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 215432 kb
Host smart-4b735752-fd9e-41d6-ac45-f064b3aeac60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9876933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi
_device_same_csr_outstanding.9876933
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3943484165
Short name T1144
Test name
Test status
Simulation time 790272340 ps
CPU time 2.79 seconds
Started Jul 10 06:01:52 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 215764 kb
Host smart-b4d27501-989c-43ad-ace6-0c42ce565977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943484165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3943484165
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4217914418
Short name T1071
Test name
Test status
Simulation time 869105111 ps
CPU time 3.6 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 218868 kb
Host smart-7c141bbf-d0a9-45f5-a06b-331d157eba52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217914418 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4217914418
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.322246950
Short name T1138
Test name
Test status
Simulation time 156542670 ps
CPU time 1.3 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 207360 kb
Host smart-7cbd169f-8db8-44f6-838b-d7085bf3de16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322246950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.322246950
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.577871425
Short name T1033
Test name
Test status
Simulation time 17411877 ps
CPU time 0.75 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 204000 kb
Host smart-b589c310-36e7-4076-af3a-efad6baa8cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577871425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.577871425
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.875318220
Short name T1132
Test name
Test status
Simulation time 60992620 ps
CPU time 1.97 seconds
Started Jul 10 06:01:51 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 215536 kb
Host smart-fd4f449e-3e33-4ad1-b33a-d21fd33b5c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875318220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.875318220
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1189610784
Short name T1078
Test name
Test status
Simulation time 252312126 ps
CPU time 3.9 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 215720 kb
Host smart-ca644f19-8c0f-4e26-b44c-1fbfaf29f029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189610784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1189610784
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3437286272
Short name T100
Test name
Test status
Simulation time 1375599269 ps
CPU time 15.71 seconds
Started Jul 10 06:01:52 PM PDT 24
Finished Jul 10 06:02:09 PM PDT 24
Peak memory 215652 kb
Host smart-7e5ddedf-87f7-4447-84e4-bb4510955361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437286272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3437286272
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4235430405
Short name T1137
Test name
Test status
Simulation time 43709219 ps
CPU time 3.25 seconds
Started Jul 10 06:01:55 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 218456 kb
Host smart-4bf52075-bdbe-47df-8b03-de37516bf258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235430405 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4235430405
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1298966470
Short name T1139
Test name
Test status
Simulation time 34845370 ps
CPU time 2.41 seconds
Started Jul 10 06:01:51 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 215500 kb
Host smart-572a675b-15bb-4df2-9e22-e67f8d5e85fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298966470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1298966470
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1205456657
Short name T1019
Test name
Test status
Simulation time 44894202 ps
CPU time 0.75 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:56 PM PDT 24
Peak memory 204000 kb
Host smart-b14e5bb9-b28f-400b-b23b-b387f52abfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205456657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1205456657
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.868545511
Short name T1024
Test name
Test status
Simulation time 116958612 ps
CPU time 3.2 seconds
Started Jul 10 06:01:53 PM PDT 24
Finished Jul 10 06:01:58 PM PDT 24
Peak memory 215492 kb
Host smart-864e3cb5-164e-4ded-8e7d-0cf2303a4b9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868545511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.868545511
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2091562480
Short name T1123
Test name
Test status
Simulation time 108280450 ps
CPU time 2.82 seconds
Started Jul 10 06:01:54 PM PDT 24
Finished Jul 10 06:01:59 PM PDT 24
Peak memory 215712 kb
Host smart-ddc918f0-1db7-449c-b847-4e31ebf37b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091562480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2091562480
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3189112552
Short name T1129
Test name
Test status
Simulation time 574702548 ps
CPU time 15.87 seconds
Started Jul 10 06:01:52 PM PDT 24
Finished Jul 10 06:02:09 PM PDT 24
Peak memory 215612 kb
Host smart-c9294310-b78f-43fb-a602-a91450b555a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189112552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3189112552
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2558578720
Short name T1075
Test name
Test status
Simulation time 439345583 ps
CPU time 3.33 seconds
Started Jul 10 06:01:59 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 216840 kb
Host smart-09e73a99-2359-4325-ad66-9f5a483c4098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558578720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2558578720
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1493417848
Short name T1035
Test name
Test status
Simulation time 43700482 ps
CPU time 1.28 seconds
Started Jul 10 06:02:03 PM PDT 24
Finished Jul 10 06:02:05 PM PDT 24
Peak memory 207296 kb
Host smart-31ac8738-4ce2-4347-b663-8ff9b15f11d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493417848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1493417848
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3996175455
Short name T1080
Test name
Test status
Simulation time 49407895 ps
CPU time 0.74 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 203956 kb
Host smart-984fa0f5-c88e-49f6-9fe6-0e246711695d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996175455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3996175455
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3014513213
Short name T1027
Test name
Test status
Simulation time 291955072 ps
CPU time 3.99 seconds
Started Jul 10 06:02:01 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 215912 kb
Host smart-02d84990-7f4b-4c6f-aea4-c7016b60b841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014513213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3014513213
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2643896857
Short name T1141
Test name
Test status
Simulation time 85386757 ps
CPU time 2.27 seconds
Started Jul 10 06:02:00 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 215452 kb
Host smart-85cfe101-0f14-4f64-8be1-f3448f9d4ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643896857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2643896857
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.192997425
Short name T1048
Test name
Test status
Simulation time 388207705 ps
CPU time 19.52 seconds
Started Jul 10 06:02:01 PM PDT 24
Finished Jul 10 06:02:22 PM PDT 24
Peak memory 215728 kb
Host smart-3b492f95-0030-4f9d-975a-cdc9f341a37b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192997425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.192997425
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2276086915
Short name T1059
Test name
Test status
Simulation time 75738625 ps
CPU time 1.55 seconds
Started Jul 10 06:01:57 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 215604 kb
Host smart-41af528d-0d80-4e2a-860c-d922b1264976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276086915 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2276086915
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3973249467
Short name T1026
Test name
Test status
Simulation time 39059398 ps
CPU time 1.29 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:01 PM PDT 24
Peak memory 207268 kb
Host smart-61bdb420-e6bc-432c-9b28-5664559544ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973249467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3973249467
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1212472254
Short name T1014
Test name
Test status
Simulation time 55435961 ps
CPU time 0.76 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 204080 kb
Host smart-4f65b95e-bb55-46d4-8688-70f0c7e1f52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212472254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1212472254
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3285307131
Short name T1112
Test name
Test status
Simulation time 29223783 ps
CPU time 1.87 seconds
Started Jul 10 06:01:59 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 215504 kb
Host smart-c0ced574-377e-4b68-9b81-6aa7c269fc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285307131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3285307131
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.996866404
Short name T1107
Test name
Test status
Simulation time 69056614 ps
CPU time 4.79 seconds
Started Jul 10 06:02:01 PM PDT 24
Finished Jul 10 06:02:07 PM PDT 24
Peak memory 215880 kb
Host smart-7726c35f-e4f9-4c13-9090-ca11f7ade2ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996866404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.996866404
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.584797331
Short name T1102
Test name
Test status
Simulation time 290338198 ps
CPU time 18.21 seconds
Started Jul 10 06:01:57 PM PDT 24
Finished Jul 10 06:02:16 PM PDT 24
Peak memory 215488 kb
Host smart-03bebe21-77de-4af7-8c0e-71cf0e9f28a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584797331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.584797331
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1047644422
Short name T1082
Test name
Test status
Simulation time 2522157094 ps
CPU time 8.82 seconds
Started Jul 10 06:01:32 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 215548 kb
Host smart-b22aab6e-c98a-4f94-beca-d22883c2c014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047644422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1047644422
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1422685863
Short name T1135
Test name
Test status
Simulation time 3734818812 ps
CPU time 25.12 seconds
Started Jul 10 06:01:35 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 207348 kb
Host smart-61563770-abfb-4c47-b407-f80a9e46de45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422685863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1422685863
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3663410245
Short name T87
Test name
Test status
Simulation time 44622369 ps
CPU time 1.4 seconds
Started Jul 10 06:01:32 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 207288 kb
Host smart-433eba33-5c12-4a11-9add-d456da31a796
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663410245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3663410245
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2359521601
Short name T1064
Test name
Test status
Simulation time 376531207 ps
CPU time 3.85 seconds
Started Jul 10 06:01:33 PM PDT 24
Finished Jul 10 06:01:38 PM PDT 24
Peak memory 217468 kb
Host smart-e6a0c15e-fa19-4382-b071-1fd640394202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359521601 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2359521601
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2331293827
Short name T120
Test name
Test status
Simulation time 28151961 ps
CPU time 1.91 seconds
Started Jul 10 06:01:33 PM PDT 24
Finished Jul 10 06:01:36 PM PDT 24
Peak memory 215452 kb
Host smart-c19f13fa-fe9b-4189-8c5f-655922568bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331293827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
331293827
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4018256309
Short name T1134
Test name
Test status
Simulation time 13211047 ps
CPU time 0.77 seconds
Started Jul 10 06:01:32 PM PDT 24
Finished Jul 10 06:01:34 PM PDT 24
Peak memory 204024 kb
Host smart-bb2fd8d3-f74f-4b15-a5c9-d26a247c54f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018256309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
018256309
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1999192198
Short name T115
Test name
Test status
Simulation time 310118203 ps
CPU time 2.3 seconds
Started Jul 10 06:01:32 PM PDT 24
Finished Jul 10 06:01:35 PM PDT 24
Peak memory 215596 kb
Host smart-6b63e320-f69f-47a8-beb8-cea180f0f516
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999192198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1999192198
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3611260987
Short name T1088
Test name
Test status
Simulation time 13084852 ps
CPU time 0.68 seconds
Started Jul 10 06:01:31 PM PDT 24
Finished Jul 10 06:01:33 PM PDT 24
Peak memory 203892 kb
Host smart-046173e4-51ae-44db-8da3-13f903f822b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611260987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3611260987
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1091445321
Short name T1046
Test name
Test status
Simulation time 66817371 ps
CPU time 2.18 seconds
Started Jul 10 06:01:32 PM PDT 24
Finished Jul 10 06:01:36 PM PDT 24
Peak memory 215496 kb
Host smart-cab5b829-6887-4fa8-ae42-bb3628b0e23a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091445321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1091445321
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4040048888
Short name T1061
Test name
Test status
Simulation time 269685414 ps
CPU time 3.89 seconds
Started Jul 10 06:01:33 PM PDT 24
Finished Jul 10 06:01:38 PM PDT 24
Peak memory 216800 kb
Host smart-9a38ef08-8b03-40c6-bf82-33c072952729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040048888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
040048888
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1205025928
Short name T98
Test name
Test status
Simulation time 7013090942 ps
CPU time 14.79 seconds
Started Jul 10 06:01:35 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 215648 kb
Host smart-cba81592-759a-4be8-a941-7fd68d78830a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205025928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1205025928
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3675918335
Short name T1090
Test name
Test status
Simulation time 24291314 ps
CPU time 0.73 seconds
Started Jul 10 06:02:00 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 204332 kb
Host smart-cafa4c93-8137-4867-900d-248ee8a77309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675918335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3675918335
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3226204967
Short name T1110
Test name
Test status
Simulation time 36201062 ps
CPU time 0.75 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 203952 kb
Host smart-816d2feb-a23a-4441-9c7f-7e03267f4eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226204967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3226204967
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3034579973
Short name T1076
Test name
Test status
Simulation time 18396740 ps
CPU time 0.74 seconds
Started Jul 10 06:02:03 PM PDT 24
Finished Jul 10 06:02:05 PM PDT 24
Peak memory 204356 kb
Host smart-894ab675-b7bc-44c5-9a10-e993d1a1ca8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034579973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3034579973
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1823542871
Short name T1073
Test name
Test status
Simulation time 24184626 ps
CPU time 0.74 seconds
Started Jul 10 06:01:59 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 204040 kb
Host smart-05c23eaf-d8bd-4c50-8873-4045d137d9d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823542871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1823542871
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.320615981
Short name T1104
Test name
Test status
Simulation time 25952913 ps
CPU time 0.77 seconds
Started Jul 10 06:02:00 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 204056 kb
Host smart-de0a5cb0-a0b1-417b-882e-837a9873125e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320615981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.320615981
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2035930417
Short name T1030
Test name
Test status
Simulation time 65705058 ps
CPU time 0.73 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 204320 kb
Host smart-baedeb1a-fb6a-40bf-b571-148c590ff911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035930417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2035930417
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1697723770
Short name T1098
Test name
Test status
Simulation time 39641882 ps
CPU time 0.71 seconds
Started Jul 10 06:01:59 PM PDT 24
Finished Jul 10 06:02:01 PM PDT 24
Peak memory 204500 kb
Host smart-ed01ff7f-09ad-4c2b-8f05-340611ee66cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697723770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1697723770
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3562760629
Short name T1034
Test name
Test status
Simulation time 31576138 ps
CPU time 0.73 seconds
Started Jul 10 06:02:00 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 203972 kb
Host smart-055413be-d639-4b7d-b481-a3b2127959de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562760629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3562760629
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2094327400
Short name T1042
Test name
Test status
Simulation time 44968966 ps
CPU time 0.87 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 204060 kb
Host smart-91768872-8ea8-4a7a-b849-87f4be323b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094327400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2094327400
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4093975776
Short name T1100
Test name
Test status
Simulation time 33859506 ps
CPU time 0.74 seconds
Started Jul 10 06:02:00 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 203996 kb
Host smart-3da10fb6-1a10-4925-b151-10cf23d9616e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093975776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4093975776
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1441495455
Short name T1089
Test name
Test status
Simulation time 315800612 ps
CPU time 20.26 seconds
Started Jul 10 06:01:37 PM PDT 24
Finished Jul 10 06:01:59 PM PDT 24
Peak memory 216588 kb
Host smart-368dbe11-bbdb-4478-9a80-1240343b8495
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441495455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1441495455
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3981670947
Short name T1021
Test name
Test status
Simulation time 371796427 ps
CPU time 12 seconds
Started Jul 10 06:01:36 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 215440 kb
Host smart-98a10a83-fcbe-48b0-94b5-0bf43ee24dc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981670947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3981670947
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1989522969
Short name T1118
Test name
Test status
Simulation time 328802000 ps
CPU time 3.83 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 218752 kb
Host smart-27dd9c0c-7eea-4602-a731-d303c79e60d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989522969 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1989522969
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.365258004
Short name T1047
Test name
Test status
Simulation time 150125523 ps
CPU time 2.36 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:42 PM PDT 24
Peak memory 207304 kb
Host smart-388781e4-5284-45cd-8150-9bbb84f83ff9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365258004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.365258004
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.753810847
Short name T1056
Test name
Test status
Simulation time 35538800 ps
CPU time 0.77 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:40 PM PDT 24
Peak memory 204280 kb
Host smart-3b680a44-945a-415a-beb3-c5121f5928ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753810847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.753810847
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2581274470
Short name T1140
Test name
Test status
Simulation time 149325643 ps
CPU time 1.26 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:46 PM PDT 24
Peak memory 215560 kb
Host smart-a2bb7ae6-55e0-4b05-a80b-3dc0cafb0213
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581274470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2581274470
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1548593019
Short name T1051
Test name
Test status
Simulation time 12360124 ps
CPU time 0.7 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:42 PM PDT 24
Peak memory 204232 kb
Host smart-0df03b9c-989f-451d-b8ea-2e181f3e0940
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548593019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1548593019
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3033024793
Short name T145
Test name
Test status
Simulation time 2663378465 ps
CPU time 3.54 seconds
Started Jul 10 06:01:37 PM PDT 24
Finished Jul 10 06:01:42 PM PDT 24
Peak memory 215588 kb
Host smart-541a46ce-7d59-4d55-bec8-35074f8801d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033024793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3033024793
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1377237719
Short name T1128
Test name
Test status
Simulation time 309490558 ps
CPU time 6.3 seconds
Started Jul 10 06:01:36 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215600 kb
Host smart-f62cd29e-c8fb-4496-89ae-300aff29ecc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377237719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1377237719
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3009590594
Short name T1015
Test name
Test status
Simulation time 14692761 ps
CPU time 0.72 seconds
Started Jul 10 06:01:58 PM PDT 24
Finished Jul 10 06:02:00 PM PDT 24
Peak memory 203928 kb
Host smart-028770a9-f1ab-4828-a4a9-b0f80b8ec01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009590594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3009590594
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2966928248
Short name T1040
Test name
Test status
Simulation time 37056597 ps
CPU time 0.73 seconds
Started Jul 10 06:02:01 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 203956 kb
Host smart-08b407a5-414b-401c-9051-b6dca7eb7e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966928248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2966928248
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.130100591
Short name T1109
Test name
Test status
Simulation time 12893500 ps
CPU time 0.77 seconds
Started Jul 10 06:02:02 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 204360 kb
Host smart-029a4e33-148d-496b-b6d3-5aa984dbe893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130100591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.130100591
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.527443187
Short name T1126
Test name
Test status
Simulation time 13339890 ps
CPU time 0.76 seconds
Started Jul 10 06:02:04 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 204000 kb
Host smart-d8014f32-35bc-4ea0-bb5f-65bfc8805cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527443187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.527443187
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1469727279
Short name T1105
Test name
Test status
Simulation time 13339231 ps
CPU time 0.81 seconds
Started Jul 10 06:02:03 PM PDT 24
Finished Jul 10 06:02:05 PM PDT 24
Peak memory 204060 kb
Host smart-bc0fce8a-e80f-499b-965d-87b89c35dd8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469727279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1469727279
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1502650456
Short name T1069
Test name
Test status
Simulation time 11381193 ps
CPU time 0.78 seconds
Started Jul 10 06:02:02 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 204068 kb
Host smart-b3f341f5-8d11-4706-be47-fe7ffa3de8d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502650456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1502650456
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3061140766
Short name T1054
Test name
Test status
Simulation time 18371553 ps
CPU time 0.8 seconds
Started Jul 10 06:02:04 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 204044 kb
Host smart-d9b4ac00-0581-4f82-851f-86fd159dd78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061140766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3061140766
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.573792160
Short name T1113
Test name
Test status
Simulation time 13679853 ps
CPU time 0.73 seconds
Started Jul 10 06:02:04 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 203996 kb
Host smart-1030d1dc-2e10-4c6b-b555-67d92a5f8fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573792160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.573792160
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2507740052
Short name T1136
Test name
Test status
Simulation time 22115091 ps
CPU time 0.71 seconds
Started Jul 10 06:02:02 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 204328 kb
Host smart-0868d996-34eb-4d10-9914-9e29aa4bf46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507740052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2507740052
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2514269603
Short name T1053
Test name
Test status
Simulation time 125991520 ps
CPU time 0.73 seconds
Started Jul 10 06:02:02 PM PDT 24
Finished Jul 10 06:02:03 PM PDT 24
Peak memory 204348 kb
Host smart-884a4d1c-1a93-495d-9ea1-55e717e4267d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514269603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2514269603
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2164578005
Short name T114
Test name
Test status
Simulation time 793120595 ps
CPU time 16.36 seconds
Started Jul 10 06:01:36 PM PDT 24
Finished Jul 10 06:01:54 PM PDT 24
Peak memory 207392 kb
Host smart-6b293a31-9dfd-47ef-8252-7a6d8da94795
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164578005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2164578005
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.743947413
Short name T1099
Test name
Test status
Simulation time 2742340019 ps
CPU time 40.59 seconds
Started Jul 10 06:01:40 PM PDT 24
Finished Jul 10 06:02:21 PM PDT 24
Peak memory 207412 kb
Host smart-0635245b-a7d5-4961-8a42-2aed1f9e8b4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743947413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.743947413
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3539180528
Short name T1145
Test name
Test status
Simulation time 107937980 ps
CPU time 1.37 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:40 PM PDT 24
Peak memory 216428 kb
Host smart-67422e15-fa02-451b-90d6-e6abfb6bfe04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539180528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3539180528
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3008744457
Short name T1094
Test name
Test status
Simulation time 60700870 ps
CPU time 4.05 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 218540 kb
Host smart-26f1cc87-1456-4269-bb40-4a384134b7d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008744457 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3008744457
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2409982082
Short name T118
Test name
Test status
Simulation time 29032818 ps
CPU time 1.98 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:41 PM PDT 24
Peak memory 215560 kb
Host smart-aa2966ac-5723-482d-aac8-d7c926152064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409982082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
409982082
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3337928096
Short name T1029
Test name
Test status
Simulation time 30407622 ps
CPU time 0.78 seconds
Started Jul 10 06:01:36 PM PDT 24
Finished Jul 10 06:01:38 PM PDT 24
Peak memory 204040 kb
Host smart-d7f81d3e-5dd7-4b37-b0dc-8e3aa201e637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337928096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
337928096
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3565138881
Short name T1142
Test name
Test status
Simulation time 48320252 ps
CPU time 1.75 seconds
Started Jul 10 06:01:37 PM PDT 24
Finished Jul 10 06:01:41 PM PDT 24
Peak memory 215508 kb
Host smart-18937ca9-8dfa-4395-9443-25019ce25641
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565138881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3565138881
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3537558992
Short name T1067
Test name
Test status
Simulation time 61137229 ps
CPU time 0.68 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:46 PM PDT 24
Peak memory 203884 kb
Host smart-3557d90a-a8ca-4240-94db-e932ee6103bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537558992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3537558992
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3816670730
Short name T1052
Test name
Test status
Simulation time 233877439 ps
CPU time 3.66 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 215404 kb
Host smart-37daf1b0-9b66-46e8-afeb-4efc171ab16d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816670730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3816670730
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3106099544
Short name T1149
Test name
Test status
Simulation time 304350610 ps
CPU time 7.95 seconds
Started Jul 10 06:01:34 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215576 kb
Host smart-823685d6-c3ff-4c58-98eb-0e7a8bbe25ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106099544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3106099544
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.208947044
Short name T1130
Test name
Test status
Simulation time 16642955 ps
CPU time 0.82 seconds
Started Jul 10 06:02:02 PM PDT 24
Finished Jul 10 06:02:04 PM PDT 24
Peak memory 204100 kb
Host smart-aa3d4553-f61f-4cae-aab8-0fa28174a900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208947044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.208947044
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3417606548
Short name T1020
Test name
Test status
Simulation time 24117403 ps
CPU time 0.77 seconds
Started Jul 10 06:02:05 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 204336 kb
Host smart-02a0e601-12b3-495b-810a-0510e6cc5d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417606548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3417606548
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1543143410
Short name T1148
Test name
Test status
Simulation time 14394443 ps
CPU time 0.77 seconds
Started Jul 10 06:02:03 PM PDT 24
Finished Jul 10 06:02:05 PM PDT 24
Peak memory 204328 kb
Host smart-70e83bf0-35ec-4105-8008-dcfd964bba5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543143410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1543143410
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4060472027
Short name T1143
Test name
Test status
Simulation time 12979123 ps
CPU time 0.76 seconds
Started Jul 10 06:02:05 PM PDT 24
Finished Jul 10 06:02:07 PM PDT 24
Peak memory 204344 kb
Host smart-dd9ddd5c-df60-4617-af34-0c69833e7d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060472027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4060472027
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1102945249
Short name T1058
Test name
Test status
Simulation time 42253465 ps
CPU time 0.78 seconds
Started Jul 10 06:02:04 PM PDT 24
Finished Jul 10 06:02:06 PM PDT 24
Peak memory 204172 kb
Host smart-1ab5f3fe-277b-4e1e-b0e9-89e29ded1073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102945249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1102945249
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3011912393
Short name T1125
Test name
Test status
Simulation time 35383856 ps
CPU time 0.76 seconds
Started Jul 10 06:02:06 PM PDT 24
Finished Jul 10 06:02:08 PM PDT 24
Peak memory 204060 kb
Host smart-e918e0f5-cc79-405e-8edf-9186d89fb795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011912393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3011912393
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.750474224
Short name T1087
Test name
Test status
Simulation time 10805272 ps
CPU time 0.7 seconds
Started Jul 10 06:02:05 PM PDT 24
Finished Jul 10 06:02:07 PM PDT 24
Peak memory 204352 kb
Host smart-bb350458-8651-4ec4-8fe2-408f526247ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750474224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.750474224
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1188235437
Short name T1114
Test name
Test status
Simulation time 20925812 ps
CPU time 0.73 seconds
Started Jul 10 06:02:18 PM PDT 24
Finished Jul 10 06:02:20 PM PDT 24
Peak memory 204044 kb
Host smart-22486646-09cc-47e4-a030-a60650dcf0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188235437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1188235437
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2102169434
Short name T1116
Test name
Test status
Simulation time 17909939 ps
CPU time 0.8 seconds
Started Jul 10 06:02:07 PM PDT 24
Finished Jul 10 06:02:08 PM PDT 24
Peak memory 204328 kb
Host smart-b00f477d-0e70-44d8-a228-9774f928f664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102169434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2102169434
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.134549994
Short name T1025
Test name
Test status
Simulation time 32166107 ps
CPU time 0.73 seconds
Started Jul 10 06:02:06 PM PDT 24
Finished Jul 10 06:02:07 PM PDT 24
Peak memory 204020 kb
Host smart-3d90ec91-6799-4234-8c55-0590cfde3bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134549994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.134549994
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2776336851
Short name T1038
Test name
Test status
Simulation time 96644488 ps
CPU time 1.73 seconds
Started Jul 10 06:01:40 PM PDT 24
Finished Jul 10 06:01:42 PM PDT 24
Peak memory 215604 kb
Host smart-540b88ac-57f2-4b67-b031-3f74f15a56d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776336851 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2776336851
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.582700673
Short name T1101
Test name
Test status
Simulation time 18711909 ps
CPU time 1.27 seconds
Started Jul 10 06:01:45 PM PDT 24
Finished Jul 10 06:01:47 PM PDT 24
Peak memory 215524 kb
Host smart-d6990b0f-7f5a-49a6-9d80-7f2ecda6a811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582700673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.582700673
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3654719350
Short name T1032
Test name
Test status
Simulation time 15382732 ps
CPU time 0.74 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 204024 kb
Host smart-68813d5d-af33-4ea7-8a9b-11a47bfa0e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654719350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
654719350
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4210786888
Short name T1044
Test name
Test status
Simulation time 490172757 ps
CPU time 1.91 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215576 kb
Host smart-6cf9d220-1504-4684-9100-08b7b130818d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210786888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4210786888
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4177106432
Short name T106
Test name
Test status
Simulation time 49622483 ps
CPU time 3.29 seconds
Started Jul 10 06:01:38 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 215872 kb
Host smart-4642deff-8bfa-46a4-a0a9-33d3f2191f42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177106432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
177106432
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.954296834
Short name T1036
Test name
Test status
Simulation time 302266220 ps
CPU time 7.31 seconds
Started Jul 10 06:01:44 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 215868 kb
Host smart-104a0e47-df6e-4fac-9c6c-c40ed0cdd9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954296834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.954296834
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2210827647
Short name T1121
Test name
Test status
Simulation time 53291412 ps
CPU time 1.89 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215520 kb
Host smart-aca1a2b9-34d6-4e34-bc7c-700ea340c411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210827647 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2210827647
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1102848564
Short name T132
Test name
Test status
Simulation time 64687431 ps
CPU time 2.16 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:01:49 PM PDT 24
Peak memory 215672 kb
Host smart-119291a2-6509-4eae-80ad-4b0d5fda8700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102848564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
102848564
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2974934893
Short name T1013
Test name
Test status
Simulation time 18452947 ps
CPU time 0.73 seconds
Started Jul 10 06:01:45 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 203932 kb
Host smart-89b491f1-a94f-467c-9afe-bdbc01159236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974934893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
974934893
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.937269652
Short name T1018
Test name
Test status
Simulation time 758847824 ps
CPU time 2.57 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:01:50 PM PDT 24
Peak memory 215728 kb
Host smart-757127a2-3165-44f3-87e1-04568ec1f780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937269652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.937269652
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4160892806
Short name T102
Test name
Test status
Simulation time 112221040 ps
CPU time 4.08 seconds
Started Jul 10 06:01:42 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 215824 kb
Host smart-b0523141-7e8f-4718-b1f6-4c02dfd2063a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160892806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
160892806
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1175258252
Short name T157
Test name
Test status
Simulation time 1512467066 ps
CPU time 6.62 seconds
Started Jul 10 06:01:40 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 215552 kb
Host smart-c6f12a5c-0f65-48a6-a9da-d51b13c913f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175258252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1175258252
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1199448437
Short name T111
Test name
Test status
Simulation time 518007370 ps
CPU time 4.12 seconds
Started Jul 10 06:01:42 PM PDT 24
Finished Jul 10 06:01:47 PM PDT 24
Peak memory 217344 kb
Host smart-0fbe79c8-2261-460c-b644-dc22e4fe6c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199448437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1199448437
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2456065228
Short name T113
Test name
Test status
Simulation time 124398494 ps
CPU time 1.25 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215576 kb
Host smart-1913fb75-3f6c-4e1e-92fb-155649412ea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456065228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
456065228
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3400049749
Short name T1072
Test name
Test status
Simulation time 56143766 ps
CPU time 0.74 seconds
Started Jul 10 06:01:45 PM PDT 24
Finished Jul 10 06:01:47 PM PDT 24
Peak memory 204000 kb
Host smart-d3ee0e53-c858-42fb-8516-65c4bc8087c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400049749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
400049749
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3663027428
Short name T131
Test name
Test status
Simulation time 616041688 ps
CPU time 3.3 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 215488 kb
Host smart-bab3145a-9b70-452f-bfb3-144a8826811b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663027428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3663027428
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3798814903
Short name T1096
Test name
Test status
Simulation time 81528357 ps
CPU time 1.46 seconds
Started Jul 10 06:01:45 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 216704 kb
Host smart-531dc0fc-7a4d-4b45-b4d7-d7ba766c1875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798814903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
798814903
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1302450275
Short name T159
Test name
Test status
Simulation time 4050342936 ps
CPU time 14.48 seconds
Started Jul 10 06:01:46 PM PDT 24
Finished Jul 10 06:02:02 PM PDT 24
Peak memory 215788 kb
Host smart-25ec4d45-4b11-4507-8724-c8b4b458c1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302450275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1302450275
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4005566096
Short name T1068
Test name
Test status
Simulation time 52884126 ps
CPU time 1.77 seconds
Started Jul 10 06:01:45 PM PDT 24
Finished Jul 10 06:01:48 PM PDT 24
Peak memory 215580 kb
Host smart-b3e10e9a-c687-4719-be1b-40ad9e3767d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005566096 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4005566096
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3221226438
Short name T1091
Test name
Test status
Simulation time 302189507 ps
CPU time 2.37 seconds
Started Jul 10 06:01:41 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 215508 kb
Host smart-dece63c0-c5ef-4125-8784-02bd8fa8d4d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221226438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
221226438
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.497939242
Short name T1097
Test name
Test status
Simulation time 108105032 ps
CPU time 0.77 seconds
Started Jul 10 06:01:42 PM PDT 24
Finished Jul 10 06:01:44 PM PDT 24
Peak memory 204076 kb
Host smart-7984abf4-0f55-40cd-98a0-7c23e040b587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497939242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.497939242
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1588952589
Short name T1081
Test name
Test status
Simulation time 105593829 ps
CPU time 1.84 seconds
Started Jul 10 06:01:40 PM PDT 24
Finished Jul 10 06:01:43 PM PDT 24
Peak memory 215436 kb
Host smart-5c67e8ea-fef2-43e3-94ba-3440f04aeb4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588952589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1588952589
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.946366743
Short name T109
Test name
Test status
Simulation time 850953156 ps
CPU time 20.87 seconds
Started Jul 10 06:01:43 PM PDT 24
Finished Jul 10 06:02:05 PM PDT 24
Peak memory 215580 kb
Host smart-a1eec700-c727-4b18-bc00-d9c462b0735a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946366743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.946366743
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3391678242
Short name T1057
Test name
Test status
Simulation time 169055425 ps
CPU time 1.68 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 215488 kb
Host smart-306c2780-8ff8-4d6e-8ae3-0a79d70944f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391678242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3391678242
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1382620973
Short name T1023
Test name
Test status
Simulation time 101749876 ps
CPU time 1.98 seconds
Started Jul 10 06:01:50 PM PDT 24
Finished Jul 10 06:01:54 PM PDT 24
Peak memory 207200 kb
Host smart-6123ec50-718d-4747-9bfa-56a3bd3666ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382620973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
382620973
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2506018988
Short name T1079
Test name
Test status
Simulation time 14864073 ps
CPU time 0.76 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:52 PM PDT 24
Peak memory 204008 kb
Host smart-6d96d42e-1e7e-46c3-86ff-38267db84893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506018988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
506018988
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3040092101
Short name T1108
Test name
Test status
Simulation time 110570103 ps
CPU time 3.8 seconds
Started Jul 10 06:01:47 PM PDT 24
Finished Jul 10 06:01:53 PM PDT 24
Peak memory 215488 kb
Host smart-b552ff93-e9e7-40aa-9edc-ab1ceb549c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040092101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3040092101
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.604997976
Short name T96
Test name
Test status
Simulation time 408254610 ps
CPU time 4.36 seconds
Started Jul 10 06:01:49 PM PDT 24
Finished Jul 10 06:01:55 PM PDT 24
Peak memory 215812 kb
Host smart-2f305ae1-21ab-451f-a1bb-73f8b24ac40f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604997976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.604997976
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3417208298
Short name T1065
Test name
Test status
Simulation time 106293422 ps
CPU time 6.62 seconds
Started Jul 10 06:01:48 PM PDT 24
Finished Jul 10 06:01:57 PM PDT 24
Peak memory 215504 kb
Host smart-652e1bef-26ab-4970-a5c1-d3cd9fec6311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417208298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3417208298
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2714790102
Short name T437
Test name
Test status
Simulation time 12956396 ps
CPU time 0.71 seconds
Started Jul 10 05:41:13 PM PDT 24
Finished Jul 10 05:41:15 PM PDT 24
Peak memory 205792 kb
Host smart-6ee911a6-a457-4d32-8f0b-f41149afc720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714790102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
714790102
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.851275961
Short name T169
Test name
Test status
Simulation time 181549973 ps
CPU time 4.1 seconds
Started Jul 10 05:41:07 PM PDT 24
Finished Jul 10 05:41:12 PM PDT 24
Peak memory 233752 kb
Host smart-af63390f-d72e-4227-a0cd-fe26a1dbf095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851275961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.851275961
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4075979484
Short name T23
Test name
Test status
Simulation time 69793010 ps
CPU time 0.82 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:05 PM PDT 24
Peak memory 207784 kb
Host smart-faccfb16-ce90-422e-b411-b0ad0f9f6082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075979484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4075979484
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2356475228
Short name T168
Test name
Test status
Simulation time 60977872985 ps
CPU time 129.19 seconds
Started Jul 10 05:41:13 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 250272 kb
Host smart-fca8ea55-892a-4904-b587-4aa090017c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356475228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2356475228
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3330369183
Short name T530
Test name
Test status
Simulation time 6004129225 ps
CPU time 41.29 seconds
Started Jul 10 05:41:17 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 254804 kb
Host smart-1b0c7459-a999-46b3-9c60-8fd48ac2ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330369183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3330369183
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1939940066
Short name T262
Test name
Test status
Simulation time 11469795444 ps
CPU time 85.31 seconds
Started Jul 10 05:41:13 PM PDT 24
Finished Jul 10 05:42:39 PM PDT 24
Peak memory 232904 kb
Host smart-e6942c0a-fafc-4e16-88ce-fa38ba756bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939940066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1939940066
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.805506246
Short name T994
Test name
Test status
Simulation time 5682350915 ps
CPU time 7.13 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 225692 kb
Host smart-8416a845-dccd-4f3e-b087-e02f3c757426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805506246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.805506246
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3561745956
Short name T170
Test name
Test status
Simulation time 55567737656 ps
CPU time 70.65 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:42:22 PM PDT 24
Peak memory 233908 kb
Host smart-10a5bf92-59ac-4c32-9850-bd5f6ec764f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561745956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3561745956
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3656916957
Short name T1
Test name
Test status
Simulation time 2555440170 ps
CPU time 12.1 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:41:24 PM PDT 24
Peak memory 233868 kb
Host smart-c3ccfe69-fe09-48d8-90d2-6769ba68ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656916957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3656916957
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3591252382
Short name T326
Test name
Test status
Simulation time 24325064770 ps
CPU time 110.12 seconds
Started Jul 10 05:41:09 PM PDT 24
Finished Jul 10 05:43:01 PM PDT 24
Peak memory 234424 kb
Host smart-3efa9244-4b46-47bc-bf83-c4534c2ad55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591252382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3591252382
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1167487753
Short name T923
Test name
Test status
Simulation time 17042823 ps
CPU time 1.07 seconds
Started Jul 10 05:41:03 PM PDT 24
Finished Jul 10 05:41:06 PM PDT 24
Peak memory 217604 kb
Host smart-e0abf836-09b1-4985-93cd-d2dcd5352832
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167487753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1167487753
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1387459969
Short name T488
Test name
Test status
Simulation time 2155372438 ps
CPU time 12.11 seconds
Started Jul 10 05:41:09 PM PDT 24
Finished Jul 10 05:41:21 PM PDT 24
Peak memory 242056 kb
Host smart-2e1d8318-fad9-41e5-9dbf-c309bfa76fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387459969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1387459969
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3542167524
Short name T896
Test name
Test status
Simulation time 519034521 ps
CPU time 4 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:41:16 PM PDT 24
Peak memory 233724 kb
Host smart-3b37fd02-8cdf-42e3-9039-134f1ffc58ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542167524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3542167524
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4099919216
Short name T925
Test name
Test status
Simulation time 1267746468 ps
CPU time 3.84 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:41:16 PM PDT 24
Peak memory 224276 kb
Host smart-ee36569d-34dc-4d40-b7af-e92eb7991595
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099919216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4099919216
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.652593747
Short name T814
Test name
Test status
Simulation time 7001594412 ps
CPU time 138.58 seconds
Started Jul 10 05:41:17 PM PDT 24
Finished Jul 10 05:43:37 PM PDT 24
Peak memory 262240 kb
Host smart-e9883f17-06c2-40e3-a6a4-a5cae9603db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652593747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.652593747
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.407570540
Short name T778
Test name
Test status
Simulation time 3559578383 ps
CPU time 25.9 seconds
Started Jul 10 05:41:10 PM PDT 24
Finished Jul 10 05:41:38 PM PDT 24
Peak memory 217668 kb
Host smart-c815dc18-0265-4715-ae72-f37e7ff441d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407570540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.407570540
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1171113211
Short name T759
Test name
Test status
Simulation time 636332820 ps
CPU time 3.45 seconds
Started Jul 10 05:41:08 PM PDT 24
Finished Jul 10 05:41:12 PM PDT 24
Peak memory 217304 kb
Host smart-419c0eb1-9429-4e93-8fbe-89868b0fd37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171113211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1171113211
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1887800102
Short name T4
Test name
Test status
Simulation time 1049945602 ps
CPU time 0.95 seconds
Started Jul 10 05:41:09 PM PDT 24
Finished Jul 10 05:41:11 PM PDT 24
Peak memory 206892 kb
Host smart-b49b89fc-6f40-40f8-b593-9f44a4b1d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887800102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1887800102
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1786835698
Short name T720
Test name
Test status
Simulation time 630862176 ps
CPU time 3.86 seconds
Started Jul 10 05:41:09 PM PDT 24
Finished Jul 10 05:41:13 PM PDT 24
Peak memory 225564 kb
Host smart-9751a44c-50d1-4884-8dff-a3d0f7071d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786835698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1786835698
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4150829646
Short name T431
Test name
Test status
Simulation time 12728385 ps
CPU time 0.72 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:26 PM PDT 24
Peak memory 205800 kb
Host smart-99325758-4ab6-4c5e-8cfd-f4df36ccdd60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150829646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
150829646
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3621243765
Short name T576
Test name
Test status
Simulation time 789029538 ps
CPU time 5.39 seconds
Started Jul 10 05:41:24 PM PDT 24
Finished Jul 10 05:41:31 PM PDT 24
Peak memory 225512 kb
Host smart-b7f94f15-6990-4e9e-9df4-fa28112b4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621243765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3621243765
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2750563796
Short name T819
Test name
Test status
Simulation time 17255885 ps
CPU time 0.81 seconds
Started Jul 10 05:41:17 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 207496 kb
Host smart-0cf55f4b-7087-41fc-ac61-b2bd442930f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750563796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2750563796
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2015026948
Short name T838
Test name
Test status
Simulation time 29642114746 ps
CPU time 262.81 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:45:46 PM PDT 24
Peak memory 252452 kb
Host smart-d08f624d-176b-45f9-b5c8-22290ddb9eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015026948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2015026948
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.953595709
Short name T284
Test name
Test status
Simulation time 41452396910 ps
CPU time 135.05 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 250412 kb
Host smart-bcb565f4-794e-4782-8862-dcf3161f14c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953595709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.953595709
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1940277877
Short name T680
Test name
Test status
Simulation time 1609794227 ps
CPU time 26.86 seconds
Started Jul 10 05:41:26 PM PDT 24
Finished Jul 10 05:41:53 PM PDT 24
Peak memory 250084 kb
Host smart-d8880500-7166-4a97-816d-4bc8b6353107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940277877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1940277877
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3122203550
Short name T889
Test name
Test status
Simulation time 424180924 ps
CPU time 5.18 seconds
Started Jul 10 05:41:26 PM PDT 24
Finished Jul 10 05:41:32 PM PDT 24
Peak memory 225464 kb
Host smart-6967cbd0-26f0-4009-aa49-3fe92d78033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122203550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3122203550
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1998904667
Short name T339
Test name
Test status
Simulation time 174211689 ps
CPU time 2.4 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:27 PM PDT 24
Peak memory 233444 kb
Host smart-5d953470-6b28-47c0-816d-88caaa884d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998904667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1998904667
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.878725736
Short name T242
Test name
Test status
Simulation time 51343139573 ps
CPU time 42.4 seconds
Started Jul 10 05:41:14 PM PDT 24
Finished Jul 10 05:41:57 PM PDT 24
Peak memory 241616 kb
Host smart-721b7c48-13bd-49d9-9a61-7b97c8353913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878725736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
878725736
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2007241128
Short name T978
Test name
Test status
Simulation time 24016330845 ps
CPU time 8.6 seconds
Started Jul 10 05:41:16 PM PDT 24
Finished Jul 10 05:41:26 PM PDT 24
Peak memory 233892 kb
Host smart-97c95ebd-de66-4283-85d1-10ffb44e45ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007241128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2007241128
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2844672812
Short name T871
Test name
Test status
Simulation time 1887612936 ps
CPU time 15.85 seconds
Started Jul 10 05:41:25 PM PDT 24
Finished Jul 10 05:41:42 PM PDT 24
Peak memory 221920 kb
Host smart-85d66c0f-067c-4806-8a04-5b2f6898fedf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2844672812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2844672812
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2922885209
Short name T78
Test name
Test status
Simulation time 258036361 ps
CPU time 1.09 seconds
Started Jul 10 05:41:24 PM PDT 24
Finished Jul 10 05:41:27 PM PDT 24
Peak memory 236272 kb
Host smart-309e1e8b-b109-4dc1-bcbd-92a439a3e43b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922885209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2922885209
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3759639983
Short name T150
Test name
Test status
Simulation time 53105574918 ps
CPU time 111.18 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:43:15 PM PDT 24
Peak memory 252216 kb
Host smart-30f57a4c-10c4-43be-9a65-ad285dcdfe7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759639983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3759639983
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1116969595
Short name T722
Test name
Test status
Simulation time 853788984 ps
CPU time 11.5 seconds
Started Jul 10 05:41:13 PM PDT 24
Finished Jul 10 05:41:25 PM PDT 24
Peak memory 221020 kb
Host smart-14819909-0e11-4d58-b5d7-5c0aa4c3005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116969595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1116969595
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.185068635
Short name T741
Test name
Test status
Simulation time 3006879265 ps
CPU time 3.46 seconds
Started Jul 10 05:41:15 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 217388 kb
Host smart-f70a9a40-3858-4de4-8854-7efb24903a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185068635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.185068635
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2251896872
Short name T455
Test name
Test status
Simulation time 64802928 ps
CPU time 2.05 seconds
Started Jul 10 05:41:16 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 217404 kb
Host smart-ad1a1f9a-3a52-4353-abe3-9703c716d4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251896872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2251896872
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.262638145
Short name T317
Test name
Test status
Simulation time 50117701 ps
CPU time 0.76 seconds
Started Jul 10 05:41:17 PM PDT 24
Finished Jul 10 05:41:19 PM PDT 24
Peak memory 206920 kb
Host smart-242bd6ca-9c58-4ca4-a4c3-178bfb26e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262638145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.262638145
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3102193837
Short name T904
Test name
Test status
Simulation time 479357286 ps
CPU time 6.58 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:31 PM PDT 24
Peak memory 241916 kb
Host smart-d64471ff-32e3-4145-8e66-58b0d513fdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102193837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3102193837
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.705237084
Short name T815
Test name
Test status
Simulation time 19069700 ps
CPU time 0.75 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 205784 kb
Host smart-359584c9-19f3-4df1-a3e3-ab702cfdeefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705237084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.705237084
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.896437823
Short name T367
Test name
Test status
Simulation time 114885278 ps
CPU time 3.99 seconds
Started Jul 10 05:42:14 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 233728 kb
Host smart-55e00738-3db7-4a5b-ae04-5357455c8bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896437823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.896437823
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1226927886
Short name T981
Test name
Test status
Simulation time 24318435 ps
CPU time 0.77 seconds
Started Jul 10 05:42:14 PM PDT 24
Finished Jul 10 05:42:15 PM PDT 24
Peak memory 206472 kb
Host smart-2bf88e1a-af63-464b-835d-13ce08fb0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226927886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1226927886
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.801944806
Short name T974
Test name
Test status
Simulation time 6906485324 ps
CPU time 30.38 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:48 PM PDT 24
Peak memory 240276 kb
Host smart-e8359e5b-a70f-4362-b756-375f7c80b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801944806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.801944806
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3591889894
Short name T697
Test name
Test status
Simulation time 13682425826 ps
CPU time 40.04 seconds
Started Jul 10 05:42:17 PM PDT 24
Finished Jul 10 05:42:59 PM PDT 24
Peak memory 218840 kb
Host smart-526d4890-c513-40dc-b7c6-5278778269e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591889894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3591889894
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2619898892
Short name T590
Test name
Test status
Simulation time 11550123191 ps
CPU time 60.34 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 250412 kb
Host smart-86fa4e66-cd29-431d-b755-704a171f3725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619898892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2619898892
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3192598263
Short name T124
Test name
Test status
Simulation time 171975513 ps
CPU time 3.92 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:21 PM PDT 24
Peak memory 225564 kb
Host smart-7fb2a44e-a8b8-4c0e-a490-cfff493a1122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192598263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3192598263
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3734744521
Short name T779
Test name
Test status
Simulation time 11888144135 ps
CPU time 42.16 seconds
Started Jul 10 05:42:14 PM PDT 24
Finished Jul 10 05:42:58 PM PDT 24
Peak memory 250424 kb
Host smart-b65eab48-1806-4625-84e4-be525c739846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734744521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3734744521
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3267130948
Short name T350
Test name
Test status
Simulation time 1403540990 ps
CPU time 6.14 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:23 PM PDT 24
Peak memory 233948 kb
Host smart-9bfdb3d8-edf9-4749-a709-fa2f7e7489b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267130948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3267130948
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4270892491
Short name T246
Test name
Test status
Simulation time 794711457 ps
CPU time 4 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:22 PM PDT 24
Peak memory 233784 kb
Host smart-5d7400bf-a42f-4a60-bae9-7f06020ee78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270892491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4270892491
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1219583765
Short name T422
Test name
Test status
Simulation time 28127740 ps
CPU time 1.09 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:19 PM PDT 24
Peak memory 217640 kb
Host smart-cb09bd4d-480a-44a5-b3c5-c5d79e69e3c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219583765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1219583765
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.371695887
Short name T794
Test name
Test status
Simulation time 14087946379 ps
CPU time 24.99 seconds
Started Jul 10 05:42:17 PM PDT 24
Finished Jul 10 05:42:43 PM PDT 24
Peak memory 250192 kb
Host smart-f55e4e5f-40f0-4942-a106-c5840a466302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371695887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.371695887
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3594892656
Short name T953
Test name
Test status
Simulation time 139684235 ps
CPU time 3.68 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:22 PM PDT 24
Peak memory 233720 kb
Host smart-54413ca7-8a5c-416e-96fb-1de7490d0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594892656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3594892656
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.454841097
Short name T868
Test name
Test status
Simulation time 98188194 ps
CPU time 4.54 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:21 PM PDT 24
Peak memory 224000 kb
Host smart-1883df6f-a898-4b22-96b7-ceb4aab61bfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454841097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.454841097
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3963300011
Short name T952
Test name
Test status
Simulation time 17612248972 ps
CPU time 92.93 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 241108 kb
Host smart-365d7f0b-aea3-4416-b8a8-75985e9efa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963300011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3963300011
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.862260475
Short name T298
Test name
Test status
Simulation time 6512814884 ps
CPU time 14.93 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:33 PM PDT 24
Peak memory 217536 kb
Host smart-93560ffa-1229-4a7b-95d7-ea5fc99d0c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862260475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.862260475
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.844135513
Short name T91
Test name
Test status
Simulation time 3062522723 ps
CPU time 4.29 seconds
Started Jul 10 05:42:14 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 217548 kb
Host smart-c22f59d3-5d36-4f8b-abd6-ecba19e825ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844135513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.844135513
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.778961132
Short name T908
Test name
Test status
Simulation time 105986004 ps
CPU time 1.7 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:18 PM PDT 24
Peak memory 217232 kb
Host smart-51550cc1-d146-4d40-92ba-3965ce171ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778961132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.778961132
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3483289661
Short name T384
Test name
Test status
Simulation time 121501592 ps
CPU time 0.89 seconds
Started Jul 10 05:42:16 PM PDT 24
Finished Jul 10 05:42:19 PM PDT 24
Peak memory 206948 kb
Host smart-07439d52-3e33-4f89-a30c-f795dc1fdffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483289661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3483289661
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2547424787
Short name T802
Test name
Test status
Simulation time 1211661602 ps
CPU time 5.68 seconds
Started Jul 10 05:42:14 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 225584 kb
Host smart-9b1795de-65cc-4c9c-884f-762bf20999e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547424787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2547424787
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1823786713
Short name T415
Test name
Test status
Simulation time 20622155 ps
CPU time 0.73 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 206388 kb
Host smart-17e38a7e-5da6-4072-96f5-64973fa26fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823786713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1823786713
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3895132692
Short name T825
Test name
Test status
Simulation time 388931753 ps
CPU time 2.37 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:27 PM PDT 24
Peak memory 225556 kb
Host smart-67f46195-3a24-44b7-b6ea-d2ee7b9acc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895132692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3895132692
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.37765304
Short name T482
Test name
Test status
Simulation time 25217585 ps
CPU time 0.8 seconds
Started Jul 10 05:42:25 PM PDT 24
Finished Jul 10 05:42:26 PM PDT 24
Peak memory 207840 kb
Host smart-d27e176a-e6cc-449e-8e4a-740ebf787478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37765304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.37765304
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1959292460
Short name T405
Test name
Test status
Simulation time 359784560 ps
CPU time 5.23 seconds
Started Jul 10 05:42:26 PM PDT 24
Finished Jul 10 05:42:33 PM PDT 24
Peak memory 236568 kb
Host smart-c1dc8dc1-d706-455e-9cca-603246226f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959292460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1959292460
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1072402549
Short name T986
Test name
Test status
Simulation time 6870500033 ps
CPU time 39.21 seconds
Started Jul 10 05:42:22 PM PDT 24
Finished Jul 10 05:43:03 PM PDT 24
Peak memory 218724 kb
Host smart-dfa7f14a-8231-43be-bf53-c59a71a75b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072402549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1072402549
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.16165497
Short name T566
Test name
Test status
Simulation time 2910594365 ps
CPU time 15.28 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:39 PM PDT 24
Peak memory 242028 kb
Host smart-35d3e798-eeb8-4411-805c-ca9340031d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16165497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.16165497
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2614600999
Short name T921
Test name
Test status
Simulation time 55686311820 ps
CPU time 85.79 seconds
Started Jul 10 05:42:24 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 233904 kb
Host smart-331509cd-9f57-4403-8be2-1f449a5ba1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614600999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2614600999
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2664922377
Short name T726
Test name
Test status
Simulation time 534822331 ps
CPU time 7.58 seconds
Started Jul 10 05:42:19 PM PDT 24
Finished Jul 10 05:42:27 PM PDT 24
Peak memory 225548 kb
Host smart-a7fd502f-abe7-4171-83f9-6787bf44aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664922377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2664922377
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2131553009
Short name T354
Test name
Test status
Simulation time 601399312 ps
CPU time 4.47 seconds
Started Jul 10 05:42:20 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 233696 kb
Host smart-ffcf3d0b-5459-4230-b9bf-119e7d12169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131553009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2131553009
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2614196735
Short name T775
Test name
Test status
Simulation time 41239204 ps
CPU time 1.04 seconds
Started Jul 10 05:42:22 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 217580 kb
Host smart-8e49ad57-6ec1-43fc-ae66-dfd7e26ed691
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614196735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2614196735
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1220479281
Short name T256
Test name
Test status
Simulation time 10124299824 ps
CPU time 21.71 seconds
Started Jul 10 05:42:26 PM PDT 24
Finished Jul 10 05:42:49 PM PDT 24
Peak memory 233824 kb
Host smart-5931d9a9-6a3b-4a5a-befb-9ed9f1eeaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220479281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1220479281
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2100854579
Short name T658
Test name
Test status
Simulation time 586344551 ps
CPU time 3.77 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:26 PM PDT 24
Peak memory 233700 kb
Host smart-4a7042c1-cbb5-47ea-af6e-341d5a5fb2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100854579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2100854579
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.718260069
Short name T485
Test name
Test status
Simulation time 194037493 ps
CPU time 4.89 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:29 PM PDT 24
Peak memory 223624 kb
Host smart-25d3fe14-a94c-47ea-a7d3-980912291423
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718260069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.718260069
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1018777009
Short name T270
Test name
Test status
Simulation time 18983215695 ps
CPU time 198.49 seconds
Started Jul 10 05:42:25 PM PDT 24
Finished Jul 10 05:45:44 PM PDT 24
Peak memory 272032 kb
Host smart-e7c86dd0-d7e9-434f-a137-6939aee4d150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018777009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1018777009
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1669952662
Short name T750
Test name
Test status
Simulation time 2067374268 ps
CPU time 15.85 seconds
Started Jul 10 05:42:24 PM PDT 24
Finished Jul 10 05:42:41 PM PDT 24
Peak memory 217104 kb
Host smart-4bc9b398-6f64-478b-a732-b3416f4c721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669952662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1669952662
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1224691986
Short name T623
Test name
Test status
Simulation time 59110411069 ps
CPU time 21.29 seconds
Started Jul 10 05:42:22 PM PDT 24
Finished Jul 10 05:42:45 PM PDT 24
Peak memory 217524 kb
Host smart-58686422-8f08-47f4-9b45-41d71d1eea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224691986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1224691986
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1412802573
Short name T382
Test name
Test status
Simulation time 182538488 ps
CPU time 1.51 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:24 PM PDT 24
Peak memory 217336 kb
Host smart-b8e2bf1a-06f4-49bd-8e22-46186a550c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412802573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1412802573
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2921137408
Short name T463
Test name
Test status
Simulation time 64655042 ps
CPU time 0.75 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 206956 kb
Host smart-18e8f5a9-e89a-41e1-a8e3-a609a2c4bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921137408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2921137408
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3354148321
Short name T251
Test name
Test status
Simulation time 548211539 ps
CPU time 3.86 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:26 PM PDT 24
Peak memory 225280 kb
Host smart-25af54aa-9761-4bb1-8bd0-bb6cc13e6374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354148321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3354148321
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.156882538
Short name T757
Test name
Test status
Simulation time 55042332 ps
CPU time 0.75 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:42:29 PM PDT 24
Peak memory 206324 kb
Host smart-6ccd139b-d70c-485b-8ec8-8fa79a036e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156882538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.156882538
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.894486552
Short name T228
Test name
Test status
Simulation time 61208082 ps
CPU time 2.68 seconds
Started Jul 10 05:42:29 PM PDT 24
Finished Jul 10 05:42:33 PM PDT 24
Peak memory 233716 kb
Host smart-ac4bf908-b66a-41de-b148-688fbd956955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894486552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.894486552
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2577417147
Short name T141
Test name
Test status
Simulation time 22447032 ps
CPU time 0.75 seconds
Started Jul 10 05:42:24 PM PDT 24
Finished Jul 10 05:42:26 PM PDT 24
Peak memory 207284 kb
Host smart-54764fec-8275-4699-a2ee-3c017b6c80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577417147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2577417147
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1537205445
Short name T708
Test name
Test status
Simulation time 304900962257 ps
CPU time 241.25 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:46:30 PM PDT 24
Peak memory 256600 kb
Host smart-fcbe6f8b-ab61-4a53-8efe-1c0e566f1263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537205445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1537205445
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1606836520
Short name T756
Test name
Test status
Simulation time 6136108108 ps
CPU time 39.56 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:43:09 PM PDT 24
Peak memory 232380 kb
Host smart-f801ec52-ebf2-4e27-a17e-fc903546b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606836520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1606836520
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3978231020
Short name T630
Test name
Test status
Simulation time 1704487368 ps
CPU time 6.55 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:42:36 PM PDT 24
Peak memory 237716 kb
Host smart-87cdafeb-6ea2-4635-b2c9-bef1f2d141ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978231020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3978231020
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.127014524
Short name T768
Test name
Test status
Simulation time 36494986336 ps
CPU time 57.81 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 250208 kb
Host smart-9482b8bb-0e15-4095-ac18-a8ae3f533fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127014524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.127014524
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2052394459
Short name T238
Test name
Test status
Simulation time 1199661986 ps
CPU time 3.35 seconds
Started Jul 10 05:42:31 PM PDT 24
Finished Jul 10 05:42:35 PM PDT 24
Peak memory 228824 kb
Host smart-81b79256-6fdb-4d30-93c4-7ec2fe0accc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052394459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2052394459
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.389676259
Short name T322
Test name
Test status
Simulation time 436394018 ps
CPU time 2.62 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:42:30 PM PDT 24
Peak memory 225628 kb
Host smart-8c706745-f90b-412c-8180-c9918ce09a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389676259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.389676259
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3690346289
Short name T987
Test name
Test status
Simulation time 126764018 ps
CPU time 1.05 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:24 PM PDT 24
Peak memory 217836 kb
Host smart-a4eac936-a987-4938-af02-9fb1082e0ca1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690346289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3690346289
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1492459677
Short name T731
Test name
Test status
Simulation time 3498513903 ps
CPU time 8 seconds
Started Jul 10 05:42:29 PM PDT 24
Finished Jul 10 05:42:38 PM PDT 24
Peak memory 233832 kb
Host smart-04ea1dbc-fba8-4046-963a-21d76c946393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492459677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1492459677
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1206806110
Short name T524
Test name
Test status
Simulation time 15995455398 ps
CPU time 13.07 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:35 PM PDT 24
Peak memory 225616 kb
Host smart-82933933-1fa9-41f1-b35e-931e5e51a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206806110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1206806110
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3849514209
Short name T620
Test name
Test status
Simulation time 2961752891 ps
CPU time 11.24 seconds
Started Jul 10 05:42:26 PM PDT 24
Finished Jul 10 05:42:38 PM PDT 24
Peak memory 223280 kb
Host smart-0de3930a-d545-45cd-836a-cfb67b4e4641
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3849514209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3849514209
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.184488965
Short name T798
Test name
Test status
Simulation time 7863879908 ps
CPU time 23.27 seconds
Started Jul 10 05:42:21 PM PDT 24
Finished Jul 10 05:42:46 PM PDT 24
Peak memory 217456 kb
Host smart-015592de-c67b-41e0-8a67-abec174533b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184488965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.184488965
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1221560063
Short name T336
Test name
Test status
Simulation time 1227737498 ps
CPU time 8.7 seconds
Started Jul 10 05:42:22 PM PDT 24
Finished Jul 10 05:42:32 PM PDT 24
Peak memory 217280 kb
Host smart-0c6e424b-6a67-4f8c-837e-0969c051e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221560063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1221560063
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1453590814
Short name T377
Test name
Test status
Simulation time 67520485 ps
CPU time 1.49 seconds
Started Jul 10 05:42:25 PM PDT 24
Finished Jul 10 05:42:27 PM PDT 24
Peak memory 217360 kb
Host smart-504b52df-a32d-463a-8ec6-ebb0797a1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453590814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1453590814
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1221434399
Short name T865
Test name
Test status
Simulation time 17811662 ps
CPU time 0.71 seconds
Started Jul 10 05:42:23 PM PDT 24
Finished Jul 10 05:42:25 PM PDT 24
Peak memory 206920 kb
Host smart-433ba72d-5c1f-4314-8a58-f5ff3767c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221434399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1221434399
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4002218889
Short name T597
Test name
Test status
Simulation time 606524512 ps
CPU time 12.5 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:42:40 PM PDT 24
Peak memory 234952 kb
Host smart-3160871c-0c24-4514-b8a8-936df501967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002218889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4002218889
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1872678032
Short name T855
Test name
Test status
Simulation time 199538547 ps
CPU time 4.28 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:42:37 PM PDT 24
Peak memory 233752 kb
Host smart-fe4e16c7-5a92-4789-895a-7af519d040f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872678032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1872678032
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1899219043
Short name T704
Test name
Test status
Simulation time 23413362 ps
CPU time 0.78 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:42:29 PM PDT 24
Peak memory 207336 kb
Host smart-a6562a43-d4ea-4bca-86ab-969e33840de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899219043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1899219043
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1077943359
Short name T43
Test name
Test status
Simulation time 327594134820 ps
CPU time 540.41 seconds
Started Jul 10 05:42:34 PM PDT 24
Finished Jul 10 05:51:35 PM PDT 24
Peak memory 263644 kb
Host smart-e25de9f1-932b-4a05-bff1-b78e28c30073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077943359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1077943359
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1829663102
Short name T266
Test name
Test status
Simulation time 128107673842 ps
CPU time 298.39 seconds
Started Jul 10 05:42:35 PM PDT 24
Finished Jul 10 05:47:35 PM PDT 24
Peak memory 252244 kb
Host smart-8b14ee8f-c453-4878-8138-262ddec74af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829663102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1829663102
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1426053269
Short name T305
Test name
Test status
Simulation time 16755037906 ps
CPU time 90.19 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:44:04 PM PDT 24
Peak memory 241772 kb
Host smart-041e9632-299f-42de-b08a-d3dce1afbf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426053269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1426053269
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1421838971
Short name T369
Test name
Test status
Simulation time 3854959256 ps
CPU time 31.33 seconds
Started Jul 10 05:42:35 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 249964 kb
Host smart-7c4e1bd7-e7a6-42ff-b9df-c5287bfbf2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421838971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1421838971
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3575495888
Short name T268
Test name
Test status
Simulation time 10870388802 ps
CPU time 149.53 seconds
Started Jul 10 05:42:35 PM PDT 24
Finished Jul 10 05:45:06 PM PDT 24
Peak memory 266204 kb
Host smart-42089aaa-f138-4159-9dfe-470597570942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575495888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3575495888
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3431916628
Short name T433
Test name
Test status
Simulation time 81298540 ps
CPU time 2.57 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:42:37 PM PDT 24
Peak memory 233732 kb
Host smart-fae7afd1-5ac1-498a-895b-8c57bf1e28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431916628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3431916628
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3866849282
Short name T556
Test name
Test status
Simulation time 3646976439 ps
CPU time 35.15 seconds
Started Jul 10 05:42:35 PM PDT 24
Finished Jul 10 05:43:11 PM PDT 24
Peak memory 225660 kb
Host smart-633f853f-02bc-4976-93c6-cb22cfa4fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866849282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3866849282
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1919599301
Short name T894
Test name
Test status
Simulation time 17092241 ps
CPU time 1.08 seconds
Started Jul 10 05:42:30 PM PDT 24
Finished Jul 10 05:42:31 PM PDT 24
Peak memory 217640 kb
Host smart-091cf4d7-c24a-46bd-9b25-f4ee43262df3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919599301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1919599301
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3312612767
Short name T432
Test name
Test status
Simulation time 7114220337 ps
CPU time 9.7 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:42:44 PM PDT 24
Peak memory 233760 kb
Host smart-5026b71e-0819-4ac4-8450-7562ca7f9e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312612767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3312612767
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2736817529
Short name T353
Test name
Test status
Simulation time 2510368265 ps
CPU time 11.78 seconds
Started Jul 10 05:42:31 PM PDT 24
Finished Jul 10 05:42:43 PM PDT 24
Peak memory 241648 kb
Host smart-54d9e42a-077c-4187-85cf-e09b458a4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736817529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2736817529
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.808750528
Short name T139
Test name
Test status
Simulation time 1038873532 ps
CPU time 10.54 seconds
Started Jul 10 05:42:33 PM PDT 24
Finished Jul 10 05:42:45 PM PDT 24
Peak memory 221624 kb
Host smart-49e634bd-1930-47d7-ad1e-607034138e83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=808750528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.808750528
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.255289059
Short name T549
Test name
Test status
Simulation time 172466689 ps
CPU time 0.96 seconds
Started Jul 10 05:42:32 PM PDT 24
Finished Jul 10 05:42:34 PM PDT 24
Peak memory 206668 kb
Host smart-bf2fae12-5af2-4637-b265-068ab01c9ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255289059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.255289059
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4087379780
Short name T304
Test name
Test status
Simulation time 6322624760 ps
CPU time 15.45 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:42:44 PM PDT 24
Peak memory 217492 kb
Host smart-166b4f8e-d8dd-4023-abb8-57ea23c82e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087379780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4087379780
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2227733920
Short name T587
Test name
Test status
Simulation time 2703566323 ps
CPU time 4.86 seconds
Started Jul 10 05:42:27 PM PDT 24
Finished Jul 10 05:42:33 PM PDT 24
Peak memory 217372 kb
Host smart-cc3df93a-ed0c-41a1-8dac-d81686755de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227733920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2227733920
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2129979368
Short name T492
Test name
Test status
Simulation time 684382397 ps
CPU time 3.21 seconds
Started Jul 10 05:42:28 PM PDT 24
Finished Jul 10 05:42:32 PM PDT 24
Peak memory 217288 kb
Host smart-d9889a0f-1561-4542-8ef3-c3fb1a40c064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129979368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2129979368
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.189872894
Short name T351
Test name
Test status
Simulation time 79755850 ps
CPU time 0.97 seconds
Started Jul 10 05:42:30 PM PDT 24
Finished Jul 10 05:42:31 PM PDT 24
Peak memory 207980 kb
Host smart-40d05041-5039-470b-aa5a-c6822689eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189872894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.189872894
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3290461826
Short name T338
Test name
Test status
Simulation time 744943808 ps
CPU time 4.6 seconds
Started Jul 10 05:42:35 PM PDT 24
Finished Jul 10 05:42:41 PM PDT 24
Peak memory 225592 kb
Host smart-cfbe5907-b099-488d-b604-34bafab6fcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290461826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3290461826
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3809031274
Short name T635
Test name
Test status
Simulation time 12709789 ps
CPU time 0.72 seconds
Started Jul 10 05:42:45 PM PDT 24
Finished Jul 10 05:42:47 PM PDT 24
Peak memory 206296 kb
Host smart-9e7365bd-cda0-4219-bf5b-3a6215450d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809031274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3809031274
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4157815025
Short name T92
Test name
Test status
Simulation time 243773358 ps
CPU time 4.96 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:46 PM PDT 24
Peak memory 233728 kb
Host smart-19278d07-84e5-4cd2-a8f5-0b5eca98b16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157815025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4157815025
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.330251873
Short name T386
Test name
Test status
Simulation time 48365226 ps
CPU time 0.82 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 05:42:42 PM PDT 24
Peak memory 206472 kb
Host smart-4a29a08e-506b-4811-a191-3481c703a522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330251873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.330251873
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3559265678
Short name T823
Test name
Test status
Simulation time 3182952200 ps
CPU time 47.48 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:43:28 PM PDT 24
Peak memory 236832 kb
Host smart-e20e6e83-86a0-4bfd-ae62-717e5d6d18a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559265678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3559265678
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3698980078
Short name T879
Test name
Test status
Simulation time 7816219730 ps
CPU time 48.08 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:43:29 PM PDT 24
Peak memory 233968 kb
Host smart-04bd9108-fbc3-4270-b28f-8b40293d3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698980078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3698980078
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2174447579
Short name T324
Test name
Test status
Simulation time 2726812832 ps
CPU time 4.43 seconds
Started Jul 10 05:42:39 PM PDT 24
Finished Jul 10 05:42:45 PM PDT 24
Peak memory 218756 kb
Host smart-f6177562-a0d0-4d63-90cf-037a5d785833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174447579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2174447579
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1211271316
Short name T137
Test name
Test status
Simulation time 424866856 ps
CPU time 5.41 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:47 PM PDT 24
Peak memory 235616 kb
Host smart-5890564a-43c3-438d-846c-96128c2b65cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211271316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1211271316
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3372366185
Short name T164
Test name
Test status
Simulation time 10491276129 ps
CPU time 114.29 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:44:36 PM PDT 24
Peak memory 258032 kb
Host smart-c07969c3-8da9-4098-88c4-7a972d07d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372366185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3372366185
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2825085085
Short name T188
Test name
Test status
Simulation time 351538432 ps
CPU time 6.5 seconds
Started Jul 10 05:42:38 PM PDT 24
Finished Jul 10 05:42:46 PM PDT 24
Peak memory 225460 kb
Host smart-649a7668-edc2-4fef-852b-5a5162203883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825085085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2825085085
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2307469886
Short name T460
Test name
Test status
Simulation time 2038956353 ps
CPU time 16.52 seconds
Started Jul 10 05:42:42 PM PDT 24
Finished Jul 10 05:42:59 PM PDT 24
Peak memory 233752 kb
Host smart-89871fb9-50ca-41af-a366-244ac6a966b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307469886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2307469886
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1495937002
Short name T715
Test name
Test status
Simulation time 34288203 ps
CPU time 1.15 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:42 PM PDT 24
Peak memory 217640 kb
Host smart-73073822-22b3-4e30-96ec-a52f52d24ee2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495937002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1495937002
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4238837967
Short name T218
Test name
Test status
Simulation time 2625051522 ps
CPU time 10.74 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 05:42:52 PM PDT 24
Peak memory 233904 kb
Host smart-078b8ed7-6ae9-4dbd-aac2-57b0e0f31530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238837967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4238837967
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1291344916
Short name T231
Test name
Test status
Simulation time 12197328935 ps
CPU time 15.05 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:56 PM PDT 24
Peak memory 233872 kb
Host smart-d4a35e8a-be37-4a0c-9932-7f5d5e6ad1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291344916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1291344916
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.156895580
Short name T571
Test name
Test status
Simulation time 1536058108 ps
CPU time 21.35 seconds
Started Jul 10 05:42:39 PM PDT 24
Finished Jul 10 05:43:01 PM PDT 24
Peak memory 221976 kb
Host smart-89d84964-5c22-4ac2-841f-32b34120f8c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=156895580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.156895580
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.668753824
Short name T63
Test name
Test status
Simulation time 127877962123 ps
CPU time 1120.56 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 06:01:22 PM PDT 24
Peak memory 291372 kb
Host smart-4fef80bd-6413-4af0-a34e-d7051267dc6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668753824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.668753824
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1622054662
Short name T844
Test name
Test status
Simulation time 1514074543 ps
CPU time 8.9 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 05:42:51 PM PDT 24
Peak memory 217404 kb
Host smart-13c5c5fd-2301-4c09-8676-452851d50323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622054662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1622054662
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1686399523
Short name T603
Test name
Test status
Simulation time 1310717782 ps
CPU time 8.06 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:49 PM PDT 24
Peak memory 217360 kb
Host smart-9452c338-c16b-454b-b942-82c249c6231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686399523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1686399523
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4104632589
Short name T705
Test name
Test status
Simulation time 53286486 ps
CPU time 0.9 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 05:42:43 PM PDT 24
Peak memory 207976 kb
Host smart-0206d66f-df9c-49df-87cf-ebc4a5a1bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104632589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4104632589
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.609389318
Short name T395
Test name
Test status
Simulation time 122240609 ps
CPU time 1.1 seconds
Started Jul 10 05:42:40 PM PDT 24
Finished Jul 10 05:42:42 PM PDT 24
Peak memory 206960 kb
Host smart-50a855c8-d150-465a-ad0c-8c293dfd1cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609389318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.609389318
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2243305759
Short name T686
Test name
Test status
Simulation time 14309961398 ps
CPU time 18.27 seconds
Started Jul 10 05:42:41 PM PDT 24
Finished Jul 10 05:43:00 PM PDT 24
Peak memory 241748 kb
Host smart-eb7d14b5-1e69-4edc-b250-9354f9d8e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243305759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2243305759
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2133041228
Short name T712
Test name
Test status
Simulation time 93648776 ps
CPU time 0.72 seconds
Started Jul 10 05:42:52 PM PDT 24
Finished Jul 10 05:42:54 PM PDT 24
Peak memory 206384 kb
Host smart-06ef26dc-70b6-46f0-9af5-5f221d99b116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133041228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2133041228
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.51113588
Short name T236
Test name
Test status
Simulation time 10109422082 ps
CPU time 26.34 seconds
Started Jul 10 05:42:45 PM PDT 24
Finished Jul 10 05:43:12 PM PDT 24
Peak memory 233784 kb
Host smart-8073b7b5-f803-465a-bdfd-7602b9c66170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51113588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.51113588
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2076374776
Short name T764
Test name
Test status
Simulation time 135558385 ps
CPU time 0.8 seconds
Started Jul 10 05:42:45 PM PDT 24
Finished Jul 10 05:42:47 PM PDT 24
Peak memory 207784 kb
Host smart-6aef8849-2258-431e-a12e-80735ed03e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076374776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2076374776
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.973815755
Short name T945
Test name
Test status
Simulation time 3227709433 ps
CPU time 45.13 seconds
Started Jul 10 05:42:52 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 250304 kb
Host smart-08db3e3e-eac3-4df3-af5d-0e42522d136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973815755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.973815755
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3548606033
Short name T126
Test name
Test status
Simulation time 37265885365 ps
CPU time 117.38 seconds
Started Jul 10 05:42:52 PM PDT 24
Finished Jul 10 05:44:51 PM PDT 24
Peak memory 258548 kb
Host smart-72de9126-2bcc-4098-889a-14d13850990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548606033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3548606033
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1210656060
Short name T912
Test name
Test status
Simulation time 3157738193 ps
CPU time 27.12 seconds
Started Jul 10 05:42:49 PM PDT 24
Finished Jul 10 05:43:17 PM PDT 24
Peak memory 250292 kb
Host smart-cc8e6299-77fa-4811-b150-69c40b15cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210656060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1210656060
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3975291768
Short name T854
Test name
Test status
Simulation time 8672627285 ps
CPU time 15.9 seconds
Started Jul 10 05:42:47 PM PDT 24
Finished Jul 10 05:43:04 PM PDT 24
Peak memory 233872 kb
Host smart-96f8c989-f4c9-4200-aaeb-ed09af7043d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975291768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3975291768
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.893174316
Short name T846
Test name
Test status
Simulation time 524749943 ps
CPU time 3.7 seconds
Started Jul 10 05:42:48 PM PDT 24
Finished Jul 10 05:42:53 PM PDT 24
Peak memory 233732 kb
Host smart-267d0c61-6d84-4d8b-9a25-dd52ae44c2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893174316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.893174316
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2742116607
Short name T701
Test name
Test status
Simulation time 60464567 ps
CPU time 1.02 seconds
Started Jul 10 05:42:48 PM PDT 24
Finished Jul 10 05:42:49 PM PDT 24
Peak memory 217628 kb
Host smart-b895a7b2-b5b8-4514-be0d-a92f7bd14578
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742116607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2742116607
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3930747088
Short name T370
Test name
Test status
Simulation time 505826991 ps
CPU time 2.74 seconds
Started Jul 10 05:42:44 PM PDT 24
Finished Jul 10 05:42:48 PM PDT 24
Peak memory 225428 kb
Host smart-8c6c4dcb-bd6b-4875-be61-1cc3c637faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930747088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3930747088
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.780309709
Short name T449
Test name
Test status
Simulation time 10156582521 ps
CPU time 19.67 seconds
Started Jul 10 05:42:46 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 233912 kb
Host smart-6519e045-a18b-4e04-b02b-6193afa5fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780309709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.780309709
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4239362849
Short name T352
Test name
Test status
Simulation time 1341427922 ps
CPU time 7.02 seconds
Started Jul 10 05:42:46 PM PDT 24
Finished Jul 10 05:42:54 PM PDT 24
Peak memory 221624 kb
Host smart-9b54d168-3cb8-49be-a80a-a5bdbeca3c46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4239362849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4239362849
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2425893934
Short name T852
Test name
Test status
Simulation time 2962068530 ps
CPU time 15.94 seconds
Started Jul 10 05:42:49 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 217420 kb
Host smart-32de51d4-1320-4401-b59f-ec96ca7d911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425893934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2425893934
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2835588595
Short name T344
Test name
Test status
Simulation time 2477058005 ps
CPU time 9.95 seconds
Started Jul 10 05:42:47 PM PDT 24
Finished Jul 10 05:42:57 PM PDT 24
Peak memory 217444 kb
Host smart-2989f65e-94e1-4dc5-bf40-06dccd3f4827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835588595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2835588595
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1343091665
Short name T826
Test name
Test status
Simulation time 44358560 ps
CPU time 2.36 seconds
Started Jul 10 05:42:46 PM PDT 24
Finished Jul 10 05:42:50 PM PDT 24
Peak memory 217372 kb
Host smart-d1ffbc21-62c2-4ffc-b8c1-1dcf1e15d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343091665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1343091665
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2223509981
Short name T761
Test name
Test status
Simulation time 96028734 ps
CPU time 0.97 seconds
Started Jul 10 05:42:48 PM PDT 24
Finished Jul 10 05:42:50 PM PDT 24
Peak memory 206896 kb
Host smart-817dc102-615f-4784-9c1a-7b1073242bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223509981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2223509981
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2230720726
Short name T332
Test name
Test status
Simulation time 1026811136 ps
CPU time 9.33 seconds
Started Jul 10 05:42:46 PM PDT 24
Finished Jul 10 05:42:56 PM PDT 24
Peak memory 234808 kb
Host smart-71153290-a1e9-4a74-883e-75ce0ef1a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230720726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2230720726
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.117245479
Short name T670
Test name
Test status
Simulation time 13079209 ps
CPU time 0.75 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:01 PM PDT 24
Peak memory 206324 kb
Host smart-8c057c93-eeb9-42a3-bb65-30330076d7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117245479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.117245479
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4128831987
Short name T233
Test name
Test status
Simulation time 120693727 ps
CPU time 2.4 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:03 PM PDT 24
Peak memory 233716 kb
Host smart-cec83a09-4a1a-4f3a-8928-a117666513f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128831987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4128831987
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4270358285
Short name T604
Test name
Test status
Simulation time 23819124 ps
CPU time 0.78 seconds
Started Jul 10 05:42:51 PM PDT 24
Finished Jul 10 05:42:53 PM PDT 24
Peak memory 207428 kb
Host smart-46ae35d5-8d0d-4175-a1c3-4029250b91f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270358285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4270358285
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3244890652
Short name T450
Test name
Test status
Simulation time 8346121137 ps
CPU time 14.56 seconds
Started Jul 10 05:42:58 PM PDT 24
Finished Jul 10 05:43:13 PM PDT 24
Peak memory 225736 kb
Host smart-f03da38a-9b2f-4e6a-bb53-ea24d7f02f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244890652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3244890652
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1847579621
Short name T129
Test name
Test status
Simulation time 55578441921 ps
CPU time 193.38 seconds
Started Jul 10 05:42:58 PM PDT 24
Finished Jul 10 05:46:13 PM PDT 24
Peak memory 250408 kb
Host smart-fdc097e0-b9fc-4ec6-8fd6-84404ea6584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847579621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1847579621
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.770210118
Short name T973
Test name
Test status
Simulation time 9986341185 ps
CPU time 59.17 seconds
Started Jul 10 05:42:57 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 234284 kb
Host smart-0dc9534b-da93-4c0e-9861-f91214433a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770210118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.770210118
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3111423272
Short name T662
Test name
Test status
Simulation time 2975880029 ps
CPU time 11.8 seconds
Started Jul 10 05:43:03 PM PDT 24
Finished Jul 10 05:43:15 PM PDT 24
Peak memory 233912 kb
Host smart-4082bf54-5f40-477e-9c01-a414a3f44ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111423272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3111423272
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3816395737
Short name T347
Test name
Test status
Simulation time 1612390072 ps
CPU time 6.54 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 233796 kb
Host smart-25f430dc-d1c1-47c1-9c5d-a52cf7f6baf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816395737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3816395737
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.587924166
Short name T971
Test name
Test status
Simulation time 63055857 ps
CPU time 1.09 seconds
Started Jul 10 05:42:54 PM PDT 24
Finished Jul 10 05:42:56 PM PDT 24
Peak memory 217640 kb
Host smart-d2dc88d5-0665-4a97-a747-10ff477c2d36
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587924166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.587924166
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1316056379
Short name T828
Test name
Test status
Simulation time 36869966704 ps
CPU time 13.37 seconds
Started Jul 10 05:42:54 PM PDT 24
Finished Jul 10 05:43:08 PM PDT 24
Peak memory 233736 kb
Host smart-ab4bda66-07b1-4df0-b81b-010ff8a4d284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316056379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1316056379
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2090891343
Short name T941
Test name
Test status
Simulation time 132269213 ps
CPU time 2.64 seconds
Started Jul 10 05:43:09 PM PDT 24
Finished Jul 10 05:43:13 PM PDT 24
Peak memory 225560 kb
Host smart-62aa9334-06d6-4c65-8616-460b99b082e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090891343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2090891343
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.172411522
Short name T546
Test name
Test status
Simulation time 210722885 ps
CPU time 4.6 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:04 PM PDT 24
Peak memory 221656 kb
Host smart-83bd90ea-53e9-427e-ad99-77e36989627a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=172411522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.172411522
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2213613687
Short name T732
Test name
Test status
Simulation time 55644514767 ps
CPU time 264.17 seconds
Started Jul 10 05:42:58 PM PDT 24
Finished Jul 10 05:47:22 PM PDT 24
Peak memory 264468 kb
Host smart-5feb09fe-b3a5-4378-836d-94131baf82d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213613687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2213613687
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.948564587
Short name T723
Test name
Test status
Simulation time 11120166508 ps
CPU time 9.22 seconds
Started Jul 10 05:42:54 PM PDT 24
Finished Jul 10 05:43:04 PM PDT 24
Peak memory 217512 kb
Host smart-a1cd9aec-ccfa-40c2-83f8-788dd0a8f150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948564587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.948564587
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3329300150
Short name T619
Test name
Test status
Simulation time 2970304841 ps
CPU time 9.74 seconds
Started Jul 10 05:43:00 PM PDT 24
Finished Jul 10 05:43:11 PM PDT 24
Peak memory 217448 kb
Host smart-6507c852-d935-4271-9a50-1f47c6ae3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329300150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3329300150
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3289201683
Short name T366
Test name
Test status
Simulation time 254190674 ps
CPU time 10.86 seconds
Started Jul 10 05:42:53 PM PDT 24
Finished Jul 10 05:43:05 PM PDT 24
Peak memory 217348 kb
Host smart-aeea1424-8441-4f89-8fe4-35921848c3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289201683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3289201683
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3578474916
Short name T906
Test name
Test status
Simulation time 23087622 ps
CPU time 0.72 seconds
Started Jul 10 05:42:52 PM PDT 24
Finished Jul 10 05:42:54 PM PDT 24
Peak memory 206888 kb
Host smart-ec88159d-99cc-4cb4-b42a-0a067f35a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578474916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3578474916
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1143404913
Short name T592
Test name
Test status
Simulation time 3417770796 ps
CPU time 6.3 seconds
Started Jul 10 05:43:00 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 242032 kb
Host smart-6190be8d-369d-47c4-95e4-e937adb3a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143404913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1143404913
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3738222553
Short name T1000
Test name
Test status
Simulation time 42622518 ps
CPU time 0.72 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 206368 kb
Host smart-a25cda09-4ce4-47df-bc0b-ce6152388904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738222553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3738222553
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3836061329
Short name T676
Test name
Test status
Simulation time 512661582 ps
CPU time 3.01 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:04 PM PDT 24
Peak memory 225524 kb
Host smart-fb8475ed-d876-4272-aa19-b30f6914b5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836061329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3836061329
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3369520279
Short name T12
Test name
Test status
Simulation time 69170564 ps
CPU time 0.8 seconds
Started Jul 10 05:43:00 PM PDT 24
Finished Jul 10 05:43:02 PM PDT 24
Peak memory 207824 kb
Host smart-d37aebac-7803-4545-a506-f48a135e70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369520279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3369520279
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.137038952
Short name T380
Test name
Test status
Simulation time 2195369700 ps
CPU time 14.94 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:20 PM PDT 24
Peak memory 238196 kb
Host smart-b0f1f7a8-f1c8-4d41-ade5-5e7a5a947876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137038952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.137038952
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3940607320
Short name T659
Test name
Test status
Simulation time 9332052269 ps
CPU time 42.27 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 255464 kb
Host smart-c72e198e-fe2f-4606-ad44-3b23165d1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940607320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3940607320
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1585392878
Short name T58
Test name
Test status
Simulation time 2768292253 ps
CPU time 10.84 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:19 PM PDT 24
Peak memory 224132 kb
Host smart-6c7c4e2c-7114-4b07-adc8-63b451c1b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585392878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1585392878
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.574954083
Short name T657
Test name
Test status
Simulation time 400272574 ps
CPU time 5.18 seconds
Started Jul 10 05:43:06 PM PDT 24
Finished Jul 10 05:43:12 PM PDT 24
Peak memory 233792 kb
Host smart-fe30b3b7-92f5-47db-8e9f-58e3905c1a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574954083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.574954083
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1165652147
Short name T401
Test name
Test status
Simulation time 69176312130 ps
CPU time 112.88 seconds
Started Jul 10 05:43:05 PM PDT 24
Finished Jul 10 05:44:59 PM PDT 24
Peak memory 242068 kb
Host smart-f22773a4-01da-485c-b2f2-22cc4a2c440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165652147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1165652147
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.673506679
Short name T5
Test name
Test status
Simulation time 2805177388 ps
CPU time 27.96 seconds
Started Jul 10 05:43:00 PM PDT 24
Finished Jul 10 05:43:29 PM PDT 24
Peak memory 233836 kb
Host smart-bac7bb7c-96cd-4982-a902-c1bc795cab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673506679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.673506679
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.376292402
Short name T940
Test name
Test status
Simulation time 1104675146 ps
CPU time 14.34 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:22 PM PDT 24
Peak memory 233728 kb
Host smart-59b9d9fe-8a94-4571-896d-de2c4c76bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376292402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.376292402
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2808152319
Short name T37
Test name
Test status
Simulation time 31261679 ps
CPU time 1.07 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:01 PM PDT 24
Peak memory 218876 kb
Host smart-867d1b84-abcf-43e7-a6ff-21049dd15c9c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808152319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2808152319
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.486966079
Short name T142
Test name
Test status
Simulation time 104612722 ps
CPU time 2.17 seconds
Started Jul 10 05:43:06 PM PDT 24
Finished Jul 10 05:43:10 PM PDT 24
Peak memory 233444 kb
Host smart-45c349f2-dff2-46f5-8a45-5f46db991b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486966079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.486966079
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2149562915
Short name T194
Test name
Test status
Simulation time 9837067246 ps
CPU time 29.3 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:37 PM PDT 24
Peak memory 242000 kb
Host smart-f0289d02-b901-4c62-8598-c0e9a6d0b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149562915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2149562915
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2684292605
Short name T134
Test name
Test status
Simulation time 908202974 ps
CPU time 5.27 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:13 PM PDT 24
Peak memory 221224 kb
Host smart-290914fe-4d56-444d-b541-022e984933eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2684292605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2684292605
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2598991593
Short name T696
Test name
Test status
Simulation time 1415017892 ps
CPU time 11.91 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:12 PM PDT 24
Peak memory 217280 kb
Host smart-1a78aa67-4ec1-417c-a3b4-67a96ff594b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598991593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2598991593
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1241062466
Short name T843
Test name
Test status
Simulation time 460901748 ps
CPU time 2.21 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:02 PM PDT 24
Peak memory 208828 kb
Host smart-6951263c-692a-4f99-a19f-bb538b890938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241062466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1241062466
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2266057280
Short name T509
Test name
Test status
Simulation time 248521267 ps
CPU time 3.99 seconds
Started Jul 10 05:42:59 PM PDT 24
Finished Jul 10 05:43:04 PM PDT 24
Peak memory 217364 kb
Host smart-ffc63de6-167d-41ed-9df3-279fe087ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266057280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2266057280
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.511687375
Short name T832
Test name
Test status
Simulation time 56552926 ps
CPU time 0.82 seconds
Started Jul 10 05:43:07 PM PDT 24
Finished Jul 10 05:43:09 PM PDT 24
Peak memory 206948 kb
Host smart-758efffc-11c7-439f-9d5c-06d9aa05220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511687375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.511687375
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.123224908
Short name T257
Test name
Test status
Simulation time 26639050500 ps
CPU time 18.12 seconds
Started Jul 10 05:42:57 PM PDT 24
Finished Jul 10 05:43:16 PM PDT 24
Peak memory 233812 kb
Host smart-7e5737d3-1095-494c-8277-3edf8b703196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123224908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.123224908
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3587145279
Short name T914
Test name
Test status
Simulation time 41231316 ps
CPU time 0.73 seconds
Started Jul 10 05:43:14 PM PDT 24
Finished Jul 10 05:43:15 PM PDT 24
Peak memory 205788 kb
Host smart-797ef9f7-1985-4ea5-a7d0-59a4e9652bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587145279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3587145279
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3056540559
Short name T765
Test name
Test status
Simulation time 3468939885 ps
CPU time 8.9 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:14 PM PDT 24
Peak memory 225592 kb
Host smart-5c261829-27f7-4aef-87a3-6328d8d4f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056540559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3056540559
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3300161406
Short name T313
Test name
Test status
Simulation time 19629580 ps
CPU time 0.79 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 207848 kb
Host smart-b1e2f723-c1f7-4028-87e1-0aaeed7308a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300161406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3300161406
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.285634669
Short name T735
Test name
Test status
Simulation time 6747160089 ps
CPU time 79.62 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:44:25 PM PDT 24
Peak memory 263792 kb
Host smart-84db8de6-3854-4793-8bd3-adec8d8e9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285634669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.285634669
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1368581292
Short name T483
Test name
Test status
Simulation time 11585550323 ps
CPU time 81.45 seconds
Started Jul 10 05:43:05 PM PDT 24
Finished Jul 10 05:44:27 PM PDT 24
Peak memory 242184 kb
Host smart-31a29267-1e63-4ad9-a27f-3ed873aee059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368581292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1368581292
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4242857958
Short name T919
Test name
Test status
Simulation time 39806723041 ps
CPU time 404.26 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:50:02 PM PDT 24
Peak memory 258404 kb
Host smart-98b3095a-225c-470a-a0d9-fc1f04235dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242857958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4242857958
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1086621271
Short name T459
Test name
Test status
Simulation time 4580346345 ps
CPU time 35.4 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:40 PM PDT 24
Peak memory 235936 kb
Host smart-ed1f2ffa-8a2c-4091-a47c-cf3753e710c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086621271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1086621271
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2279230471
Short name T198
Test name
Test status
Simulation time 44211969158 ps
CPU time 185.01 seconds
Started Jul 10 05:43:02 PM PDT 24
Finished Jul 10 05:46:08 PM PDT 24
Peak memory 258228 kb
Host smart-298b5fe2-6267-40bf-8c29-b03d10d1bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279230471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2279230471
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.588030237
Short name T589
Test name
Test status
Simulation time 6341736967 ps
CPU time 17.53 seconds
Started Jul 10 05:43:06 PM PDT 24
Finished Jul 10 05:43:24 PM PDT 24
Peak memory 233860 kb
Host smart-9ff03ae6-67e0-4acb-8b37-6ae354f0383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588030237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.588030237
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2106387802
Short name T570
Test name
Test status
Simulation time 216324683 ps
CPU time 4.77 seconds
Started Jul 10 05:43:02 PM PDT 24
Finished Jul 10 05:43:08 PM PDT 24
Peak memory 225600 kb
Host smart-aeb13e4c-b0f6-4966-99a2-5019ec27efc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106387802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2106387802
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3918771175
Short name T795
Test name
Test status
Simulation time 16705399 ps
CPU time 1.06 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 217580 kb
Host smart-36174cac-1752-4a62-8102-83e0674186ab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918771175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3918771175
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3104421402
Short name T498
Test name
Test status
Simulation time 469181352 ps
CPU time 3.51 seconds
Started Jul 10 05:43:03 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 225500 kb
Host smart-5ad7be2c-9bbc-4e89-b326-0ce8c7cb951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104421402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3104421402
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4072972356
Short name T426
Test name
Test status
Simulation time 380881042 ps
CPU time 4.34 seconds
Started Jul 10 05:43:06 PM PDT 24
Finished Jul 10 05:43:11 PM PDT 24
Peak memory 225524 kb
Host smart-8e4415ef-e891-4207-a929-a4e91105e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072972356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4072972356
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1799462246
Short name T766
Test name
Test status
Simulation time 2727790101 ps
CPU time 12.5 seconds
Started Jul 10 05:43:03 PM PDT 24
Finished Jul 10 05:43:17 PM PDT 24
Peak memory 224024 kb
Host smart-d2fd77dd-47ca-42ca-b942-7ee1bc4612eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1799462246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1799462246
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2721981325
Short name T653
Test name
Test status
Simulation time 3975490628 ps
CPU time 25.09 seconds
Started Jul 10 05:43:03 PM PDT 24
Finished Jul 10 05:43:29 PM PDT 24
Peak memory 217496 kb
Host smart-49aa610b-5cab-4f9b-90f7-12997903e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721981325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2721981325
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.57555934
Short name T90
Test name
Test status
Simulation time 6264012371 ps
CPU time 3.73 seconds
Started Jul 10 05:43:04 PM PDT 24
Finished Jul 10 05:43:09 PM PDT 24
Peak memory 217452 kb
Host smart-ae99d565-4bcd-46ab-9191-ee0c346bbe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57555934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.57555934
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3692735819
Short name T325
Test name
Test status
Simulation time 208688459 ps
CPU time 2.58 seconds
Started Jul 10 05:43:03 PM PDT 24
Finished Jul 10 05:43:06 PM PDT 24
Peak memory 217372 kb
Host smart-244ea0f8-b93e-48c4-9074-83e3736931ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692735819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3692735819
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1097487242
Short name T361
Test name
Test status
Simulation time 210750687 ps
CPU time 0.85 seconds
Started Jul 10 05:43:05 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 206896 kb
Host smart-251e4a12-0ed8-4a18-9621-ee31581fb3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097487242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1097487242
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1173288949
Short name T167
Test name
Test status
Simulation time 527049420 ps
CPU time 4.55 seconds
Started Jul 10 05:43:05 PM PDT 24
Finished Jul 10 05:43:11 PM PDT 24
Peak memory 225520 kb
Host smart-d0f096f8-586d-400a-a124-6a4e17ab6e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173288949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1173288949
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1537500562
Short name T1005
Test name
Test status
Simulation time 46625485 ps
CPU time 0.73 seconds
Started Jul 10 05:43:17 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 206312 kb
Host smart-c74aa9e1-e1ef-44f8-9d4a-88fb624fa5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537500562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1537500562
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1951752128
Short name T494
Test name
Test status
Simulation time 133540572 ps
CPU time 2.78 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:15 PM PDT 24
Peak memory 233736 kb
Host smart-4bca2763-2da8-4f5b-bf31-8a949a54251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951752128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1951752128
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2785630548
Short name T638
Test name
Test status
Simulation time 232058608 ps
CPU time 0.84 seconds
Started Jul 10 05:43:13 PM PDT 24
Finished Jul 10 05:43:15 PM PDT 24
Peak memory 207496 kb
Host smart-e6ca9850-7f8a-4e8d-9633-f1de8b34c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785630548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2785630548
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3630522710
Short name T271
Test name
Test status
Simulation time 9070852410 ps
CPU time 101.81 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:44:53 PM PDT 24
Peak memory 252620 kb
Host smart-956683e7-7cf2-452e-a252-b861093f3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630522710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3630522710
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3919283412
Short name T858
Test name
Test status
Simulation time 20533743611 ps
CPU time 209.65 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 266988 kb
Host smart-09cab10c-f60a-403f-b077-0fa5f2d574fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919283412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3919283412
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4183013241
Short name T607
Test name
Test status
Simulation time 72569333122 ps
CPU time 237.07 seconds
Started Jul 10 05:43:12 PM PDT 24
Finished Jul 10 05:47:10 PM PDT 24
Peak memory 254928 kb
Host smart-8a24d0ec-0922-4f0d-baa7-aabb7f3a3634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183013241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4183013241
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.836561715
Short name T551
Test name
Test status
Simulation time 110684788 ps
CPU time 3.87 seconds
Started Jul 10 05:43:13 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 233712 kb
Host smart-5800d316-085b-4d03-9b4b-d887723916d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836561715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.836561715
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2579103920
Short name T911
Test name
Test status
Simulation time 394949536 ps
CPU time 5.22 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:17 PM PDT 24
Peak memory 233728 kb
Host smart-171ebe87-7ed4-4abb-9c08-f64d57add3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579103920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2579103920
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3459731507
Short name T38
Test name
Test status
Simulation time 16504646 ps
CPU time 1.07 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:13 PM PDT 24
Peak memory 217652 kb
Host smart-5bffc090-59b8-4c93-93ca-c1509df2fa2b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459731507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3459731507
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.996870001
Short name T526
Test name
Test status
Simulation time 141980932 ps
CPU time 2.62 seconds
Started Jul 10 05:43:15 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 233728 kb
Host smart-9d68ebf2-2ea8-479e-b190-8369b53874db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996870001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.996870001
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1624294113
Short name T612
Test name
Test status
Simulation time 913178458 ps
CPU time 8.18 seconds
Started Jul 10 05:43:12 PM PDT 24
Finished Jul 10 05:43:21 PM PDT 24
Peak memory 234752 kb
Host smart-125be0c5-e3d1-4398-b29b-3e988d8a7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624294113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1624294113
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3902168892
Short name T698
Test name
Test status
Simulation time 4639035104 ps
CPU time 12.24 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:24 PM PDT 24
Peak memory 222060 kb
Host smart-7d376d20-098a-4646-8bb3-77cc16068726
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3902168892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3902168892
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1759724400
Short name T791
Test name
Test status
Simulation time 140699017429 ps
CPU time 297.37 seconds
Started Jul 10 05:43:17 PM PDT 24
Finished Jul 10 05:48:15 PM PDT 24
Peak memory 258564 kb
Host smart-36959fc1-16ae-4b12-b570-f101e774f53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759724400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1759724400
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.770829950
Short name T903
Test name
Test status
Simulation time 4362150395 ps
CPU time 23.06 seconds
Started Jul 10 05:43:09 PM PDT 24
Finished Jul 10 05:43:33 PM PDT 24
Peak memory 217436 kb
Host smart-c92f56ae-d5be-4ffb-9773-a44dbf275d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770829950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.770829950
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1624117627
Short name T448
Test name
Test status
Simulation time 3229681410 ps
CPU time 12.65 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:25 PM PDT 24
Peak memory 217488 kb
Host smart-4dd46a0e-42f5-4862-8e6d-575213b8f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624117627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1624117627
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3854537487
Short name T860
Test name
Test status
Simulation time 33728052 ps
CPU time 0.69 seconds
Started Jul 10 05:43:12 PM PDT 24
Finished Jul 10 05:43:14 PM PDT 24
Peak memory 206544 kb
Host smart-f2f6afc4-7914-43bf-9399-ea8bbe9177a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854537487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3854537487
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1039552643
Short name T693
Test name
Test status
Simulation time 149756984 ps
CPU time 0.82 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 206948 kb
Host smart-8ba494c6-74e6-4fe1-a166-9d4f12e1ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039552643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1039552643
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2203854066
Short name T567
Test name
Test status
Simulation time 105382702 ps
CPU time 3.58 seconds
Started Jul 10 05:43:11 PM PDT 24
Finished Jul 10 05:43:16 PM PDT 24
Peak memory 233708 kb
Host smart-790c8c9b-fc8e-4559-b587-fa57faefe44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203854066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2203854066
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2325820850
Short name T522
Test name
Test status
Simulation time 41475631 ps
CPU time 0.73 seconds
Started Jul 10 05:41:32 PM PDT 24
Finished Jul 10 05:41:35 PM PDT 24
Peak memory 206356 kb
Host smart-6d632c62-e0bb-4d56-8a76-d005a6cbcea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325820850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
325820850
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2429634683
Short name T582
Test name
Test status
Simulation time 29282636 ps
CPU time 2.29 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:41:36 PM PDT 24
Peak memory 233476 kb
Host smart-e9c82ce8-4d3f-435e-a7c5-892d664336b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429634683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2429634683
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3863195030
Short name T547
Test name
Test status
Simulation time 38276368 ps
CPU time 0.76 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:26 PM PDT 24
Peak memory 207788 kb
Host smart-22986cd0-ee52-4d33-b29f-878505d3782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863195030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3863195030
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1724396398
Short name T588
Test name
Test status
Simulation time 24858442277 ps
CPU time 165.65 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:44:16 PM PDT 24
Peak memory 253536 kb
Host smart-27455a80-a17f-493c-85cf-12a849ac30b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724396398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1724396398
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3775974594
Short name T429
Test name
Test status
Simulation time 18292552910 ps
CPU time 158.91 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:44:11 PM PDT 24
Peak memory 258436 kb
Host smart-17815260-09c3-491c-b93e-2e6915578ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775974594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3775974594
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1182955498
Short name T286
Test name
Test status
Simulation time 8718250983 ps
CPU time 114.94 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 269220 kb
Host smart-600a13e9-2b4c-4eca-bbec-fa441831cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182955498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1182955498
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2392623270
Short name T290
Test name
Test status
Simulation time 441354162 ps
CPU time 13.35 seconds
Started Jul 10 05:41:32 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 233796 kb
Host smart-fb305ae7-bf6d-4964-ae01-139bc6b4f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392623270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2392623270
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3550147353
Short name T94
Test name
Test status
Simulation time 15858123046 ps
CPU time 118.91 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:43:29 PM PDT 24
Peak memory 250272 kb
Host smart-17fd097e-e963-4564-a129-bd06b73d124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550147353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3550147353
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2263337829
Short name T365
Test name
Test status
Simulation time 4189393627 ps
CPU time 19.84 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:52 PM PDT 24
Peak memory 228964 kb
Host smart-4f4ebf95-d17b-4969-b498-f19f0885f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263337829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2263337829
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2755908174
Short name T856
Test name
Test status
Simulation time 65962081865 ps
CPU time 101.02 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:43:14 PM PDT 24
Peak memory 241960 kb
Host smart-1ce767e3-1ccc-4e37-85cf-2c807a554e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755908174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2755908174
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.438306177
Short name T656
Test name
Test status
Simulation time 27322256 ps
CPU time 1.09 seconds
Started Jul 10 05:41:24 PM PDT 24
Finished Jul 10 05:41:27 PM PDT 24
Peak memory 218872 kb
Host smart-00cf05de-a7c2-4e8f-9c4d-85068e093649
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438306177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.438306177
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4206659694
Short name T435
Test name
Test status
Simulation time 5071090462 ps
CPU time 11.13 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:42 PM PDT 24
Peak memory 233820 kb
Host smart-55117fa5-d004-4481-81ca-f6ccd4542296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206659694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4206659694
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2039346091
Short name T229
Test name
Test status
Simulation time 1537054487 ps
CPU time 6.9 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:31 PM PDT 24
Peak memory 233788 kb
Host smart-71a88102-50dd-4d21-9693-6c2f6f658028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039346091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2039346091
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4182213409
Short name T989
Test name
Test status
Simulation time 1434232690 ps
CPU time 4.17 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:36 PM PDT 24
Peak memory 223492 kb
Host smart-7e767576-cf1a-44a9-8871-76e789b121d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4182213409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4182213409
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2362070316
Short name T77
Test name
Test status
Simulation time 99930682 ps
CPU time 1.19 seconds
Started Jul 10 05:41:32 PM PDT 24
Finished Jul 10 05:41:35 PM PDT 24
Peak memory 236380 kb
Host smart-69d9e207-3443-41a7-9966-c4a3fe417f7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362070316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2362070316
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3281204081
Short name T784
Test name
Test status
Simulation time 9934856897 ps
CPU time 60.07 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:42:34 PM PDT 24
Peak memory 250780 kb
Host smart-1d042bd2-1365-47ab-9f86-7881ea221858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281204081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3281204081
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3523592768
Short name T32
Test name
Test status
Simulation time 1283665140 ps
CPU time 7.8 seconds
Started Jul 10 05:41:23 PM PDT 24
Finished Jul 10 05:41:32 PM PDT 24
Peak memory 217244 kb
Host smart-45433a5d-d2c9-40b5-9c46-f297b7bdeff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523592768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3523592768
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1730200762
Short name T625
Test name
Test status
Simulation time 117824716 ps
CPU time 1.99 seconds
Started Jul 10 05:41:24 PM PDT 24
Finished Jul 10 05:41:28 PM PDT 24
Peak memory 217316 kb
Host smart-2b766af4-b8c0-47fc-8a4e-2a9450ce2fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730200762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1730200762
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.983425424
Short name T457
Test name
Test status
Simulation time 295361932 ps
CPU time 0.93 seconds
Started Jul 10 05:41:22 PM PDT 24
Finished Jul 10 05:41:24 PM PDT 24
Peak memory 206972 kb
Host smart-4aee3d98-3a16-4cdc-a618-c9f8db589957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983425424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.983425424
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3953087713
Short name T226
Test name
Test status
Simulation time 52511205 ps
CPU time 2.98 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:41:36 PM PDT 24
Peak memory 233672 kb
Host smart-52d86b2a-0097-46f4-a30d-7d38d2c77ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953087713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3953087713
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.12645410
Short name T892
Test name
Test status
Simulation time 11106219 ps
CPU time 0.71 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 205800 kb
Host smart-67d549fa-ad9d-4e2d-82c0-01543cbd7953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12645410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.12645410
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.283438459
Short name T532
Test name
Test status
Simulation time 1001254680 ps
CPU time 6.68 seconds
Started Jul 10 05:43:20 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 225772 kb
Host smart-7acca055-b756-4b27-81a1-8fd81a686500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283438459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.283438459
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1020427390
Short name T331
Test name
Test status
Simulation time 28702066 ps
CPU time 0.8 seconds
Started Jul 10 05:43:17 PM PDT 24
Finished Jul 10 05:43:20 PM PDT 24
Peak memory 207484 kb
Host smart-75d0ba32-8d81-4651-832f-87707ed362a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020427390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1020427390
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1087964957
Short name T716
Test name
Test status
Simulation time 32809938335 ps
CPU time 223.31 seconds
Started Jul 10 05:43:24 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 258052 kb
Host smart-42c07dba-c956-4f53-bb5b-66a3efe16dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087964957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1087964957
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1907343804
Short name T933
Test name
Test status
Simulation time 4159478456 ps
CPU time 57.93 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:44:22 PM PDT 24
Peak memory 242208 kb
Host smart-5f4a92cd-c131-4525-b8d8-bd6aa11fdf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907343804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1907343804
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3602734604
Short name T294
Test name
Test status
Simulation time 3382601625 ps
CPU time 7.68 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:32 PM PDT 24
Peak memory 225616 kb
Host smart-2b783263-43af-4521-9a46-0ac7f943dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602734604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3602734604
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2729555869
Short name T172
Test name
Test status
Simulation time 69352591356 ps
CPU time 314.84 seconds
Started Jul 10 05:43:24 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 256120 kb
Host smart-f6967e90-6c43-4cca-8cbb-2ed5bca0ae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729555869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2729555869
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.649235541
Short name T688
Test name
Test status
Simulation time 343755695 ps
CPU time 4.48 seconds
Started Jul 10 05:43:17 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 225776 kb
Host smart-67be3360-15bc-456f-b199-0b9182fac2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649235541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.649235541
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2232314571
Short name T845
Test name
Test status
Simulation time 10423727362 ps
CPU time 31.1 seconds
Started Jul 10 05:43:15 PM PDT 24
Finished Jul 10 05:43:47 PM PDT 24
Peak memory 222868 kb
Host smart-b8cf8b08-2065-4015-aecd-a1a40178144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232314571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2232314571
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2812498704
Short name T358
Test name
Test status
Simulation time 32306984 ps
CPU time 1.97 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:43:19 PM PDT 24
Peak memory 224992 kb
Host smart-05096ae8-e46a-4d5e-bc8b-87e5630b9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812498704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2812498704
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2115009832
Short name T946
Test name
Test status
Simulation time 5375531790 ps
CPU time 9.54 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 225664 kb
Host smart-de62c348-5d65-41fe-a692-884dabc327cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115009832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2115009832
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2715833784
Short name T888
Test name
Test status
Simulation time 73596320 ps
CPU time 3.73 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:28 PM PDT 24
Peak memory 224220 kb
Host smart-cab2726e-9b52-4e12-a4a0-89f8b6997e22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2715833784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2715833784
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2508131183
Short name T201
Test name
Test status
Simulation time 35654674307 ps
CPU time 125.19 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:45:30 PM PDT 24
Peak memory 253640 kb
Host smart-365fbbc1-dc33-4c9f-b368-f8f6c42b4028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508131183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2508131183
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1848981140
Short name T572
Test name
Test status
Simulation time 3454749231 ps
CPU time 10.42 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 217436 kb
Host smart-e197ead0-3978-424f-be02-34c0a09c7020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848981140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1848981140
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2040485973
Short name T27
Test name
Test status
Simulation time 1347409869 ps
CPU time 6.15 seconds
Started Jul 10 05:43:16 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 217308 kb
Host smart-c3c02dff-6254-4fb5-ad31-c2874f12dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040485973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2040485973
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2277769521
Short name T721
Test name
Test status
Simulation time 23182084 ps
CPU time 0.9 seconds
Started Jul 10 05:43:18 PM PDT 24
Finished Jul 10 05:43:20 PM PDT 24
Peak memory 207996 kb
Host smart-237829bd-b00b-40f8-9b5e-e49c99a05e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277769521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2277769521
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2619955394
Short name T402
Test name
Test status
Simulation time 15813763 ps
CPU time 0.72 seconds
Started Jul 10 05:43:18 PM PDT 24
Finished Jul 10 05:43:20 PM PDT 24
Peak memory 206912 kb
Host smart-d02ae4d4-725d-41f4-86bd-02192117fbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619955394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2619955394
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2669892948
Short name T781
Test name
Test status
Simulation time 309893345 ps
CPU time 7.5 seconds
Started Jul 10 05:43:20 PM PDT 24
Finished Jul 10 05:43:28 PM PDT 24
Peak memory 233716 kb
Host smart-a6a9dfcb-24c2-4999-830e-b568f6e32a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669892948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2669892948
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.358816489
Short name T472
Test name
Test status
Simulation time 12375212 ps
CPU time 0.7 seconds
Started Jul 10 05:43:33 PM PDT 24
Finished Jul 10 05:43:35 PM PDT 24
Peak memory 206356 kb
Host smart-da18ccfe-1199-41dc-98b4-adf385d3c78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358816489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.358816489
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.953845415
Short name T807
Test name
Test status
Simulation time 942673463 ps
CPU time 4.9 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:28 PM PDT 24
Peak memory 233752 kb
Host smart-160bceef-4420-4a9a-85c3-9c1be78eccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953845415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.953845415
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.127336364
Short name T321
Test name
Test status
Simulation time 90803990 ps
CPU time 0.78 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:25 PM PDT 24
Peak memory 207456 kb
Host smart-f828b19f-78e0-48c1-82b8-a8e8751bb9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127336364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.127336364
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2047560535
Short name T176
Test name
Test status
Simulation time 24539062951 ps
CPU time 132.71 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:45:45 PM PDT 24
Peak memory 271432 kb
Host smart-1ab1c9ff-0a41-4aff-aaeb-9d1df69547cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047560535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2047560535
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2313896465
Short name T60
Test name
Test status
Simulation time 5634562242 ps
CPU time 113.45 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:45:25 PM PDT 24
Peak memory 256288 kb
Host smart-0323b15c-8146-4871-8d12-8b08cffa4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313896465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2313896465
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3412143423
Short name T85
Test name
Test status
Simulation time 32332590286 ps
CPU time 276.46 seconds
Started Jul 10 05:43:33 PM PDT 24
Finished Jul 10 05:48:10 PM PDT 24
Peak memory 255112 kb
Host smart-eeb93f0b-2f29-4a9d-a815-0be747af0a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412143423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3412143423
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4097089388
Short name T799
Test name
Test status
Simulation time 338253972 ps
CPU time 5.42 seconds
Started Jul 10 05:43:33 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 225564 kb
Host smart-1d876920-9f2b-4619-995b-41c541cdf5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097089388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4097089388
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1675346999
Short name T785
Test name
Test status
Simulation time 11724289568 ps
CPU time 11.77 seconds
Started Jul 10 05:43:24 PM PDT 24
Finished Jul 10 05:43:37 PM PDT 24
Peak memory 225688 kb
Host smart-e6be1589-8db3-4b55-bbba-79bf8429db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675346999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1675346999
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.459980443
Short name T777
Test name
Test status
Simulation time 2485123476 ps
CPU time 8.2 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:33 PM PDT 24
Peak memory 233804 kb
Host smart-ac49927c-c511-4950-81e2-d7a5e73277b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459980443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.459980443
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4080471378
Short name T72
Test name
Test status
Simulation time 4413312047 ps
CPU time 18.52 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:43 PM PDT 24
Peak memory 241912 kb
Host smart-58078615-af27-4f51-b071-268b7f3d6d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080471378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4080471378
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.951405282
Short name T947
Test name
Test status
Simulation time 539338712 ps
CPU time 5.97 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 221032 kb
Host smart-39c40fa1-8288-452b-8e22-5d8fd046eb08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=951405282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.951405282
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1044978248
Short name T283
Test name
Test status
Simulation time 13473037405 ps
CPU time 142.36 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:45:56 PM PDT 24
Peak memory 249636 kb
Host smart-363e29b4-e672-4335-afc6-e176a16d1d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044978248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1044978248
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4102908035
Short name T624
Test name
Test status
Simulation time 33581439 ps
CPU time 0.72 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:24 PM PDT 24
Peak memory 206656 kb
Host smart-fb5037c3-dea8-4f05-8c48-d4936a59b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102908035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4102908035
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1817705722
Short name T782
Test name
Test status
Simulation time 6762590078 ps
CPU time 9.53 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:34 PM PDT 24
Peak memory 217508 kb
Host smart-1e29c69b-58c1-4bcd-8c80-01d1a9075009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817705722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1817705722
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1006696296
Short name T471
Test name
Test status
Simulation time 123058958 ps
CPU time 1.15 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:23 PM PDT 24
Peak memory 207948 kb
Host smart-b9cc9663-ab98-4e25-8756-72d7b26c29ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006696296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1006696296
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4220662657
Short name T983
Test name
Test status
Simulation time 31823906 ps
CPU time 0.83 seconds
Started Jul 10 05:43:23 PM PDT 24
Finished Jul 10 05:43:25 PM PDT 24
Peak memory 206948 kb
Host smart-23177968-4f6e-4745-8844-7e49016b28e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220662657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4220662657
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.439758083
Short name T840
Test name
Test status
Simulation time 28062789969 ps
CPU time 21.9 seconds
Started Jul 10 05:43:22 PM PDT 24
Finished Jul 10 05:43:46 PM PDT 24
Peak memory 234812 kb
Host smart-01973977-d0e2-410e-a3d4-8978c1f3d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439758083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.439758083
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3070653863
Short name T73
Test name
Test status
Simulation time 45655836 ps
CPU time 0.73 seconds
Started Jul 10 05:43:37 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 206736 kb
Host smart-57b5c199-1058-40a3-9368-8a897071c8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070653863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3070653863
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3023484392
Short name T396
Test name
Test status
Simulation time 2231333007 ps
CPU time 5.48 seconds
Started Jul 10 05:43:36 PM PDT 24
Finished Jul 10 05:43:43 PM PDT 24
Peak memory 225636 kb
Host smart-d03a48df-9d52-45a6-befd-ef18335d9490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023484392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3023484392
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1473478592
Short name T881
Test name
Test status
Simulation time 53033595 ps
CPU time 0.86 seconds
Started Jul 10 05:43:33 PM PDT 24
Finished Jul 10 05:43:34 PM PDT 24
Peak memory 207496 kb
Host smart-24b26c42-1687-412b-99fd-229912a169eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473478592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1473478592
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.288565272
Short name T181
Test name
Test status
Simulation time 5406387430 ps
CPU time 62.47 seconds
Started Jul 10 05:43:37 PM PDT 24
Finished Jul 10 05:44:41 PM PDT 24
Peak memory 250404 kb
Host smart-2678d019-fd32-48d3-ac01-cc02ce246720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288565272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.288565272
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1794681860
Short name T128
Test name
Test status
Simulation time 21274854885 ps
CPU time 98.62 seconds
Started Jul 10 05:43:36 PM PDT 24
Finished Jul 10 05:45:16 PM PDT 24
Peak memory 266816 kb
Host smart-2fd5c996-611d-4e5e-b468-32d6e8322be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794681860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1794681860
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4113831388
Short name T617
Test name
Test status
Simulation time 81414968345 ps
CPU time 215.62 seconds
Started Jul 10 05:43:41 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 258556 kb
Host smart-96b96833-a124-4ad6-bada-968c76306c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113831388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4113831388
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1167910837
Short name T330
Test name
Test status
Simulation time 2203704929 ps
CPU time 16.61 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:43:55 PM PDT 24
Peak memory 235016 kb
Host smart-e265b551-27e9-48ef-a6f4-715540daef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167910837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1167910837
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2899698029
Short name T924
Test name
Test status
Simulation time 30705037130 ps
CPU time 223.74 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:47:22 PM PDT 24
Peak memory 250236 kb
Host smart-14fe4d1e-629e-4d98-978c-f2df7e701319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899698029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2899698029
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.383973523
Short name T356
Test name
Test status
Simulation time 329051908 ps
CPU time 4.46 seconds
Started Jul 10 05:43:42 PM PDT 24
Finished Jul 10 05:43:47 PM PDT 24
Peak memory 225476 kb
Host smart-942f5fdd-7f53-4474-8645-516a03d019b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383973523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.383973523
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.318628346
Short name T634
Test name
Test status
Simulation time 2088755170 ps
CPU time 7.66 seconds
Started Jul 10 05:43:39 PM PDT 24
Finished Jul 10 05:43:47 PM PDT 24
Peak memory 233772 kb
Host smart-5b03832f-6238-4e76-84b4-24ee01578246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318628346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.318628346
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3888446774
Short name T212
Test name
Test status
Simulation time 1727668937 ps
CPU time 4.17 seconds
Started Jul 10 05:43:35 PM PDT 24
Finished Jul 10 05:43:40 PM PDT 24
Peak memory 225520 kb
Host smart-3b6009ac-79a4-411f-9387-60c29f228584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888446774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3888446774
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1902033059
Short name T258
Test name
Test status
Simulation time 7677044742 ps
CPU time 19.84 seconds
Started Jul 10 05:43:31 PM PDT 24
Finished Jul 10 05:43:52 PM PDT 24
Peak memory 233880 kb
Host smart-9bee7ba5-6f54-4877-a179-0c8d394ec775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902033059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1902033059
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.501478711
Short name T390
Test name
Test status
Simulation time 573186936 ps
CPU time 4.06 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:43:43 PM PDT 24
Peak memory 219856 kb
Host smart-f8737b91-b07d-474b-ad75-1c66876bf393
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=501478711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.501478711
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.739119827
Short name T148
Test name
Test status
Simulation time 4633717316 ps
CPU time 62.61 seconds
Started Jul 10 05:43:37 PM PDT 24
Finished Jul 10 05:44:41 PM PDT 24
Peak memory 253860 kb
Host smart-880cd9a9-5bcc-474e-aa97-ae543b4dc863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739119827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.739119827
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2351545416
Short name T739
Test name
Test status
Simulation time 30556846139 ps
CPU time 45.04 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:44:18 PM PDT 24
Peak memory 217708 kb
Host smart-e6e561c6-e671-472f-8f80-07d274334970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351545416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2351545416
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.510214835
Short name T484
Test name
Test status
Simulation time 10013571 ps
CPU time 0.71 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:43:34 PM PDT 24
Peak memory 206584 kb
Host smart-ba5244e3-4418-4b7f-8f3f-19b3871f880f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510214835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.510214835
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1477293345
Short name T462
Test name
Test status
Simulation time 122218475 ps
CPU time 1.23 seconds
Started Jul 10 05:43:32 PM PDT 24
Finished Jul 10 05:43:34 PM PDT 24
Peak memory 208952 kb
Host smart-4e5b19ee-4aef-4701-877b-86d3f9e94a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477293345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1477293345
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.909051240
Short name T446
Test name
Test status
Simulation time 69795920 ps
CPU time 0.79 seconds
Started Jul 10 05:43:33 PM PDT 24
Finished Jul 10 05:43:35 PM PDT 24
Peak memory 206936 kb
Host smart-30145a51-bfdc-4ea3-9df9-36790d243e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909051240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.909051240
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1389422694
Short name T451
Test name
Test status
Simulation time 847476328 ps
CPU time 10.12 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:43:49 PM PDT 24
Peak memory 233824 kb
Host smart-1819a61c-6b56-4409-8b5f-9a0ac3dbc552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389422694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1389422694
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.590083179
Short name T554
Test name
Test status
Simulation time 42694769 ps
CPU time 0.69 seconds
Started Jul 10 05:43:41 PM PDT 24
Finished Jul 10 05:43:42 PM PDT 24
Peak memory 206352 kb
Host smart-44d68ffb-e6e3-4bf4-99b6-96f8ea3641af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590083179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.590083179
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.118590515
Short name T748
Test name
Test status
Simulation time 1589157024 ps
CPU time 2.53 seconds
Started Jul 10 05:43:43 PM PDT 24
Finished Jul 10 05:43:46 PM PDT 24
Peak memory 225536 kb
Host smart-19692eca-a032-4e98-92f8-9a8d5d56e1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118590515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.118590515
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3217046922
Short name T910
Test name
Test status
Simulation time 139441060 ps
CPU time 0.82 seconds
Started Jul 10 05:43:41 PM PDT 24
Finished Jul 10 05:43:42 PM PDT 24
Peak memory 207828 kb
Host smart-c85aea07-5381-49df-8a8a-0d35e8a2d74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217046922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3217046922
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.829135705
Short name T41
Test name
Test status
Simulation time 2463215731 ps
CPU time 26.89 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:44:19 PM PDT 24
Peak memory 242096 kb
Host smart-13a0ac77-c3b3-48b6-af6c-0dd02cafedde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829135705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.829135705
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3409912088
Short name T348
Test name
Test status
Simulation time 24386077288 ps
CPU time 214.18 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:47:26 PM PDT 24
Peak memory 252744 kb
Host smart-c04b5fff-9079-41fc-8f4a-3cdb9d2d3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409912088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3409912088
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4078994525
Short name T440
Test name
Test status
Simulation time 44266888111 ps
CPU time 232.35 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:47:41 PM PDT 24
Peak memory 258604 kb
Host smart-4581ee24-fb4d-4eb3-9dcf-c4964e2de1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078994525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4078994525
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2776206426
Short name T364
Test name
Test status
Simulation time 440087493 ps
CPU time 4.73 seconds
Started Jul 10 05:43:42 PM PDT 24
Finished Jul 10 05:43:48 PM PDT 24
Peak memory 236356 kb
Host smart-c8c3eadb-d487-45cd-9380-f230816b4adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776206426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2776206426
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2683411798
Short name T173
Test name
Test status
Simulation time 25726367882 ps
CPU time 110.98 seconds
Started Jul 10 05:43:47 PM PDT 24
Finished Jul 10 05:45:39 PM PDT 24
Peak memory 253604 kb
Host smart-c5ee98eb-9005-45c6-99ec-3d929fa006d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683411798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2683411798
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2634140896
Short name T178
Test name
Test status
Simulation time 235434202 ps
CPU time 4.42 seconds
Started Jul 10 05:43:43 PM PDT 24
Finished Jul 10 05:43:48 PM PDT 24
Peak memory 233768 kb
Host smart-dcfbd763-f52e-476c-a680-0aba5a35ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634140896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2634140896
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4214627733
Short name T202
Test name
Test status
Simulation time 711598404 ps
CPU time 7.78 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:44:00 PM PDT 24
Peak memory 225504 kb
Host smart-bf6b26ac-2147-4578-90ce-b8ca172d814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214627733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4214627733
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1010602813
Short name T599
Test name
Test status
Simulation time 116320496 ps
CPU time 2.2 seconds
Started Jul 10 05:43:47 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 224864 kb
Host smart-d06ed396-69b9-4cc7-a5cb-de23d739f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010602813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1010602813
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3089635998
Short name T252
Test name
Test status
Simulation time 1094863211 ps
CPU time 8.26 seconds
Started Jul 10 05:43:41 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 233704 kb
Host smart-e0374d47-ce35-4340-8484-a3b2fcad8e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089635998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3089635998
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4122150364
Short name T997
Test name
Test status
Simulation time 307711148 ps
CPU time 3.77 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:43:56 PM PDT 24
Peak memory 223568 kb
Host smart-b55a12fd-47b3-4e7a-9b95-711553999e76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122150364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4122150364
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1875174688
Short name T536
Test name
Test status
Simulation time 47553872151 ps
CPU time 209.59 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:47:22 PM PDT 24
Peak memory 250404 kb
Host smart-571d6048-7571-4ac8-ad3c-fe851df220ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875174688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1875174688
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2498224619
Short name T479
Test name
Test status
Simulation time 638248044 ps
CPU time 5.11 seconds
Started Jul 10 05:43:39 PM PDT 24
Finished Jul 10 05:43:45 PM PDT 24
Peak memory 217312 kb
Host smart-b4949599-31c2-4f66-a0d1-26b43c0f3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498224619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2498224619
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.111883836
Short name T452
Test name
Test status
Simulation time 52591715 ps
CPU time 1.61 seconds
Started Jul 10 05:43:38 PM PDT 24
Finished Jul 10 05:43:40 PM PDT 24
Peak memory 209104 kb
Host smart-4135bd09-408a-4770-8ee3-072ee5e03545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111883836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.111883836
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2209741963
Short name T628
Test name
Test status
Simulation time 179603820 ps
CPU time 0.83 seconds
Started Jul 10 05:43:37 PM PDT 24
Finished Jul 10 05:43:39 PM PDT 24
Peak memory 206948 kb
Host smart-e88c311d-5df2-466c-b2a4-5dad6d88bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209741963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2209741963
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1666202548
Short name T345
Test name
Test status
Simulation time 13245965448 ps
CPU time 22.87 seconds
Started Jul 10 05:43:43 PM PDT 24
Finished Jul 10 05:44:07 PM PDT 24
Peak memory 225660 kb
Host smart-504ad438-7a7e-4068-b365-f2a008aebbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666202548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1666202548
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1481962302
Short name T744
Test name
Test status
Simulation time 47637379 ps
CPU time 0.73 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 206696 kb
Host smart-079b7b64-5d31-4e17-9832-2b2bcb75944a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481962302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1481962302
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1368665984
Short name T805
Test name
Test status
Simulation time 406761461 ps
CPU time 3.56 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:54 PM PDT 24
Peak memory 233680 kb
Host smart-5ea7517e-7813-476a-b9ab-0fbdbca23547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368665984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1368665984
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3617390080
Short name T393
Test name
Test status
Simulation time 63492615 ps
CPU time 0.84 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 207496 kb
Host smart-9d6a2d1d-e459-45c8-9fe6-54c736d3cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617390080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3617390080
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3412151933
Short name T647
Test name
Test status
Simulation time 158590657884 ps
CPU time 257.65 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:48:07 PM PDT 24
Peak memory 254284 kb
Host smart-66ce0c14-35ee-45e7-912a-183389aa2981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412151933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3412151933
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3529099382
Short name T679
Test name
Test status
Simulation time 57945290332 ps
CPU time 123.72 seconds
Started Jul 10 05:43:49 PM PDT 24
Finished Jul 10 05:45:54 PM PDT 24
Peak memory 250448 kb
Host smart-288dd5c3-1698-4449-8aaf-dc9c2b0575c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529099382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3529099382
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3150244468
Short name T985
Test name
Test status
Simulation time 5504185329 ps
CPU time 47.39 seconds
Started Jul 10 05:43:49 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 236920 kb
Host smart-d7a58ae4-d23e-4800-8bd5-4be16222dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150244468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3150244468
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2992027276
Short name T977
Test name
Test status
Simulation time 104305694 ps
CPU time 4.64 seconds
Started Jul 10 05:43:50 PM PDT 24
Finished Jul 10 05:43:56 PM PDT 24
Peak memory 233820 kb
Host smart-4e45cf4a-28de-408b-b857-7fb4d3e244dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992027276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2992027276
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2784530970
Short name T959
Test name
Test status
Simulation time 32971807878 ps
CPU time 47.07 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:44:36 PM PDT 24
Peak memory 250212 kb
Host smart-6d02c7b0-1916-433b-927d-ec55360a4182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784530970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2784530970
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1525425238
Short name T824
Test name
Test status
Simulation time 2594326178 ps
CPU time 24.09 seconds
Started Jul 10 05:43:41 PM PDT 24
Finished Jul 10 05:44:07 PM PDT 24
Peak memory 225644 kb
Host smart-000f6672-d3d9-4ffb-8355-85c0e18098e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525425238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1525425238
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.658816448
Short name T200
Test name
Test status
Simulation time 20237897155 ps
CPU time 45.95 seconds
Started Jul 10 05:43:44 PM PDT 24
Finished Jul 10 05:44:31 PM PDT 24
Peak memory 233892 kb
Host smart-7f0d59b8-293c-4c66-b1d8-9b4d470d65fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658816448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.658816448
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1356392135
Short name T776
Test name
Test status
Simulation time 333860515 ps
CPU time 7.38 seconds
Started Jul 10 05:43:45 PM PDT 24
Finished Jul 10 05:43:53 PM PDT 24
Peak memory 241592 kb
Host smart-d6c5291e-b88b-4612-98c6-8b5bc14fa539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356392135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1356392135
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2496798982
Short name T762
Test name
Test status
Simulation time 54149782 ps
CPU time 2.18 seconds
Started Jul 10 05:43:43 PM PDT 24
Finished Jul 10 05:43:46 PM PDT 24
Peak memory 224792 kb
Host smart-949815b5-7676-45f1-b53d-25a9786b3a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496798982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2496798982
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1470489646
Short name T771
Test name
Test status
Simulation time 734006422 ps
CPU time 4.72 seconds
Started Jul 10 05:43:51 PM PDT 24
Finished Jul 10 05:43:58 PM PDT 24
Peak memory 224144 kb
Host smart-767bfdef-c54c-45ed-953d-a5bb34229c11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470489646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1470489646
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1712298734
Short name T13
Test name
Test status
Simulation time 177739002 ps
CPU time 1.05 seconds
Started Jul 10 05:43:50 PM PDT 24
Finished Jul 10 05:43:52 PM PDT 24
Peak memory 208100 kb
Host smart-700e2c33-20c3-40eb-92e7-7c16819b7dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712298734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1712298734
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2105094479
Short name T677
Test name
Test status
Simulation time 2725745138 ps
CPU time 7.42 seconds
Started Jul 10 05:43:42 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 217400 kb
Host smart-f1a9ddc1-4c09-4656-9f36-332078ab29ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105094479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2105094479
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1756653397
Short name T334
Test name
Test status
Simulation time 913580196 ps
CPU time 1.42 seconds
Started Jul 10 05:43:44 PM PDT 24
Finished Jul 10 05:43:46 PM PDT 24
Peak memory 208904 kb
Host smart-d9ff7cb6-bd7e-4427-9487-0cc049e3ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756653397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1756653397
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2245546433
Short name T537
Test name
Test status
Simulation time 101300209 ps
CPU time 2.35 seconds
Started Jul 10 05:43:43 PM PDT 24
Finished Jul 10 05:43:46 PM PDT 24
Peak memory 217384 kb
Host smart-c59da9dd-4cd9-4873-90a0-9348e51c8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245546433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2245546433
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2478601742
Short name T26
Test name
Test status
Simulation time 14895251 ps
CPU time 0.76 seconds
Started Jul 10 05:43:42 PM PDT 24
Finished Jul 10 05:43:44 PM PDT 24
Peak memory 206956 kb
Host smart-02368c37-581a-4579-98f8-aac176970d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478601742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2478601742
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3229279659
Short name T758
Test name
Test status
Simulation time 373597492 ps
CPU time 4.78 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:53 PM PDT 24
Peak memory 233700 kb
Host smart-e9cebeb6-d443-498a-b559-7e02b26b9f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229279659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3229279659
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3522565246
Short name T74
Test name
Test status
Simulation time 20944364 ps
CPU time 0.74 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:43:56 PM PDT 24
Peak memory 206368 kb
Host smart-f055fdc2-b1f0-42d4-a7d0-d887654c98c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522565246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3522565246
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2286016326
Short name T699
Test name
Test status
Simulation time 1508836435 ps
CPU time 7.72 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:04 PM PDT 24
Peak memory 233820 kb
Host smart-b82881b5-30d3-4ade-a0ec-46fc3824c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286016326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2286016326
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3637224793
Short name T918
Test name
Test status
Simulation time 16633146 ps
CPU time 0.8 seconds
Started Jul 10 05:43:50 PM PDT 24
Finished Jul 10 05:43:52 PM PDT 24
Peak memory 207836 kb
Host smart-b0482fa3-510e-4d24-9a2e-8dc751016f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637224793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3637224793
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.20368037
Short name T385
Test name
Test status
Simulation time 2869986028 ps
CPU time 38.34 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:35 PM PDT 24
Peak memory 250264 kb
Host smart-e3601580-fae2-4054-89ba-1d966d1b7ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20368037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.20368037
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1044086046
Short name T61
Test name
Test status
Simulation time 13176214879 ps
CPU time 143.08 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:46:20 PM PDT 24
Peak memory 258588 kb
Host smart-56ef214d-b573-4e9e-a11b-e69fb744d53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044086046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1044086046
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1972554047
Short name T675
Test name
Test status
Simulation time 8081238914 ps
CPU time 29.06 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:44:24 PM PDT 24
Peak memory 233888 kb
Host smart-25ce53d9-c475-4b55-98d6-541560322807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972554047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1972554047
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1343746042
Short name T577
Test name
Test status
Simulation time 135738657199 ps
CPU time 108.06 seconds
Started Jul 10 05:43:58 PM PDT 24
Finished Jul 10 05:45:47 PM PDT 24
Peak memory 233828 kb
Host smart-82d7a1fb-503a-48c1-8c75-374af27e6e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343746042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1343746042
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.458828163
Short name T633
Test name
Test status
Simulation time 239319579 ps
CPU time 3.84 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:54 PM PDT 24
Peak memory 233636 kb
Host smart-493a1ada-5a94-4c2e-b981-d42b49a8b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458828163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.458828163
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3860876229
Short name T769
Test name
Test status
Simulation time 3630043070 ps
CPU time 39.49 seconds
Started Jul 10 05:43:50 PM PDT 24
Finished Jul 10 05:44:31 PM PDT 24
Peak memory 233780 kb
Host smart-22473832-0402-478e-94fc-1a9a6cb4c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860876229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3860876229
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2954722839
Short name T391
Test name
Test status
Simulation time 33723142 ps
CPU time 2.4 seconds
Started Jul 10 05:43:49 PM PDT 24
Finished Jul 10 05:43:53 PM PDT 24
Peak memory 233500 kb
Host smart-7edac525-a374-42d0-92c0-2376864208ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954722839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2954722839
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.609372635
Short name T180
Test name
Test status
Simulation time 13111362664 ps
CPU time 30.51 seconds
Started Jul 10 05:43:50 PM PDT 24
Finished Jul 10 05:44:22 PM PDT 24
Peak memory 234876 kb
Host smart-db13febe-9481-41ae-ac31-6740a66bb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609372635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.609372635
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2435769341
Short name T135
Test name
Test status
Simulation time 1526401227 ps
CPU time 7.86 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:44:03 PM PDT 24
Peak memory 221616 kb
Host smart-f82605fe-622f-4dc9-90e3-4fa3a4c2545d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435769341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2435769341
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2521522591
Short name T278
Test name
Test status
Simulation time 500725039194 ps
CPU time 350.6 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 266100 kb
Host smart-4f9ebdd2-62c4-4ae0-862a-07cb196fc375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521522591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2521522591
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.551717749
Short name T378
Test name
Test status
Simulation time 64017911 ps
CPU time 0.74 seconds
Started Jul 10 05:43:49 PM PDT 24
Finished Jul 10 05:43:51 PM PDT 24
Peak memory 206624 kb
Host smart-a7db165e-0362-407f-9a1d-4554c8f7e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551717749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.551717749
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.994934206
Short name T411
Test name
Test status
Simulation time 398006882 ps
CPU time 1.41 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:50 PM PDT 24
Peak memory 208944 kb
Host smart-d9198214-2d00-43a8-9487-1014f19294b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994934206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.994934206
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.612307108
Short name T954
Test name
Test status
Simulation time 443699471 ps
CPU time 3.81 seconds
Started Jul 10 05:43:48 PM PDT 24
Finished Jul 10 05:43:53 PM PDT 24
Peak memory 217356 kb
Host smart-fa12ea94-edd2-4121-b0e1-1becabcca2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612307108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.612307108
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2448957493
Short name T678
Test name
Test status
Simulation time 85282585 ps
CPU time 0.83 seconds
Started Jul 10 05:43:49 PM PDT 24
Finished Jul 10 05:43:52 PM PDT 24
Peak memory 206948 kb
Host smart-156955fa-edf9-47a9-b460-1affbd89299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448957493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2448957493
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.859646907
Short name T489
Test name
Test status
Simulation time 5030863278 ps
CPU time 19.03 seconds
Started Jul 10 05:43:58 PM PDT 24
Finished Jul 10 05:44:18 PM PDT 24
Peak memory 233848 kb
Host smart-009ddffa-f1c0-40c0-8810-331d751c3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859646907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.859646907
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3859085651
Short name T897
Test name
Test status
Simulation time 11482550 ps
CPU time 0.72 seconds
Started Jul 10 05:44:05 PM PDT 24
Finished Jul 10 05:44:06 PM PDT 24
Peak memory 206368 kb
Host smart-e9cd6750-d329-45bd-a742-370f6d4fab15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859085651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3859085651
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3685287792
Short name T863
Test name
Test status
Simulation time 120303194 ps
CPU time 2.54 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 233496 kb
Host smart-ae74e42a-2c40-4c2b-b327-28fa0f0fca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685287792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3685287792
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2783869256
Short name T342
Test name
Test status
Simulation time 40535567 ps
CPU time 0.78 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 207812 kb
Host smart-1864b1bc-a7ee-4911-86f0-381441aad680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783869256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2783869256
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1011190734
Short name T559
Test name
Test status
Simulation time 41148171193 ps
CPU time 282.15 seconds
Started Jul 10 05:43:53 PM PDT 24
Finished Jul 10 05:48:36 PM PDT 24
Peak memory 250280 kb
Host smart-baa59cd4-f13b-4626-9641-8b1e1a10d029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011190734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1011190734
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3910243627
Short name T424
Test name
Test status
Simulation time 1267488419 ps
CPU time 20.68 seconds
Started Jul 10 05:43:56 PM PDT 24
Finished Jul 10 05:44:18 PM PDT 24
Peak memory 238944 kb
Host smart-8a7c51d4-9740-4992-9c34-47b06ec7b3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910243627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3910243627
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1305154501
Short name T474
Test name
Test status
Simulation time 111525563716 ps
CPU time 260.39 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:48:17 PM PDT 24
Peak memory 250604 kb
Host smart-7d1f23d9-dd0a-4d61-878d-ee3bc3cf0e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305154501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1305154501
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3415934645
Short name T521
Test name
Test status
Simulation time 605103279 ps
CPU time 3.66 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:00 PM PDT 24
Peak memory 233796 kb
Host smart-f98fb7fe-d005-4361-94d2-de7124e12358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415934645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3415934645
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2542609204
Short name T809
Test name
Test status
Simulation time 61771458242 ps
CPU time 202.62 seconds
Started Jul 10 05:43:53 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 268084 kb
Host smart-c881e20c-27a3-429a-84e1-2d1c2f2b1621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542609204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2542609204
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2266391974
Short name T516
Test name
Test status
Simulation time 1198006851 ps
CPU time 11.78 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:44:07 PM PDT 24
Peak memory 225524 kb
Host smart-8a4b9189-55f2-4cd0-a686-ceb8bbd40731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266391974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2266391974
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2360031170
Short name T884
Test name
Test status
Simulation time 1928069720 ps
CPU time 29.45 seconds
Started Jul 10 05:43:57 PM PDT 24
Finished Jul 10 05:44:28 PM PDT 24
Peak memory 220940 kb
Host smart-b590246c-c70c-454b-a435-b98ddd707276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360031170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2360031170
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2828774163
Short name T527
Test name
Test status
Simulation time 1133221538 ps
CPU time 2.85 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:00 PM PDT 24
Peak memory 225520 kb
Host smart-22c00d15-7fd2-44d9-9e7d-5e7e1edf45ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828774163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2828774163
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1624489078
Short name T564
Test name
Test status
Simulation time 9736507759 ps
CPU time 15.46 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:12 PM PDT 24
Peak memory 225728 kb
Host smart-3bc7ec94-21d3-4170-9815-b456990fd60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624489078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1624489078
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2760753309
Short name T591
Test name
Test status
Simulation time 2001034275 ps
CPU time 5.27 seconds
Started Jul 10 05:43:55 PM PDT 24
Finished Jul 10 05:44:01 PM PDT 24
Peak memory 222548 kb
Host smart-6b3d2fec-e4bf-47a9-b11a-02e154af0541
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760753309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2760753309
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2583670259
Short name T926
Test name
Test status
Simulation time 3194447040 ps
CPU time 44.32 seconds
Started Jul 10 05:44:00 PM PDT 24
Finished Jul 10 05:44:45 PM PDT 24
Peak memory 240796 kb
Host smart-e151e403-ef77-4876-9039-0049812ccbc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583670259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2583670259
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3872249119
Short name T303
Test name
Test status
Simulation time 3280632673 ps
CPU time 31.93 seconds
Started Jul 10 05:43:56 PM PDT 24
Finished Jul 10 05:44:29 PM PDT 24
Peak memory 217436 kb
Host smart-e27a7e45-eb8a-416d-99fb-beeacb4cf5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872249119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3872249119
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1056010030
Short name T477
Test name
Test status
Simulation time 4791566428 ps
CPU time 16.45 seconds
Started Jul 10 05:43:56 PM PDT 24
Finished Jul 10 05:44:14 PM PDT 24
Peak memory 217440 kb
Host smart-26e73da5-9fd6-46c5-a0c6-721551043b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056010030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1056010030
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.16690606
Short name T580
Test name
Test status
Simulation time 130151621 ps
CPU time 1.87 seconds
Started Jul 10 05:43:54 PM PDT 24
Finished Jul 10 05:43:57 PM PDT 24
Peak memory 217244 kb
Host smart-7d9ca31b-8ec3-449c-9b8e-e0f2ee282ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16690606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.16690606
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3070541592
Short name T882
Test name
Test status
Simulation time 44474362 ps
CPU time 0.81 seconds
Started Jul 10 05:43:56 PM PDT 24
Finished Jul 10 05:43:58 PM PDT 24
Peak memory 206948 kb
Host smart-f97f7303-1697-4c82-87d4-c2e034f33eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070541592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3070541592
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2314476013
Short name T473
Test name
Test status
Simulation time 17986458965 ps
CPU time 18.59 seconds
Started Jul 10 05:43:59 PM PDT 24
Finished Jul 10 05:44:18 PM PDT 24
Peak memory 241276 kb
Host smart-8bb6d205-2594-4962-af11-42a353a8b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314476013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2314476013
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.757695839
Short name T950
Test name
Test status
Simulation time 34918903 ps
CPU time 0.74 seconds
Started Jul 10 05:44:07 PM PDT 24
Finished Jul 10 05:44:08 PM PDT 24
Peak memory 205820 kb
Host smart-7064e457-d758-45a1-a0f5-73770eed506e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757695839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.757695839
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2021788081
Short name T323
Test name
Test status
Simulation time 120426083 ps
CPU time 2.94 seconds
Started Jul 10 05:44:02 PM PDT 24
Finished Jul 10 05:44:06 PM PDT 24
Peak memory 225512 kb
Host smart-344868a8-4d12-4a19-80ec-398bad152d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021788081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2021788081
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4011070903
Short name T915
Test name
Test status
Simulation time 57994931 ps
CPU time 0.82 seconds
Started Jul 10 05:44:02 PM PDT 24
Finished Jul 10 05:44:04 PM PDT 24
Peak memory 207488 kb
Host smart-93b980d3-a93a-4f8e-81d9-e8ebbb6fd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011070903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4011070903
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3365060430
Short name T84
Test name
Test status
Simulation time 13024688162 ps
CPU time 121.43 seconds
Started Jul 10 05:44:01 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 250220 kb
Host smart-eb810ebd-b1e5-427a-ad01-f15e86bb698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365060430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3365060430
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.627022977
Short name T302
Test name
Test status
Simulation time 4049902636 ps
CPU time 57.86 seconds
Started Jul 10 05:44:05 PM PDT 24
Finished Jul 10 05:45:04 PM PDT 24
Peak memory 250388 kb
Host smart-b2f20f82-34f9-4a05-a9d1-b81e6519afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627022977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.627022977
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.579498100
Short name T667
Test name
Test status
Simulation time 9382568208 ps
CPU time 73.29 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:45:23 PM PDT 24
Peak memory 258532 kb
Host smart-ddc9a205-b648-4b2a-a31e-20055f7cc680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579498100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.579498100
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3846942226
Short name T45
Test name
Test status
Simulation time 1474411776 ps
CPU time 21.55 seconds
Started Jul 10 05:44:06 PM PDT 24
Finished Jul 10 05:44:28 PM PDT 24
Peak memory 235712 kb
Host smart-48da3bf5-ec5e-44aa-8302-0d7ac20b1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846942226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3846942226
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4011694493
Short name T880
Test name
Test status
Simulation time 35921586752 ps
CPU time 127.89 seconds
Started Jul 10 05:44:01 PM PDT 24
Finished Jul 10 05:46:10 PM PDT 24
Peak memory 253908 kb
Host smart-62f3f6cc-95ca-42e8-a875-f76ac2009297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011694493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4011694493
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3048859072
Short name T827
Test name
Test status
Simulation time 618311535 ps
CPU time 2.91 seconds
Started Jul 10 05:44:04 PM PDT 24
Finished Jul 10 05:44:08 PM PDT 24
Peak memory 225588 kb
Host smart-a60aa2fe-7e82-48b1-99ad-9387d897f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048859072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3048859072
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2107516576
Short name T578
Test name
Test status
Simulation time 494226214 ps
CPU time 6.75 seconds
Started Jul 10 05:44:06 PM PDT 24
Finished Jul 10 05:44:14 PM PDT 24
Peak memory 233724 kb
Host smart-6b694535-4cfb-44fd-bc2a-5b895b54e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107516576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2107516576
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4106008227
Short name T281
Test name
Test status
Simulation time 1143714527 ps
CPU time 4.91 seconds
Started Jul 10 05:44:03 PM PDT 24
Finished Jul 10 05:44:09 PM PDT 24
Peak memory 225492 kb
Host smart-7464bf9d-0471-4c89-8a31-a9bff654e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106008227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4106008227
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2882518794
Short name T783
Test name
Test status
Simulation time 19594038179 ps
CPU time 16.64 seconds
Started Jul 10 05:43:59 PM PDT 24
Finished Jul 10 05:44:16 PM PDT 24
Peak memory 238120 kb
Host smart-e99f0892-4bac-4f2c-94db-e1f09ab9d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882518794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2882518794
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1196322922
Short name T430
Test name
Test status
Simulation time 851031864 ps
CPU time 5.97 seconds
Started Jul 10 05:44:06 PM PDT 24
Finished Jul 10 05:44:13 PM PDT 24
Peak memory 220220 kb
Host smart-19162f76-484c-4fec-8a05-5d58cfb597ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1196322922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1196322922
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2575159718
Short name T263
Test name
Test status
Simulation time 133370965945 ps
CPU time 900.25 seconds
Started Jul 10 05:44:06 PM PDT 24
Finished Jul 10 05:59:08 PM PDT 24
Peak memory 283500 kb
Host smart-0a1e8cf3-2915-40bb-be8b-1c2ccc9905b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575159718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2575159718
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2402415397
Short name T669
Test name
Test status
Simulation time 2107116466 ps
CPU time 3.92 seconds
Started Jul 10 05:44:00 PM PDT 24
Finished Jul 10 05:44:05 PM PDT 24
Peak memory 218484 kb
Host smart-067331c5-91de-49f2-b742-af1e55e86a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402415397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2402415397
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1712824547
Short name T717
Test name
Test status
Simulation time 15377110457 ps
CPU time 14.15 seconds
Started Jul 10 05:44:02 PM PDT 24
Finished Jul 10 05:44:17 PM PDT 24
Peak memory 217516 kb
Host smart-98b21066-9413-4cf1-aac1-341118083902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712824547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1712824547
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3606458501
Short name T955
Test name
Test status
Simulation time 94702360 ps
CPU time 0.96 seconds
Started Jul 10 05:44:04 PM PDT 24
Finished Jul 10 05:44:06 PM PDT 24
Peak memory 208192 kb
Host smart-45240599-6698-4d42-838b-1a51692b639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606458501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3606458501
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1802738820
Short name T406
Test name
Test status
Simulation time 28811330 ps
CPU time 0.92 seconds
Started Jul 10 05:44:01 PM PDT 24
Finished Jul 10 05:44:03 PM PDT 24
Peak memory 208180 kb
Host smart-72062dd4-2953-4554-b3e6-9c0401408682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802738820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1802738820
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1151776785
Short name T183
Test name
Test status
Simulation time 2622644672 ps
CPU time 5.26 seconds
Started Jul 10 05:44:01 PM PDT 24
Finished Jul 10 05:44:08 PM PDT 24
Peak memory 233860 kb
Host smart-0d8896a2-4c62-464f-bbe4-120afe48f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151776785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1151776785
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.621765175
Short name T833
Test name
Test status
Simulation time 172613098 ps
CPU time 0.75 seconds
Started Jul 10 05:44:17 PM PDT 24
Finished Jul 10 05:44:19 PM PDT 24
Peak memory 205764 kb
Host smart-3811c1d4-0b75-4b01-807e-f8dc9f93ddea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621765175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.621765175
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.72008213
Short name T808
Test name
Test status
Simulation time 2890398005 ps
CPU time 5.85 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:14 PM PDT 24
Peak memory 225656 kb
Host smart-e6f6c19d-9638-431d-bcaf-753a27bf3f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72008213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.72008213
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.621201424
Short name T737
Test name
Test status
Simulation time 57895852 ps
CPU time 0.78 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:10 PM PDT 24
Peak memory 207828 kb
Host smart-fa2c15b2-1662-4d9b-b348-33bfc793e4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621201424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.621201424
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1178696599
Short name T836
Test name
Test status
Simulation time 4637827563 ps
CPU time 60.99 seconds
Started Jul 10 05:44:14 PM PDT 24
Finished Jul 10 05:45:16 PM PDT 24
Peak memory 250568 kb
Host smart-eaa0d338-49af-42c0-bc68-44f201e3c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178696599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1178696599
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3391090879
Short name T308
Test name
Test status
Simulation time 18179718282 ps
CPU time 146.24 seconds
Started Jul 10 05:44:14 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 258504 kb
Host smart-13d894a7-682e-466c-bc43-3887c71b7418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391090879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3391090879
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2137562694
Short name T842
Test name
Test status
Simulation time 4401899012 ps
CPU time 22.38 seconds
Started Jul 10 05:44:16 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 220476 kb
Host smart-016c842f-a741-44f4-8fe7-15e8488c20cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137562694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2137562694
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4287667974
Short name T822
Test name
Test status
Simulation time 3590496976 ps
CPU time 7.29 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:16 PM PDT 24
Peak memory 225640 kb
Host smart-ec29a8bb-79d3-4b5c-93f6-49f0b8fbe490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287667974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4287667974
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2921293790
Short name T222
Test name
Test status
Simulation time 7270481246 ps
CPU time 69.16 seconds
Started Jul 10 05:44:14 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 256296 kb
Host smart-29da6806-e012-4bec-881b-ba0f66a50c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921293790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2921293790
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3023268732
Short name T594
Test name
Test status
Simulation time 108224786 ps
CPU time 3.69 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:12 PM PDT 24
Peak memory 233764 kb
Host smart-b36214c1-1214-4e6f-86a6-73861914668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023268732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3023268732
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3454642179
Short name T248
Test name
Test status
Simulation time 42954116374 ps
CPU time 79.27 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:45:29 PM PDT 24
Peak memory 250176 kb
Host smart-3bee14f6-2b92-45a5-96bb-680ec79de037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454642179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3454642179
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4009141918
Short name T239
Test name
Test status
Simulation time 879053947 ps
CPU time 6.64 seconds
Started Jul 10 05:44:07 PM PDT 24
Finished Jul 10 05:44:15 PM PDT 24
Peak memory 233724 kb
Host smart-3ae873c0-ec53-41a7-b0c1-620eb0b85e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009141918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4009141918
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2899630794
Short name T467
Test name
Test status
Simulation time 18883442964 ps
CPU time 14.19 seconds
Started Jul 10 05:44:07 PM PDT 24
Finished Jul 10 05:44:22 PM PDT 24
Peak memory 225684 kb
Host smart-9b8da4f9-9188-42aa-adaf-2bc220e40fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899630794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2899630794
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2980784951
Short name T949
Test name
Test status
Simulation time 1690515993 ps
CPU time 19.51 seconds
Started Jul 10 05:44:18 PM PDT 24
Finished Jul 10 05:44:39 PM PDT 24
Peak memory 219832 kb
Host smart-271511f5-5bcf-4c62-a26c-da0fbafa0df3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2980784951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2980784951
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3952117369
Short name T557
Test name
Test status
Simulation time 4640076551 ps
CPU time 27.45 seconds
Started Jul 10 05:44:07 PM PDT 24
Finished Jul 10 05:44:36 PM PDT 24
Peak memory 221148 kb
Host smart-7aa80f37-d421-4a52-8a47-5a607385be31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952117369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3952117369
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3233084715
Short name T29
Test name
Test status
Simulation time 3869034137 ps
CPU time 7.6 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:17 PM PDT 24
Peak memory 217484 kb
Host smart-ea2e45e0-7ee3-4191-a400-5e48cf457614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233084715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3233084715
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2427502567
Short name T673
Test name
Test status
Simulation time 17156094 ps
CPU time 0.78 seconds
Started Jul 10 05:44:10 PM PDT 24
Finished Jul 10 05:44:12 PM PDT 24
Peak memory 206916 kb
Host smart-ffdbb678-2cba-4357-ad16-c70c549de374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427502567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2427502567
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3314639553
Short name T397
Test name
Test status
Simulation time 30678595 ps
CPU time 0.7 seconds
Started Jul 10 05:44:08 PM PDT 24
Finished Jul 10 05:44:10 PM PDT 24
Peak memory 206512 kb
Host smart-62850d54-ff38-4919-b424-9c918dd4b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314639553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3314639553
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3735228550
Short name T786
Test name
Test status
Simulation time 128612322 ps
CPU time 3.11 seconds
Started Jul 10 05:44:11 PM PDT 24
Finished Jul 10 05:44:15 PM PDT 24
Peak memory 233688 kb
Host smart-5bee28e4-90be-4a97-a988-1b0d9e451e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735228550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3735228550
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2249400772
Short name T349
Test name
Test status
Simulation time 15335383 ps
CPU time 0.72 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:22 PM PDT 24
Peak memory 206420 kb
Host smart-2525f500-7630-4252-89c1-694807a294ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249400772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2249400772
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4218448030
Short name T69
Test name
Test status
Simulation time 246081705 ps
CPU time 2.84 seconds
Started Jul 10 05:44:17 PM PDT 24
Finished Jul 10 05:44:21 PM PDT 24
Peak memory 233720 kb
Host smart-1e16e582-b8d0-4814-bbfd-f5b2cc71fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218448030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4218448030
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3858487261
Short name T376
Test name
Test status
Simulation time 17037668 ps
CPU time 0.78 seconds
Started Jul 10 05:44:15 PM PDT 24
Finished Jul 10 05:44:18 PM PDT 24
Peak memory 207476 kb
Host smart-9beb3fb2-c205-4c06-9478-075aa20dfe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858487261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3858487261
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.112226434
Short name T513
Test name
Test status
Simulation time 29443537638 ps
CPU time 192.91 seconds
Started Jul 10 05:44:19 PM PDT 24
Finished Jul 10 05:47:34 PM PDT 24
Peak memory 252528 kb
Host smart-4cd30fbe-5f4e-4269-b321-8fa0409c4796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112226434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.112226434
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2433203950
Short name T261
Test name
Test status
Simulation time 17978800643 ps
CPU time 78.14 seconds
Started Jul 10 05:44:19 PM PDT 24
Finished Jul 10 05:45:38 PM PDT 24
Peak memory 256380 kb
Host smart-4208284c-d590-4781-9828-c3723966df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433203950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2433203950
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1650093450
Short name T767
Test name
Test status
Simulation time 6759240062 ps
CPU time 98.43 seconds
Started Jul 10 05:44:18 PM PDT 24
Finished Jul 10 05:45:57 PM PDT 24
Peak memory 252816 kb
Host smart-49d2df7a-dac5-41ce-8803-6199bdbe5508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650093450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1650093450
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3390790825
Short name T8
Test name
Test status
Simulation time 70816795 ps
CPU time 4.25 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:25 PM PDT 24
Peak memory 225532 kb
Host smart-85cde60b-c2c8-4583-b0ce-5d4be7b6211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390790825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3390790825
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1842060914
Short name T161
Test name
Test status
Simulation time 1779599719 ps
CPU time 29.14 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:50 PM PDT 24
Peak memory 250224 kb
Host smart-becbece6-ef5d-4128-9a1e-8e2555404f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842060914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1842060914
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.237091287
Short name T944
Test name
Test status
Simulation time 954559100 ps
CPU time 13.19 seconds
Started Jul 10 05:44:17 PM PDT 24
Finished Jul 10 05:44:32 PM PDT 24
Peak memory 233660 kb
Host smart-d222789d-d142-49fa-b051-55104c007de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237091287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.237091287
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1981374022
Short name T707
Test name
Test status
Simulation time 9583882783 ps
CPU time 34.02 seconds
Started Jul 10 05:44:16 PM PDT 24
Finished Jul 10 05:44:51 PM PDT 24
Peak memory 225672 kb
Host smart-f74daeef-693d-4b34-816b-90d5090c074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981374022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1981374022
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.152854180
Short name T740
Test name
Test status
Simulation time 1666518157 ps
CPU time 9.98 seconds
Started Jul 10 05:44:16 PM PDT 24
Finished Jul 10 05:44:27 PM PDT 24
Peak memory 239704 kb
Host smart-d2918b0a-2bff-45a2-bfcf-7f8dd6c2625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152854180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.152854180
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1296523610
Short name T736
Test name
Test status
Simulation time 352120267 ps
CPU time 3.16 seconds
Started Jul 10 05:44:15 PM PDT 24
Finished Jul 10 05:44:20 PM PDT 24
Peak memory 225548 kb
Host smart-76287306-6b47-483c-83fd-4c5d61cbb4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296523610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1296523610
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2427814909
Short name T668
Test name
Test status
Simulation time 120672604 ps
CPU time 3.38 seconds
Started Jul 10 05:44:21 PM PDT 24
Finished Jul 10 05:44:26 PM PDT 24
Peak memory 219832 kb
Host smart-cc58cbd9-f08c-4b1b-b352-adb204e1f7a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2427814909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2427814909
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4125506930
Short name T972
Test name
Test status
Simulation time 133703901750 ps
CPU time 301.75 seconds
Started Jul 10 05:44:24 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 269324 kb
Host smart-c44b6807-2502-40af-ace7-3e30675c0936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125506930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4125506930
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3604676584
Short name T733
Test name
Test status
Simulation time 2723278495 ps
CPU time 27.82 seconds
Started Jul 10 05:44:15 PM PDT 24
Finished Jul 10 05:44:44 PM PDT 24
Peak memory 217432 kb
Host smart-bbceb6e9-fe39-4f84-873e-3aae9c6507b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604676584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3604676584
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2227052985
Short name T763
Test name
Test status
Simulation time 2698318917 ps
CPU time 4.64 seconds
Started Jul 10 05:44:14 PM PDT 24
Finished Jul 10 05:44:20 PM PDT 24
Peak memory 217696 kb
Host smart-94a4fd66-955a-46ba-a9fd-609a8c4a6c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227052985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2227052985
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.675369863
Short name T560
Test name
Test status
Simulation time 220572966 ps
CPU time 2.48 seconds
Started Jul 10 05:44:17 PM PDT 24
Finished Jul 10 05:44:21 PM PDT 24
Peak memory 217304 kb
Host smart-1e4ef13e-dbaf-4a50-810f-2200171f18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675369863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.675369863
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1304551110
Short name T315
Test name
Test status
Simulation time 13711182 ps
CPU time 0.72 seconds
Started Jul 10 05:44:15 PM PDT 24
Finished Jul 10 05:44:17 PM PDT 24
Peak memory 206552 kb
Host smart-dcc2f6bd-de1a-4675-a59f-d224ae6fb8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304551110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1304551110
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.263500149
Short name T713
Test name
Test status
Simulation time 23500672541 ps
CPU time 20.09 seconds
Started Jul 10 05:44:16 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 233784 kb
Host smart-0cc5115d-6664-4684-be01-f620abea3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263500149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.263500149
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.677507444
Short name T831
Test name
Test status
Simulation time 13081456 ps
CPU time 0.74 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:33 PM PDT 24
Peak memory 206408 kb
Host smart-488f7df8-c0d1-4841-9704-dc9481847018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677507444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.677507444
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2955529311
Short name T520
Test name
Test status
Simulation time 525993344 ps
CPU time 2.94 seconds
Started Jul 10 05:41:33 PM PDT 24
Finished Jul 10 05:41:37 PM PDT 24
Peak memory 225492 kb
Host smart-6c7d2002-d4ad-4f99-b9c9-a07673ba72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955529311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2955529311
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.469475214
Short name T1012
Test name
Test status
Simulation time 39123659 ps
CPU time 0.75 seconds
Started Jul 10 05:41:33 PM PDT 24
Finished Jul 10 05:41:35 PM PDT 24
Peak memory 206472 kb
Host smart-851c0247-3e72-44f8-846e-ac2d0add0525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469475214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.469475214
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3575546988
Short name T269
Test name
Test status
Simulation time 5940272346 ps
CPU time 77 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:42:50 PM PDT 24
Peak memory 269720 kb
Host smart-22af085f-651e-4120-8a60-2e284bbc7c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575546988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3575546988
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1691550640
Short name T154
Test name
Test status
Simulation time 5590084015 ps
CPU time 95.52 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 253620 kb
Host smart-ddfe34b0-07d9-4362-ba57-f2b74cab3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691550640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1691550640
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3237525787
Short name T187
Test name
Test status
Simulation time 93694973689 ps
CPU time 170.52 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:44:23 PM PDT 24
Peak memory 250268 kb
Host smart-b7971641-75e9-497e-bcca-157ca24b4e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237525787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3237525787
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4045784230
Short name T1008
Test name
Test status
Simulation time 99997736 ps
CPU time 3.24 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:35 PM PDT 24
Peak memory 225560 kb
Host smart-d9a46303-b8a5-4d44-9947-f5e4144dcee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045784230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4045784230
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.797145157
Short name T221
Test name
Test status
Simulation time 2197687707 ps
CPU time 48.9 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:42:22 PM PDT 24
Peak memory 251660 kb
Host smart-aa29b559-686f-4225-be12-3d99144d786e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797145157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
797145157
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.343601703
Short name T93
Test name
Test status
Simulation time 9486385350 ps
CPU time 11.37 seconds
Started Jul 10 05:41:34 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 233912 kb
Host smart-5115c580-e792-4b9f-8935-c57d53761ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343601703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.343601703
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4288729447
Short name T490
Test name
Test status
Simulation time 164915494 ps
CPU time 3.97 seconds
Started Jul 10 05:41:32 PM PDT 24
Finished Jul 10 05:41:38 PM PDT 24
Peak memory 225460 kb
Host smart-315527b3-07dd-446b-8069-6a26237d3d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288729447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4288729447
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.429949374
Short name T834
Test name
Test status
Simulation time 56380174 ps
CPU time 1.11 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:32 PM PDT 24
Peak memory 217636 kb
Host smart-db9d2550-d941-4799-8d94-b95caf1c2416
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429949374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.429949374
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3668556201
Short name T850
Test name
Test status
Simulation time 4148505539 ps
CPU time 13.92 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:46 PM PDT 24
Peak memory 233844 kb
Host smart-da3a6072-1a0e-435f-8f12-d2736486a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668556201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3668556201
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2753818639
Short name T714
Test name
Test status
Simulation time 1672358176 ps
CPU time 5.2 seconds
Started Jul 10 05:41:32 PM PDT 24
Finished Jul 10 05:41:39 PM PDT 24
Peak memory 233692 kb
Host smart-19dad2c2-97aa-4357-9aff-e7176f568b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753818639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2753818639
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2929614938
Short name T548
Test name
Test status
Simulation time 536380335 ps
CPU time 4.49 seconds
Started Jul 10 05:41:33 PM PDT 24
Finished Jul 10 05:41:39 PM PDT 24
Peak memory 222484 kb
Host smart-76be5ab5-84da-4444-af3f-630d245c787b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2929614938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2929614938
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.886696790
Short name T76
Test name
Test status
Simulation time 122907257 ps
CPU time 1.06 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:30 PM PDT 24
Peak memory 236288 kb
Host smart-9925b9b4-3e5b-48bb-9a69-fb14bb999921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886696790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.886696790
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3455990534
Short name T203
Test name
Test status
Simulation time 19151423321 ps
CPU time 107.06 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 265528 kb
Host smart-55fd0474-203a-4254-8403-e6f5f9515b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455990534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3455990534
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1518485808
Short name T413
Test name
Test status
Simulation time 14733660364 ps
CPU time 29.28 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 217480 kb
Host smart-d2086ddb-44d2-43b6-9507-fe5256f774e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518485808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1518485808
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2802036623
Short name T685
Test name
Test status
Simulation time 1372382855 ps
CPU time 5.37 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:38 PM PDT 24
Peak memory 217404 kb
Host smart-ef1757ca-40eb-486d-a587-97424c40aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802036623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2802036623
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2256899442
Short name T30
Test name
Test status
Simulation time 413746611 ps
CPU time 1.81 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:33 PM PDT 24
Peak memory 217316 kb
Host smart-748f40bc-4a09-4354-a392-56b60189d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256899442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2256899442
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.384224075
Short name T381
Test name
Test status
Simulation time 129416113 ps
CPU time 0.96 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:41:34 PM PDT 24
Peak memory 206868 kb
Host smart-e334d500-6e05-4fe8-a8a1-9d8de2e809d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384224075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.384224075
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1360699163
Short name T227
Test name
Test status
Simulation time 410263203 ps
CPU time 2.7 seconds
Started Jul 10 05:41:28 PM PDT 24
Finished Jul 10 05:41:31 PM PDT 24
Peak memory 233748 kb
Host smart-2e382fbe-c852-452e-9c3f-071f1b70a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360699163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1360699163
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1948211304
Short name T928
Test name
Test status
Simulation time 49743661 ps
CPU time 0.71 seconds
Started Jul 10 05:44:26 PM PDT 24
Finished Jul 10 05:44:28 PM PDT 24
Peak memory 206616 kb
Host smart-346d0048-0fe9-4595-8676-466c146ad6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948211304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1948211304
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3569554937
Short name T563
Test name
Test status
Simulation time 814033417 ps
CPU time 3.45 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:32 PM PDT 24
Peak memory 225576 kb
Host smart-99331139-5515-4bbe-bf6a-e562a33b19ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569554937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3569554937
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2747802588
Short name T355
Test name
Test status
Simulation time 24905492 ps
CPU time 0.79 seconds
Started Jul 10 05:44:22 PM PDT 24
Finished Jul 10 05:44:24 PM PDT 24
Peak memory 207496 kb
Host smart-84b4d4df-0508-48c1-a27d-5bec41caac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747802588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2747802588
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.891119968
Short name T480
Test name
Test status
Simulation time 6184998046 ps
CPU time 24.41 seconds
Started Jul 10 05:44:28 PM PDT 24
Finished Jul 10 05:44:54 PM PDT 24
Peak memory 250268 kb
Host smart-82e2371a-76c4-4cd6-9bf9-4092e8cf6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891119968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.891119968
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3395068018
Short name T626
Test name
Test status
Simulation time 20922431768 ps
CPU time 205.16 seconds
Started Jul 10 05:44:26 PM PDT 24
Finished Jul 10 05:47:53 PM PDT 24
Peak memory 251348 kb
Host smart-df683d3d-bf2c-414b-a463-f907c3802c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395068018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3395068018
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3642568253
Short name T47
Test name
Test status
Simulation time 598778679 ps
CPU time 11.51 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 236028 kb
Host smart-c3dbea20-f8f6-4686-b68b-74d64b66fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642568253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3642568253
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2731188343
Short name T274
Test name
Test status
Simulation time 21421920152 ps
CPU time 66.11 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:45:34 PM PDT 24
Peak memory 255792 kb
Host smart-11fed3b0-b354-4a1f-8107-bb1c5a5c0749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731188343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2731188343
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2051062917
Short name T636
Test name
Test status
Simulation time 764786154 ps
CPU time 6.27 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:28 PM PDT 24
Peak memory 225524 kb
Host smart-76811ca7-b6c2-41af-8175-0e62b89c8e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051062917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2051062917
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1663269361
Short name T216
Test name
Test status
Simulation time 2417300438 ps
CPU time 26.78 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:48 PM PDT 24
Peak memory 233868 kb
Host smart-15c866ee-efed-4824-bf90-645e9039da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663269361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1663269361
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1040491956
Short name T586
Test name
Test status
Simulation time 1006678368 ps
CPU time 3.6 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:25 PM PDT 24
Peak memory 233812 kb
Host smart-f893e02c-c77d-45f0-bbaf-2fd4ae8c2966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040491956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1040491956
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4071426976
Short name T225
Test name
Test status
Simulation time 2942901059 ps
CPU time 10.84 seconds
Started Jul 10 05:44:24 PM PDT 24
Finished Jul 10 05:44:35 PM PDT 24
Peak memory 233848 kb
Host smart-4f77eb68-4300-48ea-96ec-63a9c0a51c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071426976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4071426976
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1570626179
Short name T878
Test name
Test status
Simulation time 422896249 ps
CPU time 9.03 seconds
Started Jul 10 05:44:28 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 220400 kb
Host smart-4e923d91-e35c-4183-b91e-c45b9cce0eb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1570626179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1570626179
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2459032492
Short name T661
Test name
Test status
Simulation time 2561430787 ps
CPU time 29.2 seconds
Started Jul 10 05:44:29 PM PDT 24
Finished Jul 10 05:44:59 PM PDT 24
Peak memory 241928 kb
Host smart-0fccff19-0faa-48cc-98eb-e77846a515f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459032492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2459032492
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2898044119
Short name T1002
Test name
Test status
Simulation time 12716698722 ps
CPU time 18.99 seconds
Started Jul 10 05:44:25 PM PDT 24
Finished Jul 10 05:44:44 PM PDT 24
Peak memory 217416 kb
Host smart-2aa9ba6a-52d3-4598-a9dd-6f2079332c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898044119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2898044119
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1445939939
Short name T870
Test name
Test status
Simulation time 40192762 ps
CPU time 0.69 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:22 PM PDT 24
Peak memory 206548 kb
Host smart-0204b8bd-b105-4445-97b6-e33d15bf673c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445939939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1445939939
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3202048841
Short name T57
Test name
Test status
Simulation time 341053669 ps
CPU time 5.51 seconds
Started Jul 10 05:44:20 PM PDT 24
Finished Jul 10 05:44:26 PM PDT 24
Peak memory 217360 kb
Host smart-78907dff-4870-4e09-b5cb-af7361149f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202048841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3202048841
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.906007359
Short name T930
Test name
Test status
Simulation time 15347565 ps
CPU time 0.76 seconds
Started Jul 10 05:44:25 PM PDT 24
Finished Jul 10 05:44:26 PM PDT 24
Peak memory 206764 kb
Host smart-8931b80f-f66b-460b-a98f-eed14c0ef3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906007359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.906007359
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2276875919
Short name T143
Test name
Test status
Simulation time 881162993 ps
CPU time 4.3 seconds
Started Jul 10 05:44:26 PM PDT 24
Finished Jul 10 05:44:32 PM PDT 24
Peak memory 233724 kb
Host smart-8c4d114b-961d-4f07-a97e-51be18b3298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276875919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2276875919
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2222889763
Short name T333
Test name
Test status
Simulation time 38836449 ps
CPU time 0.76 seconds
Started Jul 10 05:44:37 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 205788 kb
Host smart-60016d28-1726-41c9-bd6c-4f7220355c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222889763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2222889763
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3516811230
Short name T235
Test name
Test status
Simulation time 1598605748 ps
CPU time 18.01 seconds
Started Jul 10 05:44:34 PM PDT 24
Finished Jul 10 05:44:53 PM PDT 24
Peak memory 233772 kb
Host smart-55d22597-24f2-4505-9092-5f33fbbaae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516811230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3516811230
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.517042909
Short name T542
Test name
Test status
Simulation time 213032587 ps
CPU time 0.73 seconds
Started Jul 10 05:44:26 PM PDT 24
Finished Jul 10 05:44:28 PM PDT 24
Peak memory 206800 kb
Host smart-6327c474-f172-4c8c-bc33-7b1adad90c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517042909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.517042909
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.137478411
Short name T991
Test name
Test status
Simulation time 10521532349 ps
CPU time 43.36 seconds
Started Jul 10 05:44:37 PM PDT 24
Finished Jul 10 05:45:21 PM PDT 24
Peak memory 241968 kb
Host smart-54e3d19c-298c-48ce-9606-3ca70dfd8300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137478411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.137478411
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2765102528
Short name T980
Test name
Test status
Simulation time 14215785351 ps
CPU time 86.76 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 257900 kb
Host smart-c757854c-80d4-4d55-ad92-08c43ad53785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765102528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2765102528
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2150680017
Short name T277
Test name
Test status
Simulation time 250102011913 ps
CPU time 166.67 seconds
Started Jul 10 05:44:36 PM PDT 24
Finished Jul 10 05:47:23 PM PDT 24
Peak memory 265112 kb
Host smart-f03cfbdf-a658-4fcb-a91b-d14076d5f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150680017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2150680017
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1762465593
Short name T813
Test name
Test status
Simulation time 547795824 ps
CPU time 3.92 seconds
Started Jul 10 05:44:36 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 225564 kb
Host smart-fbb0b03a-01a0-4baf-8c59-137cafba6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762465593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1762465593
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1028220557
Short name T224
Test name
Test status
Simulation time 2759848600 ps
CPU time 9.19 seconds
Started Jul 10 05:44:28 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 225644 kb
Host smart-50b8abfd-a33e-43ed-bb24-31486087e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028220557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1028220557
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3278562533
Short name T710
Test name
Test status
Simulation time 359965171 ps
CPU time 2.54 seconds
Started Jul 10 05:44:28 PM PDT 24
Finished Jul 10 05:44:31 PM PDT 24
Peak memory 227828 kb
Host smart-7a52deb0-0820-4342-ad52-213ef10780cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278562533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3278562533
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3281903740
Short name T245
Test name
Test status
Simulation time 6090237143 ps
CPU time 10.34 seconds
Started Jul 10 05:44:28 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 225712 kb
Host smart-c7da0d96-505a-4ef5-ab43-1dac93d140fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281903740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3281903740
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3739122764
Short name T249
Test name
Test status
Simulation time 4697598462 ps
CPU time 8.65 seconds
Started Jul 10 05:44:26 PM PDT 24
Finished Jul 10 05:44:35 PM PDT 24
Peak memory 225660 kb
Host smart-c3829563-792f-457a-af8e-dc917e4b59e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739122764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3739122764
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.922416248
Short name T466
Test name
Test status
Simulation time 343338576 ps
CPU time 3.7 seconds
Started Jul 10 05:44:33 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 224132 kb
Host smart-b9b0e3fc-fc1b-4155-895d-af24db5b5f9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=922416248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.922416248
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1637812954
Short name T929
Test name
Test status
Simulation time 16660553394 ps
CPU time 335.56 seconds
Started Jul 10 05:44:34 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 287172 kb
Host smart-b63cf9fc-e64f-4bdb-bc32-95de90ec803a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637812954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1637812954
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.87438804
Short name T493
Test name
Test status
Simulation time 2321154359 ps
CPU time 29.57 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:58 PM PDT 24
Peak memory 217348 kb
Host smart-4dbffe4e-6d49-4278-8119-dbdf07641c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87438804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.87438804
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1580205432
Short name T501
Test name
Test status
Simulation time 1777347499 ps
CPU time 4.47 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:33 PM PDT 24
Peak memory 217316 kb
Host smart-a3d053fd-b853-47cb-917f-ceae99248e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580205432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1580205432
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4183645565
Short name T725
Test name
Test status
Simulation time 14701704 ps
CPU time 0.95 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:29 PM PDT 24
Peak memory 207984 kb
Host smart-bf40dd6d-2d7b-468d-82e9-2a5b4f12c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183645565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4183645565
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.9931644
Short name T664
Test name
Test status
Simulation time 29580719 ps
CPU time 0.71 seconds
Started Jul 10 05:44:27 PM PDT 24
Finished Jul 10 05:44:29 PM PDT 24
Peak memory 206532 kb
Host smart-cc8fb774-15c1-4933-8f20-092e52c69b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9931644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.9931644
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1148019511
Short name T964
Test name
Test status
Simulation time 598678690 ps
CPU time 2.17 seconds
Started Jul 10 05:44:29 PM PDT 24
Finished Jul 10 05:44:32 PM PDT 24
Peak memory 224216 kb
Host smart-7013ea2a-8e19-4290-b558-653615e28885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148019511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1148019511
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.857642190
Short name T727
Test name
Test status
Simulation time 13252239 ps
CPU time 0.71 seconds
Started Jul 10 05:44:40 PM PDT 24
Finished Jul 10 05:44:42 PM PDT 24
Peak memory 205788 kb
Host smart-50905dfd-2a76-4d9c-9c5a-43aadac0b03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857642190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.857642190
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1950896289
Short name T534
Test name
Test status
Simulation time 1515499529 ps
CPU time 5.52 seconds
Started Jul 10 05:44:33 PM PDT 24
Finished Jul 10 05:44:39 PM PDT 24
Peak memory 225540 kb
Host smart-c356ff3e-4950-4895-a02a-f75767452066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950896289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1950896289
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1914441031
Short name T372
Test name
Test status
Simulation time 45260352 ps
CPU time 0.75 seconds
Started Jul 10 05:44:33 PM PDT 24
Finished Jul 10 05:44:35 PM PDT 24
Peak memory 206740 kb
Host smart-25650f60-a71c-46b0-958c-848217c51bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914441031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1914441031
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1515359446
Short name T821
Test name
Test status
Simulation time 9861739714 ps
CPU time 39.34 seconds
Started Jul 10 05:44:37 PM PDT 24
Finished Jul 10 05:45:17 PM PDT 24
Peak memory 254676 kb
Host smart-48a2360f-d6ef-4dfb-afe2-86498f8b3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515359446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1515359446
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1570534151
Short name T62
Test name
Test status
Simulation time 158513833044 ps
CPU time 394.89 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:51:17 PM PDT 24
Peak memory 256500 kb
Host smart-d533d893-20fc-4f82-9520-891d9d8b114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570534151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1570534151
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1509619563
Short name T970
Test name
Test status
Simulation time 15169898001 ps
CPU time 39.9 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:45:23 PM PDT 24
Peak memory 225792 kb
Host smart-f363b8bc-a310-4c04-be53-0d34ae9579b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509619563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1509619563
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1187171135
Short name T54
Test name
Test status
Simulation time 131906722 ps
CPU time 5.16 seconds
Started Jul 10 05:44:34 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 236848 kb
Host smart-85d01758-6ea4-48dc-9c92-00339911b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187171135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1187171135
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1151661271
Short name T237
Test name
Test status
Simulation time 108711639328 ps
CPU time 228.5 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 253616 kb
Host smart-5d9bf05a-d3f8-4613-b840-2b79a3d9006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151661271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1151661271
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.770519017
Short name T259
Test name
Test status
Simulation time 3639258374 ps
CPU time 13.53 seconds
Started Jul 10 05:44:34 PM PDT 24
Finished Jul 10 05:44:48 PM PDT 24
Peak memory 225648 kb
Host smart-1e1bee23-1a75-43c6-94c7-00c3580d29b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770519017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.770519017
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3751476325
Short name T651
Test name
Test status
Simulation time 4887175964 ps
CPU time 64.2 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 233808 kb
Host smart-ecb4123b-e4e4-4861-931b-b3d7760c6741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751476325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3751476325
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1184858897
Short name T487
Test name
Test status
Simulation time 927966286 ps
CPU time 4.74 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 225588 kb
Host smart-4745d310-46aa-47d0-9396-f3ea07318d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184858897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1184858897
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3454975660
Short name T213
Test name
Test status
Simulation time 798384754 ps
CPU time 2.73 seconds
Started Jul 10 05:44:39 PM PDT 24
Finished Jul 10 05:44:42 PM PDT 24
Peak memory 225556 kb
Host smart-017f6579-0e68-446d-a495-116218c82496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454975660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3454975660
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4045798142
Short name T48
Test name
Test status
Simulation time 748178796 ps
CPU time 12.54 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:44:49 PM PDT 24
Peak memory 221444 kb
Host smart-fca6c536-37da-46ec-9149-796e28e6a2f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045798142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4045798142
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2926701629
Short name T958
Test name
Test status
Simulation time 79129515597 ps
CPU time 226.55 seconds
Started Jul 10 05:44:40 PM PDT 24
Finished Jul 10 05:48:27 PM PDT 24
Peak memory 250684 kb
Host smart-4a2f58fa-fa1b-4c17-a9ec-f5157a799744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926701629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2926701629
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3880935484
Short name T297
Test name
Test status
Simulation time 7057186141 ps
CPU time 17.17 seconds
Started Jul 10 05:44:33 PM PDT 24
Finished Jul 10 05:44:51 PM PDT 24
Peak memory 217456 kb
Host smart-1c366034-95f3-42f1-8947-5ed7ddb8ecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880935484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3880935484
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4008206963
Short name T495
Test name
Test status
Simulation time 330612997 ps
CPU time 1.13 seconds
Started Jul 10 05:44:35 PM PDT 24
Finished Jul 10 05:44:38 PM PDT 24
Peak memory 208756 kb
Host smart-1ede0fdb-bdca-49cf-b43b-85f8a552cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008206963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4008206963
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.253731284
Short name T602
Test name
Test status
Simulation time 2460793077 ps
CPU time 2.4 seconds
Started Jul 10 05:44:38 PM PDT 24
Finished Jul 10 05:44:41 PM PDT 24
Peak memory 217376 kb
Host smart-154eb968-9471-4276-a99c-c671bf383471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253731284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.253731284
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3068179932
Short name T552
Test name
Test status
Simulation time 43803216 ps
CPU time 0.88 seconds
Started Jul 10 05:44:34 PM PDT 24
Finished Jul 10 05:44:36 PM PDT 24
Peak memory 206888 kb
Host smart-933341e2-3368-468e-ba2f-96856839b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068179932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3068179932
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1103498235
Short name T867
Test name
Test status
Simulation time 3328173412 ps
CPU time 10.08 seconds
Started Jul 10 05:44:38 PM PDT 24
Finished Jul 10 05:44:49 PM PDT 24
Peak memory 233832 kb
Host smart-86b587eb-9f2a-4fff-b739-7a1188691e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103498235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1103498235
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2155894544
Short name T649
Test name
Test status
Simulation time 25231386 ps
CPU time 0.72 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:44:52 PM PDT 24
Peak memory 205804 kb
Host smart-720b3463-4d70-4f4f-81dd-3e909aa58c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155894544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2155894544
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3516732133
Short name T9
Test name
Test status
Simulation time 7123773898 ps
CPU time 19.32 seconds
Started Jul 10 05:44:49 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 233940 kb
Host smart-b4c1d68b-b888-43d3-a665-b8da3329e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516732133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3516732133
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3057535833
Short name T738
Test name
Test status
Simulation time 21737643 ps
CPU time 0.81 seconds
Started Jul 10 05:44:44 PM PDT 24
Finished Jul 10 05:44:46 PM PDT 24
Peak memory 207484 kb
Host smart-5e762c5b-1d9c-4224-8e85-090fb14cac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057535833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3057535833
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2264370499
Short name T362
Test name
Test status
Simulation time 4578310675 ps
CPU time 34.86 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:45:27 PM PDT 24
Peak memory 242112 kb
Host smart-0134f656-cb35-441b-8796-32d520a2c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264370499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2264370499
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.651444375
Short name T461
Test name
Test status
Simulation time 15819681648 ps
CPU time 51.06 seconds
Started Jul 10 05:44:49 PM PDT 24
Finished Jul 10 05:45:41 PM PDT 24
Peak memory 242188 kb
Host smart-6811d8fc-ab17-48f3-aeb6-449696582579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651444375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.651444375
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2063223272
Short name T127
Test name
Test status
Simulation time 18042288088 ps
CPU time 75.13 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:46:07 PM PDT 24
Peak memory 250360 kb
Host smart-d7c28299-2d66-4885-b9d1-787ee5b31a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063223272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2063223272
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1354780135
Short name T292
Test name
Test status
Simulation time 849049024 ps
CPU time 5.79 seconds
Started Jul 10 05:44:48 PM PDT 24
Finished Jul 10 05:44:54 PM PDT 24
Peak memory 225584 kb
Host smart-66d2a885-3ae3-4fbf-9120-08ba6039bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354780135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1354780135
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2936937438
Short name T873
Test name
Test status
Simulation time 57256743965 ps
CPU time 81.66 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:46:12 PM PDT 24
Peak memory 238284 kb
Host smart-624d1ad3-d282-4c28-8052-59e387ac303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936937438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2936937438
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.664277875
Short name T648
Test name
Test status
Simulation time 149568811 ps
CPU time 2.7 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:44:45 PM PDT 24
Peak memory 233956 kb
Host smart-2be7f5d5-25a8-4db7-8f26-886b7d3cfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664277875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.664277875
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1357406616
Short name T583
Test name
Test status
Simulation time 147483516 ps
CPU time 2.65 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:44:45 PM PDT 24
Peak memory 233500 kb
Host smart-798abd0f-0608-43d3-9ea4-4ab17cca7919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357406616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1357406616
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2704112238
Short name T792
Test name
Test status
Simulation time 1381802380 ps
CPU time 12.69 seconds
Started Jul 10 05:44:39 PM PDT 24
Finished Jul 10 05:44:53 PM PDT 24
Peak memory 233716 kb
Host smart-d90175b2-dedb-4672-aa20-8d1000a284c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704112238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2704112238
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.607177425
Short name T575
Test name
Test status
Simulation time 1409644818 ps
CPU time 6.7 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:44:49 PM PDT 24
Peak memory 233696 kb
Host smart-53b3808b-59ee-4ae4-a198-e7998895fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607177425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.607177425
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3003188724
Short name T507
Test name
Test status
Simulation time 1741968911 ps
CPU time 5.14 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:44:56 PM PDT 24
Peak memory 224164 kb
Host smart-94d48d03-9b39-4c58-a2c5-6f1ca040b831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3003188724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3003188724
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3831558835
Short name T21
Test name
Test status
Simulation time 81595378 ps
CPU time 1.24 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:44:53 PM PDT 24
Peak memory 208576 kb
Host smart-f76e7bfc-caa0-4ffa-8a51-62f50f5bbf02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831558835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3831558835
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3444168194
Short name T296
Test name
Test status
Simulation time 2561466887 ps
CPU time 14.5 seconds
Started Jul 10 05:44:43 PM PDT 24
Finished Jul 10 05:44:58 PM PDT 24
Peak memory 217452 kb
Host smart-2d1c610f-14b2-47de-9654-d5c1272f6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444168194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3444168194
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.311622622
Short name T439
Test name
Test status
Simulation time 2701016076 ps
CPU time 9.99 seconds
Started Jul 10 05:44:45 PM PDT 24
Finished Jul 10 05:44:56 PM PDT 24
Peak memory 217476 kb
Host smart-c5e1e820-efcf-4073-a427-d66e5db093a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311622622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.311622622
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.764732283
Short name T900
Test name
Test status
Simulation time 99622155 ps
CPU time 1.18 seconds
Started Jul 10 05:44:40 PM PDT 24
Finished Jul 10 05:44:42 PM PDT 24
Peak memory 217160 kb
Host smart-1caa2cc8-55cc-4f61-96a8-c1a3657a2155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764732283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.764732283
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2153792851
Short name T371
Test name
Test status
Simulation time 24412673 ps
CPU time 0.7 seconds
Started Jul 10 05:44:39 PM PDT 24
Finished Jul 10 05:44:40 PM PDT 24
Peak memory 206956 kb
Host smart-9f867c62-dc60-497c-a24d-d7077ca9953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153792851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2153792851
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1723233834
Short name T646
Test name
Test status
Simulation time 54207005545 ps
CPU time 36.72 seconds
Started Jul 10 05:44:41 PM PDT 24
Finished Jul 10 05:45:19 PM PDT 24
Peak memory 234140 kb
Host smart-b32f4728-32cd-4aad-b2bc-36ac5caeae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723233834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1723233834
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1805032006
Short name T454
Test name
Test status
Simulation time 14043546 ps
CPU time 0.73 seconds
Started Jul 10 05:44:56 PM PDT 24
Finished Jul 10 05:44:58 PM PDT 24
Peak memory 206308 kb
Host smart-3fbf8f79-9ae4-4ad5-b161-ac1e127d66f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805032006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1805032006
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2022971589
Short name T125
Test name
Test status
Simulation time 211636279 ps
CPU time 3.49 seconds
Started Jul 10 05:44:57 PM PDT 24
Finished Jul 10 05:45:02 PM PDT 24
Peak memory 225544 kb
Host smart-b5a43376-b664-4cbb-b408-285a7b138dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022971589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2022971589
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.214861113
Short name T518
Test name
Test status
Simulation time 17963758 ps
CPU time 0.73 seconds
Started Jul 10 05:44:48 PM PDT 24
Finished Jul 10 05:44:50 PM PDT 24
Peak memory 207800 kb
Host smart-26e0bf79-21a6-4dce-8c42-053c9efabefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214861113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.214861113
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1537003671
Short name T208
Test name
Test status
Simulation time 34647242736 ps
CPU time 212.34 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:48:33 PM PDT 24
Peak memory 258444 kb
Host smart-d7ae2050-0402-492b-9973-5a33b8e495cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537003671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1537003671
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.710013574
Short name T223
Test name
Test status
Simulation time 15914356743 ps
CPU time 164.92 seconds
Started Jul 10 05:44:57 PM PDT 24
Finished Jul 10 05:47:43 PM PDT 24
Peak memory 274320 kb
Host smart-9d528828-9769-4eb1-9cf2-53af27198a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710013574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.710013574
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.519837645
Short name T637
Test name
Test status
Simulation time 13872227947 ps
CPU time 19.38 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:19 PM PDT 24
Peak memory 218836 kb
Host smart-9a5e4708-a0ea-4347-83bb-f574c25af7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519837645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.519837645
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.392120096
Short name T133
Test name
Test status
Simulation time 8064787795 ps
CPU time 20.35 seconds
Started Jul 10 05:44:58 PM PDT 24
Finished Jul 10 05:45:19 PM PDT 24
Peak memory 225684 kb
Host smart-4e2dc8c7-c60f-406c-b58c-f688bde935b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392120096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.392120096
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1747460022
Short name T1006
Test name
Test status
Simulation time 7094487042 ps
CPU time 9.69 seconds
Started Jul 10 05:44:49 PM PDT 24
Finished Jul 10 05:45:00 PM PDT 24
Peak memory 225616 kb
Host smart-5c5d0701-0c05-4295-a3f3-23077d252b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747460022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1747460022
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1931562657
Short name T3
Test name
Test status
Simulation time 10332099095 ps
CPU time 32.13 seconds
Started Jul 10 05:44:48 PM PDT 24
Finished Jul 10 05:45:21 PM PDT 24
Peak memory 225620 kb
Host smart-40bdb609-9732-46d2-89a3-cd728c5834cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931562657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1931562657
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2829777943
Short name T806
Test name
Test status
Simulation time 3579685636 ps
CPU time 9.77 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:45:01 PM PDT 24
Peak memory 250588 kb
Host smart-5fbee5ca-8280-4b18-959c-bc86801beb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829777943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2829777943
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1254187172
Short name T967
Test name
Test status
Simulation time 15025080147 ps
CPU time 19.26 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 233852 kb
Host smart-5ead5582-ddc3-4432-aa85-46f43bff8647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254187172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1254187172
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.52942364
Short name T609
Test name
Test status
Simulation time 435691841 ps
CPU time 5.75 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:05 PM PDT 24
Peak memory 220972 kb
Host smart-6c17a211-5b64-4c7a-8037-0cfbd362d2a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52942364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.52942364
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3350856946
Short name T788
Test name
Test status
Simulation time 348044838 ps
CPU time 1.27 seconds
Started Jul 10 05:44:58 PM PDT 24
Finished Jul 10 05:45:01 PM PDT 24
Peak memory 208852 kb
Host smart-01beae06-d6aa-4be3-b965-355b28ed7649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350856946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3350856946
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.778302080
Short name T500
Test name
Test status
Simulation time 1760555558 ps
CPU time 7.18 seconds
Started Jul 10 05:44:49 PM PDT 24
Finished Jul 10 05:44:57 PM PDT 24
Peak memory 217336 kb
Host smart-209f2b8b-d714-445a-af5d-8bcd9a110701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778302080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.778302080
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1675070121
Short name T25
Test name
Test status
Simulation time 1326135461 ps
CPU time 7.73 seconds
Started Jul 10 05:44:51 PM PDT 24
Finished Jul 10 05:45:00 PM PDT 24
Peak memory 217320 kb
Host smart-d2efbc1e-27fa-4a4d-8fa2-8e1d1d4080eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675070121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1675070121
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1896756670
Short name T874
Test name
Test status
Simulation time 20494490 ps
CPU time 0.71 seconds
Started Jul 10 05:44:50 PM PDT 24
Finished Jul 10 05:44:52 PM PDT 24
Peak memory 206524 kb
Host smart-128c088f-d4f4-42d1-bf7f-47c6676c2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896756670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1896756670
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1362480003
Short name T379
Test name
Test status
Simulation time 79184940 ps
CPU time 0.81 seconds
Started Jul 10 05:44:49 PM PDT 24
Finished Jul 10 05:44:51 PM PDT 24
Peak memory 206948 kb
Host smart-49422a42-98e7-42c9-b4b5-164b4112e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362480003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1362480003
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2131546471
Short name T250
Test name
Test status
Simulation time 404927988 ps
CPU time 7.76 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:08 PM PDT 24
Peak memory 225524 kb
Host smart-f36d0486-dce8-4f5a-99be-356c1a1f2d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131546471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2131546471
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4000256348
Short name T368
Test name
Test status
Simulation time 37364015 ps
CPU time 0.73 seconds
Started Jul 10 05:45:06 PM PDT 24
Finished Jul 10 05:45:08 PM PDT 24
Peak memory 206368 kb
Host smart-01c0d937-c3ab-45f8-83f4-23f170203b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000256348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4000256348
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.420330880
Short name T979
Test name
Test status
Simulation time 371525522 ps
CPU time 3.23 seconds
Started Jul 10 05:44:58 PM PDT 24
Finished Jul 10 05:45:02 PM PDT 24
Peak memory 233704 kb
Host smart-96efa817-718e-4b03-ad48-cd348d17828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420330880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.420330880
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4156055000
Short name T122
Test name
Test status
Simulation time 19525856 ps
CPU time 0.83 seconds
Started Jul 10 05:44:57 PM PDT 24
Finished Jul 10 05:44:58 PM PDT 24
Peak memory 207836 kb
Host smart-a306e08b-39f2-48e1-9cd1-00f70e5de9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156055000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4156055000
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1026159204
Short name T174
Test name
Test status
Simulation time 60162957734 ps
CPU time 240.68 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:49:00 PM PDT 24
Peak memory 250496 kb
Host smart-2b0c3cf4-dd64-4a49-a81c-b4393649c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026159204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1026159204
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3566848336
Short name T988
Test name
Test status
Simulation time 38614874866 ps
CPU time 131.6 seconds
Started Jul 10 05:45:02 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 239500 kb
Host smart-096ab598-191e-4c87-9e00-7a4aba111000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566848336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3566848336
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3678468415
Short name T59
Test name
Test status
Simulation time 4193140193 ps
CPU time 45.03 seconds
Started Jul 10 05:45:08 PM PDT 24
Finished Jul 10 05:45:53 PM PDT 24
Peak memory 250408 kb
Host smart-fccc9847-9016-4786-b503-d794901b07f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678468415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3678468415
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1821080004
Short name T312
Test name
Test status
Simulation time 15331939486 ps
CPU time 49.82 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:50 PM PDT 24
Peak memory 250268 kb
Host smart-ad905cb8-590d-48c3-b07c-20b75a2c1147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821080004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1821080004
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3198192106
Short name T219
Test name
Test status
Simulation time 2744349761 ps
CPU time 28.75 seconds
Started Jul 10 05:44:58 PM PDT 24
Finished Jul 10 05:45:28 PM PDT 24
Peak memory 233864 kb
Host smart-c374fcc4-bdb7-4c01-9847-a3d856cc0083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198192106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3198192106
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4058632962
Short name T193
Test name
Test status
Simulation time 12614180929 ps
CPU time 12 seconds
Started Jul 10 05:44:57 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 225616 kb
Host smart-2010e722-0082-44ac-a7f4-80ac32406b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058632962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4058632962
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4160090001
Short name T862
Test name
Test status
Simulation time 772133321 ps
CPU time 6.3 seconds
Started Jul 10 05:45:03 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 233772 kb
Host smart-fc79a035-68e9-44f9-bffe-14377a16dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160090001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4160090001
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2553142389
Short name T420
Test name
Test status
Simulation time 232403844 ps
CPU time 4.65 seconds
Started Jul 10 05:44:56 PM PDT 24
Finished Jul 10 05:45:01 PM PDT 24
Peak memory 224080 kb
Host smart-ec9486f3-402e-4d4f-b689-06bbadb8001b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2553142389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2553142389
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2485528169
Short name T428
Test name
Test status
Simulation time 43990284 ps
CPU time 0.94 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:06 PM PDT 24
Peak memory 206856 kb
Host smart-958fd93f-eca1-4283-9194-3a94f70dd9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485528169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2485528169
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4037909898
Short name T674
Test name
Test status
Simulation time 1480586690 ps
CPU time 24.78 seconds
Started Jul 10 05:44:56 PM PDT 24
Finished Jul 10 05:45:21 PM PDT 24
Peak memory 217692 kb
Host smart-9327f252-89ff-4a66-a137-05b0bb88cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037909898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4037909898
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1279650787
Short name T742
Test name
Test status
Simulation time 1012192156 ps
CPU time 6.64 seconds
Started Jul 10 05:45:03 PM PDT 24
Finished Jul 10 05:45:11 PM PDT 24
Peak memory 217276 kb
Host smart-a7190b8a-43b7-4c1b-97fc-e97c7ff19447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279650787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1279650787
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.879241010
Short name T1011
Test name
Test status
Simulation time 93851730 ps
CPU time 0.94 seconds
Started Jul 10 05:44:56 PM PDT 24
Finished Jul 10 05:44:58 PM PDT 24
Peak memory 208068 kb
Host smart-8e799796-f8b1-4f32-b942-3c4b5bc73b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879241010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.879241010
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1237082710
Short name T525
Test name
Test status
Simulation time 151477094 ps
CPU time 1.11 seconds
Started Jul 10 05:44:59 PM PDT 24
Finished Jul 10 05:45:01 PM PDT 24
Peak memory 207944 kb
Host smart-1cab4fc8-2ac4-4f3c-a84d-fbb1c3003853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237082710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1237082710
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1782405130
Short name T998
Test name
Test status
Simulation time 127730014 ps
CPU time 3.47 seconds
Started Jul 10 05:45:03 PM PDT 24
Finished Jul 10 05:45:07 PM PDT 24
Peak memory 233792 kb
Host smart-234fb27d-3942-4b84-857d-8e4fddcb0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782405130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1782405130
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.487806658
Short name T399
Test name
Test status
Simulation time 28723565 ps
CPU time 0.69 seconds
Started Jul 10 05:45:07 PM PDT 24
Finished Jul 10 05:45:09 PM PDT 24
Peak memory 206280 kb
Host smart-e6341100-1a8f-4b5f-b1a7-28464c7180b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487806658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.487806658
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2506672795
Short name T456
Test name
Test status
Simulation time 4027086712 ps
CPU time 11.45 seconds
Started Jul 10 05:45:04 PM PDT 24
Finished Jul 10 05:45:16 PM PDT 24
Peak memory 225656 kb
Host smart-055c5f74-0254-4156-a8da-9b972be28be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506672795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2506672795
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3074918101
Short name T363
Test name
Test status
Simulation time 63262293 ps
CPU time 0.81 seconds
Started Jul 10 05:45:08 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 207840 kb
Host smart-2561c8d3-f832-4ce5-aefd-e53ed5ac314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074918101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3074918101
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3282967160
Short name T403
Test name
Test status
Simulation time 3986736575 ps
CPU time 35.75 seconds
Started Jul 10 05:45:04 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 256584 kb
Host smart-19204d4c-ba4b-4dcf-863a-0d0e988ecd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282967160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3282967160
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1197019851
Short name T606
Test name
Test status
Simulation time 3776817333 ps
CPU time 39.51 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:45 PM PDT 24
Peak memory 250392 kb
Host smart-28109bd9-2019-4bb5-b435-3c4ec46ec80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197019851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1197019851
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3674068065
Short name T49
Test name
Test status
Simulation time 10030074065 ps
CPU time 30.67 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:37 PM PDT 24
Peak memory 239840 kb
Host smart-602fcebc-0f54-4a69-8227-92839c403175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674068065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3674068065
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1417812765
Short name T585
Test name
Test status
Simulation time 121658021 ps
CPU time 5.08 seconds
Started Jul 10 05:45:03 PM PDT 24
Finished Jul 10 05:45:08 PM PDT 24
Peak memory 240960 kb
Host smart-dfdd1fcf-8b0f-43bd-859c-bdea9b2c2a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417812765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1417812765
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2814542585
Short name T961
Test name
Test status
Simulation time 12982476871 ps
CPU time 97.75 seconds
Started Jul 10 05:45:04 PM PDT 24
Finished Jul 10 05:46:43 PM PDT 24
Peak memory 250212 kb
Host smart-a38d56ef-bf6e-44db-ad85-9d88bbb1f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814542585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2814542585
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.304114590
Short name T475
Test name
Test status
Simulation time 5344552999 ps
CPU time 17.42 seconds
Started Jul 10 05:45:06 PM PDT 24
Finished Jul 10 05:45:25 PM PDT 24
Peak memory 233848 kb
Host smart-a56247bd-4b0c-4ebe-843e-19b364cd3548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304114590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.304114590
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2935607392
Short name T247
Test name
Test status
Simulation time 8301630501 ps
CPU time 23.45 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:30 PM PDT 24
Peak memory 233880 kb
Host smart-04287c9d-8d57-473f-82ed-853b637fe9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935607392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2935607392
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3238022829
Short name T960
Test name
Test status
Simulation time 399120299 ps
CPU time 2.34 seconds
Started Jul 10 05:45:07 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 224160 kb
Host smart-0e5986d5-de8a-4ea8-adc0-091995f4b301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238022829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3238022829
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1363370715
Short name T196
Test name
Test status
Simulation time 9050254968 ps
CPU time 26.42 seconds
Started Jul 10 05:45:06 PM PDT 24
Finished Jul 10 05:45:33 PM PDT 24
Peak memory 242004 kb
Host smart-457f0ede-84d5-4373-807a-3ccc83bcc1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363370715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1363370715
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3889577653
Short name T140
Test name
Test status
Simulation time 2934124379 ps
CPU time 8.13 seconds
Started Jul 10 05:45:04 PM PDT 24
Finished Jul 10 05:45:13 PM PDT 24
Peak memory 224104 kb
Host smart-e489c3f8-da1e-4608-8f40-f16fec94076d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3889577653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3889577653
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1427606306
Short name T600
Test name
Test status
Simulation time 615434936450 ps
CPU time 412.3 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:51:59 PM PDT 24
Peak memory 272576 kb
Host smart-ffd1cbb1-1a22-4ddf-b9d2-a54b2085671d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427606306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1427606306
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1208972781
Short name T706
Test name
Test status
Simulation time 1569501182 ps
CPU time 23.34 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:29 PM PDT 24
Peak memory 217636 kb
Host smart-2cfd9a99-1d6f-43c8-9dc5-4f610ddfd564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208972781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1208972781
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4017792537
Short name T421
Test name
Test status
Simulation time 4689711427 ps
CPU time 6.04 seconds
Started Jul 10 05:45:04 PM PDT 24
Finished Jul 10 05:45:11 PM PDT 24
Peak memory 217516 kb
Host smart-c6c69d89-60a2-4b52-a3dc-19a8de5a15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017792537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4017792537
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3229133724
Short name T596
Test name
Test status
Simulation time 377413250 ps
CPU time 2.05 seconds
Started Jul 10 05:45:06 PM PDT 24
Finished Jul 10 05:45:09 PM PDT 24
Peak memory 217372 kb
Host smart-937ac750-f5df-4cfe-8a9c-a4ea6a0d0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229133724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3229133724
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3571574125
Short name T905
Test name
Test status
Simulation time 24195526 ps
CPU time 0.8 seconds
Started Jul 10 05:45:05 PM PDT 24
Finished Jul 10 05:45:07 PM PDT 24
Peak memory 206956 kb
Host smart-56040e37-7302-44f4-b3f7-7506a25c38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571574125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3571574125
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3032075176
Short name T934
Test name
Test status
Simulation time 54884124 ps
CPU time 1.92 seconds
Started Jul 10 05:45:07 PM PDT 24
Finished Jul 10 05:45:10 PM PDT 24
Peak memory 225244 kb
Host smart-26632b42-87e7-4fe8-bb51-3e0f286b7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032075176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3032075176
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.838429806
Short name T593
Test name
Test status
Simulation time 31920625 ps
CPU time 0.71 seconds
Started Jul 10 05:45:16 PM PDT 24
Finished Jul 10 05:45:17 PM PDT 24
Peak memory 205232 kb
Host smart-e18dba4c-0e12-414e-a903-63357ea853ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838429806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.838429806
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1077333338
Short name T885
Test name
Test status
Simulation time 126066395 ps
CPU time 2.56 seconds
Started Jul 10 05:45:16 PM PDT 24
Finished Jul 10 05:45:19 PM PDT 24
Peak memory 225504 kb
Host smart-ef34622a-86a0-4b89-9893-287eea2d8647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077333338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1077333338
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4037369243
Short name T902
Test name
Test status
Simulation time 36715575 ps
CPU time 0.77 seconds
Started Jul 10 05:45:16 PM PDT 24
Finished Jul 10 05:45:17 PM PDT 24
Peak memory 207828 kb
Host smart-bf1ce8f1-d4be-4aef-85cd-57614a8e1a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037369243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4037369243
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.487716099
Short name T993
Test name
Test status
Simulation time 92841539342 ps
CPU time 169.88 seconds
Started Jul 10 05:45:15 PM PDT 24
Finished Jul 10 05:48:05 PM PDT 24
Peak memory 267064 kb
Host smart-3229e3ba-8d8d-4243-8b48-76fbb5b0a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487716099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.487716099
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1923517303
Short name T859
Test name
Test status
Simulation time 3179930682 ps
CPU time 69.19 seconds
Started Jul 10 05:45:15 PM PDT 24
Finished Jul 10 05:46:25 PM PDT 24
Peak memory 257668 kb
Host smart-dd1383ab-a1e4-41fe-974b-3503468e2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923517303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1923517303
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4113675849
Short name T968
Test name
Test status
Simulation time 98259969899 ps
CPU time 253.75 seconds
Started Jul 10 05:45:15 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 267420 kb
Host smart-3e05870b-02b5-40b6-a3a3-2e54fbde0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113675849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4113675849
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3640507682
Short name T65
Test name
Test status
Simulation time 42479297297 ps
CPU time 94.28 seconds
Started Jul 10 05:45:15 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 250232 kb
Host smart-ddc9fc8d-47b2-4a32-800a-a78197b349d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640507682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3640507682
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1566098574
Short name T703
Test name
Test status
Simulation time 1801607478 ps
CPU time 7.49 seconds
Started Jul 10 05:45:16 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 224932 kb
Host smart-28fddb78-6225-4cde-9a6e-6c97cc9de57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566098574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1566098574
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3976674912
Short name T491
Test name
Test status
Simulation time 106842834 ps
CPU time 2.16 seconds
Started Jul 10 05:45:13 PM PDT 24
Finished Jul 10 05:45:16 PM PDT 24
Peak memory 225136 kb
Host smart-d82b066b-34bc-4cba-904a-5e6197f67959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976674912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3976674912
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3518798599
Short name T447
Test name
Test status
Simulation time 40508841 ps
CPU time 2.71 seconds
Started Jul 10 05:45:14 PM PDT 24
Finished Jul 10 05:45:18 PM PDT 24
Peak memory 233704 kb
Host smart-dec1b221-6849-4692-b737-d9c01b2bdea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518798599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3518798599
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3774420989
Short name T123
Test name
Test status
Simulation time 36714643242 ps
CPU time 24.94 seconds
Started Jul 10 05:45:14 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 225700 kb
Host smart-bf3e0771-fe7d-464d-a9d7-4ec90641dffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774420989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3774420989
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.930719516
Short name T666
Test name
Test status
Simulation time 1671572044 ps
CPU time 10.6 seconds
Started Jul 10 05:45:14 PM PDT 24
Finished Jul 10 05:45:26 PM PDT 24
Peak memory 220228 kb
Host smart-e5b31fab-e91b-4623-bea9-f5ee7780fb76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=930719516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.930719516
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1631788717
Short name T936
Test name
Test status
Simulation time 41147096 ps
CPU time 0.96 seconds
Started Jul 10 05:45:13 PM PDT 24
Finished Jul 10 05:45:14 PM PDT 24
Peak memory 207628 kb
Host smart-9bb8d437-9306-45ca-9dcf-32415d5e8983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631788717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1631788717
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3138593176
Short name T690
Test name
Test status
Simulation time 1617522089 ps
CPU time 5.73 seconds
Started Jul 10 05:45:14 PM PDT 24
Finished Jul 10 05:45:20 PM PDT 24
Peak memory 217368 kb
Host smart-04c9b2c6-9ae6-4ec0-b71e-4cad61b8507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138593176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3138593176
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3633773074
Short name T70
Test name
Test status
Simulation time 3452011172 ps
CPU time 10.45 seconds
Started Jul 10 05:45:12 PM PDT 24
Finished Jul 10 05:45:23 PM PDT 24
Peak memory 217392 kb
Host smart-4f91128f-f799-499f-a876-e2eb6ec58a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633773074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3633773074
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1506325303
Short name T328
Test name
Test status
Simulation time 150033481 ps
CPU time 1.98 seconds
Started Jul 10 05:45:14 PM PDT 24
Finished Jul 10 05:45:17 PM PDT 24
Peak memory 217368 kb
Host smart-9c58548c-09da-4080-ad15-86883d3e3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506325303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1506325303
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3014503253
Short name T629
Test name
Test status
Simulation time 31549366 ps
CPU time 0.84 seconds
Started Jul 10 05:45:11 PM PDT 24
Finished Jul 10 05:45:13 PM PDT 24
Peak memory 206888 kb
Host smart-6533022b-180b-434b-b210-517a595a4c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014503253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3014503253
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.57795224
Short name T800
Test name
Test status
Simulation time 1142790004 ps
CPU time 4.84 seconds
Started Jul 10 05:45:12 PM PDT 24
Finished Jul 10 05:45:18 PM PDT 24
Peak memory 225544 kb
Host smart-5672349e-a44a-4b2d-bebc-00e5810e1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57795224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.57795224
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1178726901
Short name T999
Test name
Test status
Simulation time 13434773 ps
CPU time 0.75 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:23 PM PDT 24
Peak memory 206308 kb
Host smart-76ff8a00-4901-430a-b87a-36624cf4f8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178726901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1178726901
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2137657420
Short name T314
Test name
Test status
Simulation time 53429212 ps
CPU time 2.21 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 233428 kb
Host smart-5b29b5cc-2812-445a-aab8-11bafae53220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137657420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2137657420
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.677747411
Short name T790
Test name
Test status
Simulation time 59890038 ps
CPU time 0.8 seconds
Started Jul 10 05:45:16 PM PDT 24
Finished Jul 10 05:45:17 PM PDT 24
Peak memory 206800 kb
Host smart-274c0962-39cf-4d82-9409-e08afae1f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677747411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.677747411
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3037224969
Short name T898
Test name
Test status
Simulation time 3079862212 ps
CPU time 21.14 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:45 PM PDT 24
Peak memory 250300 kb
Host smart-82a9883d-eb14-454e-bb3e-62b663ff14f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037224969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3037224969
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2921371231
Short name T561
Test name
Test status
Simulation time 5918026098 ps
CPU time 34.45 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:58 PM PDT 24
Peak memory 241672 kb
Host smart-44bc6e33-daf0-4b98-81a1-0cadd8c6dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921371231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2921371231
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1052123753
Short name T996
Test name
Test status
Simulation time 70395759675 ps
CPU time 585.68 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:55:06 PM PDT 24
Peak memory 267412 kb
Host smart-3f5870ef-dba6-416a-a792-d17cff6b23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052123753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1052123753
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.784188862
Short name T568
Test name
Test status
Simulation time 5229684144 ps
CPU time 17.82 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 225684 kb
Host smart-a6825dad-9c1b-48ca-9598-e9ed610505d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784188862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.784188862
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.561996888
Short name T976
Test name
Test status
Simulation time 5048694023 ps
CPU time 40.35 seconds
Started Jul 10 05:45:19 PM PDT 24
Finished Jul 10 05:46:00 PM PDT 24
Peak memory 250776 kb
Host smart-f47b612b-d7e5-4aa2-a8b4-c4936d6b9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561996888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.561996888
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3770113154
Short name T681
Test name
Test status
Simulation time 528318661 ps
CPU time 4.76 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:26 PM PDT 24
Peak memory 233840 kb
Host smart-75876d99-8f1f-4311-a7d1-8fa7b4454b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770113154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3770113154
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.105209759
Short name T55
Test name
Test status
Simulation time 11369433200 ps
CPU time 38.32 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:46:01 PM PDT 24
Peak memory 250236 kb
Host smart-b2aa83eb-5b40-4879-bc92-7e8dda0a68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105209759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.105209759
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1052127897
Short name T849
Test name
Test status
Simulation time 50496555606 ps
CPU time 33.25 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:54 PM PDT 24
Peak memory 249844 kb
Host smart-58efc273-8ff2-4068-ab56-58f2ae8b9de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052127897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1052127897
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1423516981
Short name T990
Test name
Test status
Simulation time 1449820727 ps
CPU time 7.03 seconds
Started Jul 10 05:45:18 PM PDT 24
Finished Jul 10 05:45:26 PM PDT 24
Peak memory 233796 kb
Host smart-edf79002-da1f-483c-81af-e35ec4a89a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423516981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1423516981
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3006977607
Short name T531
Test name
Test status
Simulation time 806872967 ps
CPU time 9.04 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:45:31 PM PDT 24
Peak memory 221112 kb
Host smart-d7a1e316-bdc3-40ac-864f-10c945a6a50a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006977607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3006977607
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4053158311
Short name T866
Test name
Test status
Simulation time 247763032 ps
CPU time 1.16 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:25 PM PDT 24
Peak memory 208108 kb
Host smart-53304d11-c65a-4126-a466-1f57642c3f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053158311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4053158311
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1900660100
Short name T652
Test name
Test status
Simulation time 319948330 ps
CPU time 2.83 seconds
Started Jul 10 05:45:19 PM PDT 24
Finished Jul 10 05:45:22 PM PDT 24
Peak memory 217316 kb
Host smart-95e9d567-54e6-458d-9026-03458bcfa8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900660100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1900660100
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4030899695
Short name T931
Test name
Test status
Simulation time 1212820871 ps
CPU time 7.44 seconds
Started Jul 10 05:45:13 PM PDT 24
Finished Jul 10 05:45:21 PM PDT 24
Peak memory 217308 kb
Host smart-e75ae40d-db06-46e5-8ec4-bb20be66469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030899695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4030899695
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2226532198
Short name T538
Test name
Test status
Simulation time 20339370 ps
CPU time 0.78 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 206952 kb
Host smart-a11a8674-a652-4cf9-a00a-8a34ce2b243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226532198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2226532198
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.763268911
Short name T718
Test name
Test status
Simulation time 51692689 ps
CPU time 0.75 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:22 PM PDT 24
Peak memory 206888 kb
Host smart-844f6fa5-5764-4c89-9ef9-89bca6b3bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763268911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.763268911
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2532924681
Short name T175
Test name
Test status
Simulation time 3632025873 ps
CPU time 11.38 seconds
Started Jul 10 05:45:19 PM PDT 24
Finished Jul 10 05:45:31 PM PDT 24
Peak memory 233808 kb
Host smart-76f6e8f6-a589-4a29-b8d5-8c6f72fbe7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532924681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2532924681
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.956058455
Short name T689
Test name
Test status
Simulation time 22451215 ps
CPU time 0.73 seconds
Started Jul 10 05:45:27 PM PDT 24
Finished Jul 10 05:45:28 PM PDT 24
Peak memory 205736 kb
Host smart-946d988e-35d2-4bc9-9ca7-4d82e8754df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956058455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.956058455
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.469921076
Short name T829
Test name
Test status
Simulation time 51477597 ps
CPU time 2.84 seconds
Started Jul 10 05:45:26 PM PDT 24
Finished Jul 10 05:45:29 PM PDT 24
Peak memory 233728 kb
Host smart-c5b54e0a-a9c5-49b2-b24c-5adc586a85ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469921076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.469921076
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2832914886
Short name T24
Test name
Test status
Simulation time 34882973 ps
CPU time 0.77 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:45:23 PM PDT 24
Peak memory 207828 kb
Host smart-35d75f91-ddde-4150-8c14-08704d00e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832914886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2832914886
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3175600616
Short name T614
Test name
Test status
Simulation time 101210995360 ps
CPU time 190 seconds
Started Jul 10 05:45:28 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 255596 kb
Host smart-497c1511-0d44-45b3-9424-45acd01bfd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175600616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3175600616
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1059037662
Short name T728
Test name
Test status
Simulation time 34817336923 ps
CPU time 76.71 seconds
Started Jul 10 05:45:28 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 238756 kb
Host smart-97498c3c-a014-43e0-a0dc-4eda2f76f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059037662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1059037662
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1273188190
Short name T83
Test name
Test status
Simulation time 176892610841 ps
CPU time 412.62 seconds
Started Jul 10 05:45:28 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 251852 kb
Host smart-9a4d3b24-e3d9-45d1-a06d-d75d05c9b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273188190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1273188190
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2280288405
Short name T942
Test name
Test status
Simulation time 2665317269 ps
CPU time 9.21 seconds
Started Jul 10 05:45:26 PM PDT 24
Finished Jul 10 05:45:36 PM PDT 24
Peak memory 234936 kb
Host smart-90102fc0-3b6e-402e-bd23-4143ebb26703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280288405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2280288405
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3147509352
Short name T423
Test name
Test status
Simulation time 7879192519 ps
CPU time 49.67 seconds
Started Jul 10 05:45:27 PM PDT 24
Finished Jul 10 05:46:18 PM PDT 24
Peak memory 251544 kb
Host smart-4889c55a-e641-494f-ac47-19cf6780c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147509352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3147509352
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.86989906
Short name T683
Test name
Test status
Simulation time 145371943 ps
CPU time 2.4 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:24 PM PDT 24
Peak memory 224896 kb
Host smart-f63a2245-b5da-473f-9943-39241ac01b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86989906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.86989906
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.327677882
Short name T569
Test name
Test status
Simulation time 836667041 ps
CPU time 5.05 seconds
Started Jul 10 05:45:29 PM PDT 24
Finished Jul 10 05:45:35 PM PDT 24
Peak memory 233764 kb
Host smart-121a6501-af9d-4de2-89c4-1cac443ea3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327677882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.327677882
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1371036785
Short name T209
Test name
Test status
Simulation time 3145702294 ps
CPU time 7.84 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:31 PM PDT 24
Peak memory 233860 kb
Host smart-65710ad1-4662-4f69-8dd1-8e60601d6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371036785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1371036785
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.305589275
Short name T407
Test name
Test status
Simulation time 445022538 ps
CPU time 3.73 seconds
Started Jul 10 05:45:22 PM PDT 24
Finished Jul 10 05:45:27 PM PDT 24
Peak memory 225576 kb
Host smart-d6113e23-b14c-4fc0-b6eb-7848c3dbd1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305589275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.305589275
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2558586094
Short name T643
Test name
Test status
Simulation time 260074948 ps
CPU time 3.93 seconds
Started Jul 10 05:45:28 PM PDT 24
Finished Jul 10 05:45:33 PM PDT 24
Peak memory 221368 kb
Host smart-b7804ed1-fa6b-4856-9f3f-5d02dc3a7b13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558586094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2558586094
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4003564492
Short name T285
Test name
Test status
Simulation time 69306773905 ps
CPU time 614.17 seconds
Started Jul 10 05:45:28 PM PDT 24
Finished Jul 10 05:55:43 PM PDT 24
Peak memory 273984 kb
Host smart-3a791c8f-21ec-442b-8f1f-ee092cac74e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003564492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4003564492
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1494470513
Short name T300
Test name
Test status
Simulation time 6177248078 ps
CPU time 37.21 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:45:59 PM PDT 24
Peak memory 217548 kb
Host smart-fbbd86cc-25ad-44b1-a43f-abc3e934146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494470513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1494470513
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3789210026
Short name T329
Test name
Test status
Simulation time 1878966229 ps
CPU time 7.95 seconds
Started Jul 10 05:45:21 PM PDT 24
Finished Jul 10 05:45:30 PM PDT 24
Peak memory 217292 kb
Host smart-fc4ccaf4-0ad7-4ed1-b099-b6efefb89d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789210026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3789210026
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.843732657
Short name T916
Test name
Test status
Simulation time 104790905 ps
CPU time 4.7 seconds
Started Jul 10 05:45:19 PM PDT 24
Finished Jul 10 05:45:25 PM PDT 24
Peak memory 217316 kb
Host smart-e32ee76e-db25-4160-a17f-a06fdee779ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843732657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.843732657
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3280981665
Short name T901
Test name
Test status
Simulation time 16991136 ps
CPU time 0.7 seconds
Started Jul 10 05:45:20 PM PDT 24
Finished Jul 10 05:45:22 PM PDT 24
Peak memory 206936 kb
Host smart-123b0d82-51b8-4128-9031-2da9a6f2137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280981665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3280981665
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.72282113
Short name T835
Test name
Test status
Simulation time 2237656740 ps
CPU time 6.42 seconds
Started Jul 10 05:45:27 PM PDT 24
Finished Jul 10 05:45:34 PM PDT 24
Peak memory 233844 kb
Host smart-3f4ecd73-9256-4dc3-bb63-2358304290dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72282113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.72282113
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3816810168
Short name T817
Test name
Test status
Simulation time 15150394 ps
CPU time 0.76 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:39 PM PDT 24
Peak memory 206000 kb
Host smart-8a3c6e23-d9d1-4fa2-b651-466feb19ae80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816810168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
816810168
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.856006069
Short name T82
Test name
Test status
Simulation time 179907962 ps
CPU time 2.46 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:41 PM PDT 24
Peak memory 233636 kb
Host smart-04927377-216e-482e-b60b-5e2d38f41561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856006069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.856006069
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1242592772
Short name T545
Test name
Test status
Simulation time 40805892 ps
CPU time 0.8 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:32 PM PDT 24
Peak memory 207828 kb
Host smart-f87683b7-e189-4ad7-b794-815dbc726991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242592772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1242592772
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3114253289
Short name T398
Test name
Test status
Simulation time 2531762543 ps
CPU time 18.38 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:57 PM PDT 24
Peak memory 234916 kb
Host smart-3e939950-1b91-4ce2-b726-d113d447887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114253289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3114253289
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2939486773
Short name T621
Test name
Test status
Simulation time 43495500897 ps
CPU time 201.5 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:44:59 PM PDT 24
Peak memory 258564 kb
Host smart-622f8241-13a1-4480-a257-d36c65223668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939486773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2939486773
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1804773922
Short name T291
Test name
Test status
Simulation time 1942395977 ps
CPU time 19.96 seconds
Started Jul 10 05:41:38 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 225564 kb
Host smart-2c8b5a40-797c-4c40-9287-a3eb9d9141b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804773922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1804773922
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2657875762
Short name T419
Test name
Test status
Simulation time 19805403450 ps
CPU time 69.97 seconds
Started Jul 10 05:41:37 PM PDT 24
Finished Jul 10 05:42:49 PM PDT 24
Peak memory 256412 kb
Host smart-4efc09de-ea78-4194-8183-a9307b32efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657875762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2657875762
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3624812353
Short name T938
Test name
Test status
Simulation time 1524774332 ps
CPU time 4.49 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:43 PM PDT 24
Peak memory 225464 kb
Host smart-7e5e76ec-ff66-4b89-a168-e80641fbe2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624812353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3624812353
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4210769697
Short name T839
Test name
Test status
Simulation time 8234148608 ps
CPU time 67.12 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:42:45 PM PDT 24
Peak memory 241508 kb
Host smart-3e368072-6558-4baf-9d90-63e52589168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210769697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4210769697
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.14518045
Short name T598
Test name
Test status
Simulation time 57619661 ps
CPU time 1.16 seconds
Started Jul 10 05:41:30 PM PDT 24
Finished Jul 10 05:41:33 PM PDT 24
Peak memory 217836 kb
Host smart-cda2369f-ea8c-40cf-a50c-68ee7a81be45
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14518045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.14518045
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2884491437
Short name T558
Test name
Test status
Simulation time 599787524 ps
CPU time 6.71 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 225440 kb
Host smart-705d3b33-d3a4-4565-a14f-22002140325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884491437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2884491437
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3621253644
Short name T770
Test name
Test status
Simulation time 200750704 ps
CPU time 4.11 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 233708 kb
Host smart-ed919b6a-1235-4da3-acc5-32d9553aab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621253644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3621253644
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1106678001
Short name T876
Test name
Test status
Simulation time 431296960 ps
CPU time 3.44 seconds
Started Jul 10 05:41:40 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 220364 kb
Host smart-34ec4358-7cb9-4afc-b34e-22d16734ce2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1106678001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1106678001
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2216220056
Short name T14
Test name
Test status
Simulation time 109232906 ps
CPU time 1.11 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:39 PM PDT 24
Peak memory 236264 kb
Host smart-51b1013f-bd96-44b8-a9a0-9fde9b952c88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216220056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2216220056
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.33707583
Short name T640
Test name
Test status
Simulation time 113169934975 ps
CPU time 315.99 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:46:52 PM PDT 24
Peak memory 254520 kb
Host smart-89720486-402b-4eb9-bdbd-d1d605e996e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33707583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.33707583
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2852967468
Short name T864
Test name
Test status
Simulation time 14793195 ps
CPU time 0.73 seconds
Started Jul 10 05:41:31 PM PDT 24
Finished Jul 10 05:41:34 PM PDT 24
Peak memory 206956 kb
Host smart-120a54e3-c31c-4bda-9c1b-cfe01716bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852967468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2852967468
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1381298306
Short name T476
Test name
Test status
Simulation time 5426268465 ps
CPU time 9.44 seconds
Started Jul 10 05:41:29 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 217416 kb
Host smart-7a95a603-3af3-425e-a465-c6215376bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381298306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1381298306
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3876464874
Short name T327
Test name
Test status
Simulation time 29590663 ps
CPU time 0.71 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:38 PM PDT 24
Peak memory 206556 kb
Host smart-c63071e6-6de3-4b7b-8a84-68bef89da78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876464874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3876464874
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.401281116
Short name T787
Test name
Test status
Simulation time 43635534 ps
CPU time 0.83 seconds
Started Jul 10 05:41:38 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 206948 kb
Host smart-983e0c43-5952-455b-ac58-c4fda3fadc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401281116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.401281116
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3619089853
Short name T541
Test name
Test status
Simulation time 6386525794 ps
CPU time 14.93 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:41:52 PM PDT 24
Peak memory 233916 kb
Host smart-50615461-262c-435a-ac21-5bf56d8f7f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619089853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3619089853
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.972426281
Short name T851
Test name
Test status
Simulation time 12360099 ps
CPU time 0.75 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 205792 kb
Host smart-32bd73d1-7aa2-4748-bd70-7ec4f674fc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972426281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.972426281
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3370555421
Short name T253
Test name
Test status
Simulation time 97276310 ps
CPU time 2.32 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:41 PM PDT 24
Peak memory 225512 kb
Host smart-9155f3ca-7c03-4b53-8c8e-38910b2bd8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370555421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3370555421
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.787834806
Short name T719
Test name
Test status
Simulation time 20971628 ps
CPU time 0.8 seconds
Started Jul 10 05:45:25 PM PDT 24
Finished Jul 10 05:45:26 PM PDT 24
Peak memory 207520 kb
Host smart-f468f430-8068-4289-9430-cd43ff68f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787834806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.787834806
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2686969659
Short name T975
Test name
Test status
Simulation time 74008146509 ps
CPU time 164.14 seconds
Started Jul 10 05:45:36 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 252612 kb
Host smart-25543fc8-02d1-4772-a064-24969bc300fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686969659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2686969659
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.284520020
Short name T56
Test name
Test status
Simulation time 189654065331 ps
CPU time 205.86 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 250288 kb
Host smart-9a7897b7-4a07-42a0-ba6c-6ae316a41e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284520020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.284520020
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3427261692
Short name T939
Test name
Test status
Simulation time 154772855276 ps
CPU time 402.24 seconds
Started Jul 10 05:45:36 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 274588 kb
Host smart-d42c8be1-aa28-4c09-805e-b61b0ad18aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427261692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3427261692
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2095914052
Short name T319
Test name
Test status
Simulation time 10359608798 ps
CPU time 41.69 seconds
Started Jul 10 05:45:36 PM PDT 24
Finished Jul 10 05:46:19 PM PDT 24
Peak memory 240608 kb
Host smart-9457c364-3bce-4d91-8932-b01c9bc922d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095914052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2095914052
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1266798995
Short name T162
Test name
Test status
Simulation time 6097775061 ps
CPU time 24.77 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 250300 kb
Host smart-77c467f7-ca79-4bbd-9180-b2c36d3ba2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266798995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1266798995
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.765161579
Short name T984
Test name
Test status
Simulation time 429928862 ps
CPU time 6.13 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:45 PM PDT 24
Peak memory 225556 kb
Host smart-edf71e6d-801a-445e-ac35-996f2ff8afbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765161579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.765161579
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1791452455
Short name T81
Test name
Test status
Simulation time 383184349 ps
CPU time 6.56 seconds
Started Jul 10 05:45:36 PM PDT 24
Finished Jul 10 05:45:43 PM PDT 24
Peak memory 241668 kb
Host smart-96d37f53-2954-4380-b371-fd4b3b92c4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791452455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1791452455
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2504718638
Short name T394
Test name
Test status
Simulation time 4226302460 ps
CPU time 14.27 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:53 PM PDT 24
Peak memory 233844 kb
Host smart-ddf27d0f-fd27-42aa-8673-ba4f71d6846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504718638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2504718638
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2544738474
Short name T695
Test name
Test status
Simulation time 642811367 ps
CPU time 3.96 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:42 PM PDT 24
Peak memory 233724 kb
Host smart-1a3b183e-dcc6-487d-b801-6695ba0d918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544738474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2544738474
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.936459622
Short name T745
Test name
Test status
Simulation time 178428367 ps
CPU time 5.03 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:44 PM PDT 24
Peak memory 223792 kb
Host smart-4cb6639e-6bfe-4404-8b20-e270856a5aec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=936459622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.936459622
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2492410413
Short name T957
Test name
Test status
Simulation time 54633440 ps
CPU time 0.96 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:39 PM PDT 24
Peak memory 208532 kb
Host smart-734b9ff6-0c53-4713-ae38-c0636b15bbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492410413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2492410413
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2828883250
Short name T309
Test name
Test status
Simulation time 1013794741 ps
CPU time 10.3 seconds
Started Jul 10 05:45:26 PM PDT 24
Finished Jul 10 05:45:37 PM PDT 24
Peak memory 219884 kb
Host smart-bfab8370-6531-4c0f-8d82-042e84a4f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828883250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2828883250
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1296445339
Short name T511
Test name
Test status
Simulation time 3804340946 ps
CPU time 1.5 seconds
Started Jul 10 05:45:26 PM PDT 24
Finished Jul 10 05:45:28 PM PDT 24
Peak memory 208752 kb
Host smart-f81641ee-e23e-46a6-a2e4-b94f963c2b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296445339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1296445339
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2088992908
Short name T872
Test name
Test status
Simulation time 12150502 ps
CPU time 0.74 seconds
Started Jul 10 05:45:27 PM PDT 24
Finished Jul 10 05:45:28 PM PDT 24
Peak memory 207164 kb
Host smart-cc5ae002-f815-4611-8a32-526ba6cb2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088992908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2088992908
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1242131358
Short name T887
Test name
Test status
Simulation time 37471308 ps
CPU time 0.79 seconds
Started Jul 10 05:45:27 PM PDT 24
Finished Jul 10 05:45:29 PM PDT 24
Peak memory 206948 kb
Host smart-efbd9318-c8b7-4769-9e56-8d56d58f17d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242131358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1242131358
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.113587736
Short name T441
Test name
Test status
Simulation time 2719907073 ps
CPU time 13.88 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:52 PM PDT 24
Peak memory 233868 kb
Host smart-56fde2aa-89f9-4d3d-8b4e-f51e4c36c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113587736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.113587736
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2294698325
Short name T408
Test name
Test status
Simulation time 146712694 ps
CPU time 0.77 seconds
Started Jul 10 05:45:42 PM PDT 24
Finished Jul 10 05:45:43 PM PDT 24
Peak memory 205800 kb
Host smart-93f396c0-d935-42dc-b521-a387b77b0d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294698325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2294698325
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3086978822
Short name T341
Test name
Test status
Simulation time 31361203 ps
CPU time 2.24 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:45:47 PM PDT 24
Peak memory 233480 kb
Host smart-71f972ec-e8c7-46ad-89f6-0cabf93382f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086978822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3086978822
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.450302616
Short name T711
Test name
Test status
Simulation time 44123602 ps
CPU time 0.8 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:39 PM PDT 24
Peak memory 207504 kb
Host smart-268425cb-b3e4-4726-ba16-c2b0511ed599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450302616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.450302616
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.148044352
Short name T837
Test name
Test status
Simulation time 24136219974 ps
CPU time 65.22 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:46:49 PM PDT 24
Peak memory 250268 kb
Host smart-c3464f25-4003-4ffc-adfe-27024309b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148044352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.148044352
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.117303451
Short name T1004
Test name
Test status
Simulation time 2744172255 ps
CPU time 36.98 seconds
Started Jul 10 05:45:42 PM PDT 24
Finished Jul 10 05:46:20 PM PDT 24
Peak memory 237644 kb
Host smart-4d7f2a60-aae8-442e-8c53-03a7f905581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117303451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.117303451
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4258167426
Short name T400
Test name
Test status
Simulation time 338936739 ps
CPU time 5.05 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:51 PM PDT 24
Peak memory 225524 kb
Host smart-9de4761f-a1e8-4435-a98e-ac9e3135b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258167426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4258167426
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1279830909
Short name T155
Test name
Test status
Simulation time 9808038014 ps
CPU time 34.23 seconds
Started Jul 10 05:45:45 PM PDT 24
Finished Jul 10 05:46:21 PM PDT 24
Peak memory 251996 kb
Host smart-915acbb2-4e33-409d-9a97-ea76584ecd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279830909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1279830909
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2394859650
Short name T481
Test name
Test status
Simulation time 850603465 ps
CPU time 3.26 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:49 PM PDT 24
Peak memory 228888 kb
Host smart-e5c2d338-0592-4b09-a356-dea805f74530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394859650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2394859650
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4088725874
Short name T337
Test name
Test status
Simulation time 1905271158 ps
CPU time 16.45 seconds
Started Jul 10 05:45:46 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 240996 kb
Host smart-b7084fa4-460c-45ba-9687-acea5ae84e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088725874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4088725874
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1536994014
Short name T810
Test name
Test status
Simulation time 16002367954 ps
CPU time 12.38 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:45:57 PM PDT 24
Peak memory 225644 kb
Host smart-4f67435b-d835-44c2-a789-aaeb70685197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536994014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1536994014
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2637150452
Short name T691
Test name
Test status
Simulation time 9510909551 ps
CPU time 13.22 seconds
Started Jul 10 05:45:38 PM PDT 24
Finished Jul 10 05:45:52 PM PDT 24
Peak memory 225688 kb
Host smart-2a8fb57f-8cd9-4916-825b-9af9ca74a62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637150452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2637150452
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.443890306
Short name T357
Test name
Test status
Simulation time 386047090 ps
CPU time 4.31 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:49 PM PDT 24
Peak memory 223540 kb
Host smart-9fa42ae9-0847-4388-9405-1ec297c8e67f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=443890306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.443890306
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1450705205
Short name T146
Test name
Test status
Simulation time 51353499 ps
CPU time 1 seconds
Started Jul 10 05:45:46 PM PDT 24
Finished Jul 10 05:45:48 PM PDT 24
Peak memory 207768 kb
Host smart-f8edae84-b4bf-4166-ad12-9a125f260717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450705205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1450705205
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2772275360
Short name T306
Test name
Test status
Simulation time 10282253156 ps
CPU time 23.51 seconds
Started Jul 10 05:45:40 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 221164 kb
Host smart-d772d4ca-6f39-49c0-9db1-8fc4f65f5078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772275360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2772275360
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2117166652
Short name T937
Test name
Test status
Simulation time 1061923555 ps
CPU time 2.34 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:40 PM PDT 24
Peak memory 217156 kb
Host smart-75784f28-8859-48cb-8a51-9f1619ff3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117166652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2117166652
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3133359919
Short name T340
Test name
Test status
Simulation time 85780755 ps
CPU time 0.83 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:39 PM PDT 24
Peak memory 206952 kb
Host smart-bffa2a6b-45af-48d3-a4e2-0e749c45b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133359919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3133359919
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3807050938
Short name T533
Test name
Test status
Simulation time 104785548 ps
CPU time 0.9 seconds
Started Jul 10 05:45:37 PM PDT 24
Finished Jul 10 05:45:39 PM PDT 24
Peak memory 207984 kb
Host smart-ae05b438-3afd-4c97-ac40-d06550f5d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807050938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3807050938
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.651979112
Short name T392
Test name
Test status
Simulation time 17986501124 ps
CPU time 23.17 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:46:08 PM PDT 24
Peak memory 238232 kb
Host smart-da19fb10-dfe6-4f09-89c7-60b732da5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651979112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.651979112
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1081711405
Short name T641
Test name
Test status
Simulation time 16668959 ps
CPU time 0.73 seconds
Started Jul 10 05:45:51 PM PDT 24
Finished Jul 10 05:45:53 PM PDT 24
Peak memory 206356 kb
Host smart-a009d485-5976-47e6-9630-1139e060820e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081711405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1081711405
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1405430838
Short name T573
Test name
Test status
Simulation time 76256841 ps
CPU time 2.98 seconds
Started Jul 10 05:45:45 PM PDT 24
Finished Jul 10 05:45:50 PM PDT 24
Peak memory 225552 kb
Host smart-fc1c34c7-2258-470b-9513-96f2a92b442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405430838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1405430838
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1602191163
Short name T1009
Test name
Test status
Simulation time 15822905 ps
CPU time 0.76 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:45:44 PM PDT 24
Peak memory 206492 kb
Host smart-d56625c8-01d4-46e9-8d83-0373334dede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602191163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1602191163
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3326328917
Short name T544
Test name
Test status
Simulation time 14013386866 ps
CPU time 53.69 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:46:39 PM PDT 24
Peak memory 250264 kb
Host smart-885ae281-8da5-4902-b480-0815d6012169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326328917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3326328917
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.404888515
Short name T935
Test name
Test status
Simulation time 4275201974 ps
CPU time 88.97 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 255668 kb
Host smart-768e8705-588f-40b8-beeb-eb57b9bb78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404888515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.404888515
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3103612890
Short name T927
Test name
Test status
Simulation time 123078407861 ps
CPU time 272.28 seconds
Started Jul 10 05:45:49 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 252760 kb
Host smart-af2f4519-73f3-4cca-b193-7e9f16d5219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103612890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3103612890
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3139554319
Short name T215
Test name
Test status
Simulation time 5925342619 ps
CPU time 33.71 seconds
Started Jul 10 05:45:43 PM PDT 24
Finished Jul 10 05:46:17 PM PDT 24
Peak memory 242224 kb
Host smart-d0a8b6be-bc72-4082-9364-568b0ad5e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139554319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3139554319
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1186901558
Short name T496
Test name
Test status
Simulation time 1230608026 ps
CPU time 5.84 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:51 PM PDT 24
Peak memory 233696 kb
Host smart-4f4de410-89ee-418d-b1a6-94b0857668bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186901558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1186901558
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1520145131
Short name T1007
Test name
Test status
Simulation time 5499324122 ps
CPU time 51.58 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:46:37 PM PDT 24
Peak memory 233868 kb
Host smart-362f552f-a546-495b-887b-960726f09af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520145131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1520145131
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1966851004
Short name T343
Test name
Test status
Simulation time 731362815 ps
CPU time 2.92 seconds
Started Jul 10 05:45:41 PM PDT 24
Finished Jul 10 05:45:45 PM PDT 24
Peak memory 225488 kb
Host smart-fe913b97-f442-4d04-9c0f-4682ef23d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966851004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1966851004
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1609409640
Short name T962
Test name
Test status
Simulation time 488025078 ps
CPU time 3.82 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:50 PM PDT 24
Peak memory 225608 kb
Host smart-6088fff2-971c-4317-b42f-01d8ecec27c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609409640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1609409640
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2335670172
Short name T464
Test name
Test status
Simulation time 3322844373 ps
CPU time 7.21 seconds
Started Jul 10 05:45:45 PM PDT 24
Finished Jul 10 05:45:53 PM PDT 24
Peak memory 223740 kb
Host smart-8d730f85-e73e-476d-8c2c-a1a7c10f345c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335670172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2335670172
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2020714013
Short name T774
Test name
Test status
Simulation time 89655740 ps
CPU time 1 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:45:59 PM PDT 24
Peak memory 208700 kb
Host smart-9f54c6db-dd88-4b89-835d-e8a6515d1d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020714013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2020714013
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4042918471
Short name T645
Test name
Test status
Simulation time 3810754484 ps
CPU time 18.03 seconds
Started Jul 10 05:45:45 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 217748 kb
Host smart-30c03401-2da0-407a-a018-e89182c65107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042918471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4042918471
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1092301929
Short name T316
Test name
Test status
Simulation time 4462023018 ps
CPU time 12.41 seconds
Started Jul 10 05:45:45 PM PDT 24
Finished Jul 10 05:45:59 PM PDT 24
Peak memory 217340 kb
Host smart-b2d5fdaa-e6c1-4d15-aacc-dc76826fe8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092301929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1092301929
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.515760968
Short name T610
Test name
Test status
Simulation time 382726830 ps
CPU time 2.18 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:47 PM PDT 24
Peak memory 217328 kb
Host smart-19b3ec49-8547-42a4-9f96-22631cd989c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515760968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.515760968
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2270494424
Short name T555
Test name
Test status
Simulation time 19257037 ps
CPU time 0.75 seconds
Started Jul 10 05:45:46 PM PDT 24
Finished Jul 10 05:45:48 PM PDT 24
Peak memory 206960 kb
Host smart-2c954658-5478-4b0f-b58c-eb376a69ba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270494424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2270494424
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2341661527
Short name T665
Test name
Test status
Simulation time 439925073 ps
CPU time 3.49 seconds
Started Jul 10 05:45:44 PM PDT 24
Finished Jul 10 05:45:48 PM PDT 24
Peak memory 225504 kb
Host smart-6f204eef-d086-4c0a-a4c0-cd3514c3bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341661527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2341661527
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.453233891
Short name T414
Test name
Test status
Simulation time 14622411 ps
CPU time 0.8 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:45:59 PM PDT 24
Peak memory 205740 kb
Host smart-369fd682-a152-4e45-92d5-0e30e112897a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453233891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.453233891
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2376391122
Short name T841
Test name
Test status
Simulation time 153200782 ps
CPU time 2.51 seconds
Started Jul 10 05:45:52 PM PDT 24
Finished Jul 10 05:45:55 PM PDT 24
Peak memory 225564 kb
Host smart-0d9aad49-f92d-4d29-8cdf-00999b409d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376391122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2376391122
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1339837955
Short name T512
Test name
Test status
Simulation time 61148726 ps
CPU time 0.78 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:45:58 PM PDT 24
Peak memory 207488 kb
Host smart-ddf0b068-67fd-424c-a47f-e7bc108a45a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339837955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1339837955
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2022274104
Short name T404
Test name
Test status
Simulation time 3520136997 ps
CPU time 32.14 seconds
Started Jul 10 05:45:48 PM PDT 24
Finished Jul 10 05:46:22 PM PDT 24
Peak memory 242336 kb
Host smart-391040b8-75c9-4b48-aa31-444aeee3b910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022274104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2022274104
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2581115082
Short name T192
Test name
Test status
Simulation time 27004984182 ps
CPU time 240.27 seconds
Started Jul 10 05:45:50 PM PDT 24
Finished Jul 10 05:49:52 PM PDT 24
Peak memory 266740 kb
Host smart-ef4bb08a-52f7-495e-85b1-e325a4bf1679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581115082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2581115082
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2287260599
Short name T920
Test name
Test status
Simulation time 10655981375 ps
CPU time 53.41 seconds
Started Jul 10 05:45:51 PM PDT 24
Finished Jul 10 05:46:45 PM PDT 24
Peak memory 250392 kb
Host smart-7ee969bb-8cb4-43aa-bba2-53b51aac9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287260599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2287260599
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.866671059
Short name T505
Test name
Test status
Simulation time 6981853171 ps
CPU time 28.52 seconds
Started Jul 10 05:45:49 PM PDT 24
Finished Jul 10 05:46:19 PM PDT 24
Peak memory 233892 kb
Host smart-70d12627-4b94-4c95-b78b-eaa9861c7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866671059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.866671059
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3519075192
Short name T601
Test name
Test status
Simulation time 4772673317 ps
CPU time 20.36 seconds
Started Jul 10 05:45:51 PM PDT 24
Finished Jul 10 05:46:12 PM PDT 24
Peak memory 250300 kb
Host smart-cf0c6888-e434-4869-aa0e-a65668b821f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519075192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3519075192
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3272404892
Short name T185
Test name
Test status
Simulation time 1305056140 ps
CPU time 11.78 seconds
Started Jul 10 05:45:50 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 233748 kb
Host smart-ebc900eb-5fd3-4481-a111-72852641c2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272404892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3272404892
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2224938069
Short name T375
Test name
Test status
Simulation time 3687656688 ps
CPU time 17.65 seconds
Started Jul 10 05:45:50 PM PDT 24
Finished Jul 10 05:46:09 PM PDT 24
Peak memory 233828 kb
Host smart-72e6bde9-e5c3-4936-b79a-9cd0b6336333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224938069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2224938069
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3933672630
Short name T264
Test name
Test status
Simulation time 55241428586 ps
CPU time 18.3 seconds
Started Jul 10 05:45:51 PM PDT 24
Finished Jul 10 05:46:11 PM PDT 24
Peak memory 233840 kb
Host smart-922b43b0-7c56-4a4b-9359-e1030fb8b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933672630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3933672630
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3466007757
Short name T254
Test name
Test status
Simulation time 2930900861 ps
CPU time 4.52 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 225644 kb
Host smart-2f6e313e-692b-435a-bc9f-8acf4a917b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466007757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3466007757
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.92517107
Short name T497
Test name
Test status
Simulation time 127023567 ps
CPU time 3.79 seconds
Started Jul 10 05:45:52 PM PDT 24
Finished Jul 10 05:45:57 PM PDT 24
Peak memory 223616 kb
Host smart-e073e717-c717-44bc-b5c2-4bb39602e2c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=92517107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direc
t.92517107
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.488214391
Short name T147
Test name
Test status
Simulation time 181647425 ps
CPU time 1.02 seconds
Started Jul 10 05:45:49 PM PDT 24
Finished Jul 10 05:45:52 PM PDT 24
Peak memory 207892 kb
Host smart-a8b5095a-8cdc-4cba-8ba2-013fa7d002cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488214391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.488214391
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2755301700
Short name T529
Test name
Test status
Simulation time 3165340937 ps
CPU time 38.56 seconds
Started Jul 10 05:45:51 PM PDT 24
Finished Jul 10 05:46:31 PM PDT 24
Peak memory 217432 kb
Host smart-4733a27a-4c4d-48b7-8aab-bd8656e0e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755301700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2755301700
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3912129765
Short name T320
Test name
Test status
Simulation time 340227415 ps
CPU time 1.59 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:45:59 PM PDT 24
Peak memory 208904 kb
Host smart-9f9092ca-1b1c-46dc-b292-1deab22286ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912129765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3912129765
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3947615728
Short name T760
Test name
Test status
Simulation time 272946036 ps
CPU time 1.73 seconds
Started Jul 10 05:45:50 PM PDT 24
Finished Jul 10 05:45:54 PM PDT 24
Peak memory 217324 kb
Host smart-9ed09469-e6c0-4a30-ac4b-63618a9ecf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947615728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3947615728
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1348945092
Short name T749
Test name
Test status
Simulation time 35123383 ps
CPU time 0.78 seconds
Started Jul 10 05:45:49 PM PDT 24
Finished Jul 10 05:45:52 PM PDT 24
Peak memory 206860 kb
Host smart-2dfb9211-b0b7-49fc-bb88-40e31fae708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348945092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1348945092
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1860387853
Short name T427
Test name
Test status
Simulation time 101465023 ps
CPU time 2.14 seconds
Started Jul 10 05:45:52 PM PDT 24
Finished Jul 10 05:45:55 PM PDT 24
Peak memory 225496 kb
Host smart-40c494de-74c6-409e-9e2f-bffd929f4b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860387853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1860387853
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3349950566
Short name T510
Test name
Test status
Simulation time 41683611 ps
CPU time 0.72 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:46:00 PM PDT 24
Peak memory 205780 kb
Host smart-f87a2757-f47c-4ee7-8f5d-fc82e3b7222a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349950566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3349950566
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.200031560
Short name T595
Test name
Test status
Simulation time 3054933484 ps
CPU time 23.94 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:46:24 PM PDT 24
Peak memory 233924 kb
Host smart-96d7acbe-a897-4b8b-a444-7c8779e5583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200031560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.200031560
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.408179975
Short name T729
Test name
Test status
Simulation time 54082687 ps
CPU time 0.81 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:46:01 PM PDT 24
Peak memory 207528 kb
Host smart-7cfaeb52-53d3-4ed9-a250-9c650cdff579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408179975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.408179975
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2322146400
Short name T982
Test name
Test status
Simulation time 51828732164 ps
CPU time 71.05 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:47:10 PM PDT 24
Peak memory 223968 kb
Host smart-7bf215c1-f807-42ce-8601-7ed819e2777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322146400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2322146400
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4012124970
Short name T663
Test name
Test status
Simulation time 17111761856 ps
CPU time 178.25 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:48:57 PM PDT 24
Peak memory 257792 kb
Host smart-fcfc97c5-0eaa-4036-8628-39a3701dd091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012124970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4012124970
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.233674510
Short name T682
Test name
Test status
Simulation time 25768407014 ps
CPU time 37.91 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:46:36 PM PDT 24
Peak memory 233820 kb
Host smart-1e1060fb-3b7d-4158-9549-ecf0d2860910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233674510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.233674510
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1834510884
Short name T755
Test name
Test status
Simulation time 904047634 ps
CPU time 4.67 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 225468 kb
Host smart-2ec63a86-90b1-49a2-8f87-633da0f2211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834510884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1834510884
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.812222740
Short name T44
Test name
Test status
Simulation time 43276712614 ps
CPU time 128.39 seconds
Started Jul 10 05:46:01 PM PDT 24
Finished Jul 10 05:48:10 PM PDT 24
Peak memory 233884 kb
Host smart-f53f0c0f-49be-4fac-b392-793641ad7707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812222740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.812222740
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.113249315
Short name T244
Test name
Test status
Simulation time 4197978951 ps
CPU time 14.57 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:16 PM PDT 24
Peak memory 233888 kb
Host smart-a8f9cc4b-82d8-4535-8205-e4aa0003baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113249315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.113249315
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3060642753
Short name T627
Test name
Test status
Simulation time 659464249 ps
CPU time 8.22 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:46:08 PM PDT 24
Peak memory 233760 kb
Host smart-06035716-2f0b-4830-b213-5d033db78f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060642753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3060642753
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.696741366
Short name T752
Test name
Test status
Simulation time 262008437 ps
CPU time 6.03 seconds
Started Jul 10 05:45:57 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 221552 kb
Host smart-561e34a7-1c8e-4eac-a6df-b1ed2f4cf6a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696741366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.696741366
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3361754848
Short name T149
Test name
Test status
Simulation time 31215259329 ps
CPU time 84.86 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:47:26 PM PDT 24
Peak memory 250416 kb
Host smart-d0d70fc6-8530-42dc-a97f-babf237994c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361754848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3361754848
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.673697817
Short name T307
Test name
Test status
Simulation time 15913749621 ps
CPU time 40.5 seconds
Started Jul 10 05:45:58 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 217456 kb
Host smart-5778f07d-a6ad-4eb1-ba5e-d69b382d64b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673697817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.673697817
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4095847297
Short name T499
Test name
Test status
Simulation time 1512285176 ps
CPU time 2.49 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 217348 kb
Host smart-4822f1e2-0a39-4e20-80d8-583be2c9dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095847297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4095847297
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1877690377
Short name T615
Test name
Test status
Simulation time 515656493 ps
CPU time 6.59 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:46:07 PM PDT 24
Peak memory 217320 kb
Host smart-1398c416-e3f9-4a41-8b8b-d6a333c7797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877690377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1877690377
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1973226181
Short name T425
Test name
Test status
Simulation time 60144898 ps
CPU time 0.82 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:46:01 PM PDT 24
Peak memory 206948 kb
Host smart-786e8e0a-b387-4bab-871e-52e9824a645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973226181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1973226181
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.89993302
Short name T890
Test name
Test status
Simulation time 533197300 ps
CPU time 2.52 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:03 PM PDT 24
Peak memory 224924 kb
Host smart-d1a4a201-cf78-482a-81ce-613093608bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89993302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.89993302
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3741707263
Short name T907
Test name
Test status
Simulation time 14723612 ps
CPU time 0.73 seconds
Started Jul 10 05:46:09 PM PDT 24
Finished Jul 10 05:46:11 PM PDT 24
Peak memory 205628 kb
Host smart-177fe68e-3d9f-4cce-b1dc-8f6fbd3e72a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741707263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3741707263
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2458199256
Short name T506
Test name
Test status
Simulation time 5656852339 ps
CPU time 17.99 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:46:25 PM PDT 24
Peak memory 225664 kb
Host smart-cdf94cbf-861d-4112-b92a-53db4ee9ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458199256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2458199256
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.444999657
Short name T318
Test name
Test status
Simulation time 50934149 ps
CPU time 0.84 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:02 PM PDT 24
Peak memory 207484 kb
Host smart-3b91aae8-04b4-4bde-96ee-046977467b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444999657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.444999657
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.170164273
Short name T272
Test name
Test status
Simulation time 154174348583 ps
CPU time 309.28 seconds
Started Jul 10 05:46:09 PM PDT 24
Finished Jul 10 05:51:19 PM PDT 24
Peak memory 266420 kb
Host smart-4947364e-0f71-40cd-b473-216cad2135d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170164273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.170164273
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3179411168
Short name T913
Test name
Test status
Simulation time 56140323908 ps
CPU time 210.57 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 255060 kb
Host smart-c3bc7cc3-5b52-45ed-81c3-ec560cffee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179411168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3179411168
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1665095833
Short name T1010
Test name
Test status
Simulation time 11553270584 ps
CPU time 38.92 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:47 PM PDT 24
Peak memory 225720 kb
Host smart-2f93d2c3-e239-4d14-a1bd-bbed5031c493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665095833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1665095833
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.414182543
Short name T605
Test name
Test status
Simulation time 56888517 ps
CPU time 1 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:10 PM PDT 24
Peak memory 217160 kb
Host smart-8a68632f-03f3-45d1-9f98-97edab3566f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414182543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.414182543
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3288422498
Short name T883
Test name
Test status
Simulation time 18293794825 ps
CPU time 28.39 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:46:36 PM PDT 24
Peak memory 233904 kb
Host smart-af70e662-4f03-4e57-bdda-c23cf50cf716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288422498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3288422498
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3895611910
Short name T540
Test name
Test status
Simulation time 989518453 ps
CPU time 10.06 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:16 PM PDT 24
Peak memory 225464 kb
Host smart-c6905e87-ea36-4701-ae03-581c854c6df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895611910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3895611910
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1209181043
Short name T553
Test name
Test status
Simulation time 57872459 ps
CPU time 2.61 seconds
Started Jul 10 05:46:09 PM PDT 24
Finished Jul 10 05:46:13 PM PDT 24
Peak memory 233296 kb
Host smart-50e3c433-c838-4520-893b-8a2671955c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209181043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1209181043
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2292967039
Short name T11
Test name
Test status
Simulation time 7034799384 ps
CPU time 11.12 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:17 PM PDT 24
Peak memory 233836 kb
Host smart-eb17d4c4-cffd-4e31-8f29-60e91bb8f7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292967039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2292967039
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1405577055
Short name T801
Test name
Test status
Simulation time 1491429749 ps
CPU time 10.46 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:46:19 PM PDT 24
Peak memory 222936 kb
Host smart-6ba59db4-47d6-4c61-803c-be490b3565bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405577055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1405577055
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3882816749
Short name T15
Test name
Test status
Simulation time 63408969 ps
CPU time 1.08 seconds
Started Jul 10 05:46:09 PM PDT 24
Finished Jul 10 05:46:11 PM PDT 24
Peak memory 208080 kb
Host smart-741a7553-e46c-4ba2-a28e-ae1373bab5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882816749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3882816749
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2827396139
Short name T28
Test name
Test status
Simulation time 7902608247 ps
CPU time 38.74 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 221520 kb
Host smart-4dbe0514-7212-4b11-a61f-1617dead6fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827396139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2827396139
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2988391678
Short name T528
Test name
Test status
Simulation time 1131606325 ps
CPU time 2.5 seconds
Started Jul 10 05:46:00 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 208928 kb
Host smart-40bd7364-5ce9-44ff-803c-8acc32c77a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988391678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2988391678
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1726936983
Short name T877
Test name
Test status
Simulation time 26928033 ps
CPU time 0.75 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:07 PM PDT 24
Peak memory 206952 kb
Host smart-1398d028-3d5e-414e-9801-6dcae0c3dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726936983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1726936983
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3133323168
Short name T346
Test name
Test status
Simulation time 31897927 ps
CPU time 0.82 seconds
Started Jul 10 05:45:59 PM PDT 24
Finished Jul 10 05:46:01 PM PDT 24
Peak memory 206868 kb
Host smart-0ae1b25f-acb7-4321-81f3-2c62852623de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133323168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3133323168
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2330493782
Short name T796
Test name
Test status
Simulation time 16767077235 ps
CPU time 25.76 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 237340 kb
Host smart-6d256464-35a8-46aa-b1cb-2721ef4e0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330493782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2330493782
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1917686605
Short name T581
Test name
Test status
Simulation time 11604897 ps
CPU time 0.7 seconds
Started Jul 10 05:46:03 PM PDT 24
Finished Jul 10 05:46:04 PM PDT 24
Peak memory 206280 kb
Host smart-c9d843d3-da11-4ff6-a832-199fb32b3732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917686605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1917686605
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3153481353
Short name T642
Test name
Test status
Simulation time 164448943 ps
CPU time 2.66 seconds
Started Jul 10 05:46:08 PM PDT 24
Finished Jul 10 05:46:12 PM PDT 24
Peak memory 225624 kb
Host smart-573561c3-657a-4426-9a45-8b3f8d877afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153481353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3153481353
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4168697139
Short name T820
Test name
Test status
Simulation time 38426392 ps
CPU time 0.76 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:10 PM PDT 24
Peak memory 207488 kb
Host smart-9ef2ccfb-61a0-4e0c-b5b3-833c89cf5ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168697139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4168697139
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1506616963
Short name T166
Test name
Test status
Simulation time 300808589697 ps
CPU time 481.52 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:54:09 PM PDT 24
Peak memory 266656 kb
Host smart-4e3a71d4-28a0-413b-b969-e76dd4702e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506616963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1506616963
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3595490418
Short name T190
Test name
Test status
Simulation time 12609040665 ps
CPU time 105.76 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:47:55 PM PDT 24
Peak memory 250328 kb
Host smart-2843c052-7570-4618-84cc-5f903e540fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595490418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3595490418
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2214355673
Short name T204
Test name
Test status
Simulation time 7234106160 ps
CPU time 57.33 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 250420 kb
Host smart-1969baf9-0473-4227-b06d-9c636b99956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214355673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2214355673
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.489044063
Short name T389
Test name
Test status
Simulation time 416816537 ps
CPU time 9.04 seconds
Started Jul 10 05:46:04 PM PDT 24
Finished Jul 10 05:46:14 PM PDT 24
Peak memory 233732 kb
Host smart-c25095e8-2f77-43cc-8158-4b07863e5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489044063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.489044063
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3543699170
Short name T753
Test name
Test status
Simulation time 31109791821 ps
CPU time 267.2 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 258456 kb
Host smart-6a4be662-91bc-4d1f-a783-0ec07a675130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543699170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3543699170
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.798873371
Short name T374
Test name
Test status
Simulation time 1158267230 ps
CPU time 5.91 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:15 PM PDT 24
Peak memory 233668 kb
Host smart-99725c34-f47f-4c97-8dde-447429517e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798873371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.798873371
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4236936099
Short name T963
Test name
Test status
Simulation time 8340801135 ps
CPU time 45.39 seconds
Started Jul 10 05:46:04 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 241868 kb
Host smart-aefb0ed3-99d0-4dd3-9e74-71643cf9bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236936099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4236936099
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2078885338
Short name T830
Test name
Test status
Simulation time 383582255 ps
CPU time 5.57 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:11 PM PDT 24
Peak memory 233720 kb
Host smart-4b035629-34f7-4c12-9887-f70f0908a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078885338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2078885338
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.900841985
Short name T672
Test name
Test status
Simulation time 1021146683 ps
CPU time 3.37 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:09 PM PDT 24
Peak memory 233736 kb
Host smart-14dc3ce3-42a7-4d20-861d-853f91b456f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900841985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.900841985
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.554618049
Short name T468
Test name
Test status
Simulation time 134999403 ps
CPU time 3.9 seconds
Started Jul 10 05:46:08 PM PDT 24
Finished Jul 10 05:46:13 PM PDT 24
Peak memory 224112 kb
Host smart-b14f747f-6299-40e2-a1e6-c25aa518b729
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=554618049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.554618049
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1284780947
Short name T458
Test name
Test status
Simulation time 137218998703 ps
CPU time 167.51 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:48:54 PM PDT 24
Peak memory 251344 kb
Host smart-6a632fc4-cfe7-4e07-a0a0-25c9f4cf80f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284780947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1284780947
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3404039320
Short name T847
Test name
Test status
Simulation time 1008704873 ps
CPU time 6.89 seconds
Started Jul 10 05:46:03 PM PDT 24
Finished Jul 10 05:46:11 PM PDT 24
Peak memory 220100 kb
Host smart-a8942aba-983e-4118-a08b-261146dabb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404039320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3404039320
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2953822282
Short name T616
Test name
Test status
Simulation time 1842065139 ps
CPU time 6.63 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:46:14 PM PDT 24
Peak memory 217288 kb
Host smart-93bec971-6c51-4bb1-b510-a7e42b0974cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953822282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2953822282
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3612171892
Short name T465
Test name
Test status
Simulation time 84551600 ps
CPU time 0.92 seconds
Started Jul 10 05:46:06 PM PDT 24
Finished Jul 10 05:46:08 PM PDT 24
Peak memory 207764 kb
Host smart-35a41798-e9e2-4c78-90f2-f327444e66de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612171892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3612171892
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.491593962
Short name T579
Test name
Test status
Simulation time 133124767 ps
CPU time 0.7 seconds
Started Jul 10 05:46:04 PM PDT 24
Finished Jul 10 05:46:05 PM PDT 24
Peak memory 206540 kb
Host smart-86548e32-5060-48dc-93bd-9a19ad34ad05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491593962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.491593962
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2614995578
Short name T848
Test name
Test status
Simulation time 42483270 ps
CPU time 2.43 seconds
Started Jul 10 05:46:04 PM PDT 24
Finished Jul 10 05:46:07 PM PDT 24
Peak memory 225520 kb
Host smart-9fd9503e-9a11-49e8-9474-26a4599fa469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614995578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2614995578
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3106192581
Short name T517
Test name
Test status
Simulation time 59081997 ps
CPU time 0.74 seconds
Started Jul 10 05:46:10 PM PDT 24
Finished Jul 10 05:46:12 PM PDT 24
Peak memory 205800 kb
Host smart-e55456bb-9e1c-4b59-ab3d-1babf86c9328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106192581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3106192581
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1948320555
Short name T410
Test name
Test status
Simulation time 206239229 ps
CPU time 3.25 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:46:16 PM PDT 24
Peak memory 225552 kb
Host smart-9f26e669-5add-47d7-948e-51263a7ba67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948320555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1948320555
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.175470089
Short name T335
Test name
Test status
Simulation time 29058666 ps
CPU time 0.76 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:07 PM PDT 24
Peak memory 206796 kb
Host smart-443d1ba7-6982-4c0b-bf72-66a259c1cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175470089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.175470089
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1455316243
Short name T199
Test name
Test status
Simulation time 28127831607 ps
CPU time 131.17 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:48:23 PM PDT 24
Peak memory 266816 kb
Host smart-0617fce8-9a17-41f9-946f-a7737a93e46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455316243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1455316243
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1121506516
Short name T611
Test name
Test status
Simulation time 14783373238 ps
CPU time 132.44 seconds
Started Jul 10 05:46:10 PM PDT 24
Finished Jul 10 05:48:24 PM PDT 24
Peak memory 252380 kb
Host smart-a8fef940-c135-462b-afd2-815122c4f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121506516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1121506516
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.114459548
Short name T574
Test name
Test status
Simulation time 852242857 ps
CPU time 7.32 seconds
Started Jul 10 05:46:14 PM PDT 24
Finished Jul 10 05:46:22 PM PDT 24
Peak memory 233768 kb
Host smart-69444981-1951-45af-a8e1-d8ba6e22aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114459548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.114459548
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2290386999
Short name T276
Test name
Test status
Simulation time 13367360737 ps
CPU time 26.99 seconds
Started Jul 10 05:46:13 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 236436 kb
Host smart-e81dba0e-9add-4a57-9658-208e08daf680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290386999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2290386999
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1108659215
Short name T189
Test name
Test status
Simulation time 6397134311 ps
CPU time 27.22 seconds
Started Jul 10 05:46:10 PM PDT 24
Finished Jul 10 05:46:39 PM PDT 24
Peak memory 225692 kb
Host smart-5ee2c748-6828-44eb-9794-4db2732aa137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108659215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1108659215
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.211907535
Short name T608
Test name
Test status
Simulation time 10642745945 ps
CPU time 21.99 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 233888 kb
Host smart-c355b718-7343-4dc2-9de6-308fe258bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211907535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.211907535
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3500282390
Short name T210
Test name
Test status
Simulation time 2191407657 ps
CPU time 4.99 seconds
Started Jul 10 05:46:09 PM PDT 24
Finished Jul 10 05:46:15 PM PDT 24
Peak memory 233848 kb
Host smart-c47df261-6280-448f-ab56-f5629800462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500282390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3500282390
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.505865874
Short name T217
Test name
Test status
Simulation time 23305332922 ps
CPU time 14.27 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:46:27 PM PDT 24
Peak memory 233808 kb
Host smart-f52db3b7-b364-4088-83d2-49097628b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505865874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.505865874
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1527813090
Short name T772
Test name
Test status
Simulation time 1516279417 ps
CPU time 9.15 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:46:22 PM PDT 24
Peak memory 222848 kb
Host smart-a10b07d9-26c6-461b-81a6-4a2f73e4ca2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1527813090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1527813090
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3270465987
Short name T618
Test name
Test status
Simulation time 831636126 ps
CPU time 6.71 seconds
Started Jul 10 05:46:05 PM PDT 24
Finished Jul 10 05:46:13 PM PDT 24
Peak memory 220296 kb
Host smart-0b95d5bf-090d-4dbe-acfb-97996cceb4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270465987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3270465987
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2323442826
Short name T438
Test name
Test status
Simulation time 20023835 ps
CPU time 0.73 seconds
Started Jul 10 05:46:07 PM PDT 24
Finished Jul 10 05:46:09 PM PDT 24
Peak memory 206620 kb
Host smart-5e176dac-5fc9-43e6-8812-0d0539053071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323442826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2323442826
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.427342055
Short name T969
Test name
Test status
Simulation time 170456989 ps
CPU time 1.4 seconds
Started Jul 10 05:46:12 PM PDT 24
Finished Jul 10 05:46:15 PM PDT 24
Peak memory 217360 kb
Host smart-ec6761f5-6a7c-4422-9bd7-40ef80ca1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427342055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.427342055
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2221342305
Short name T899
Test name
Test status
Simulation time 1049643548 ps
CPU time 0.93 seconds
Started Jul 10 05:46:11 PM PDT 24
Finished Jul 10 05:46:13 PM PDT 24
Peak memory 208004 kb
Host smart-2c2c9ef2-1a07-4f4b-abf2-e4ee085bb335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221342305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2221342305
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4258199740
Short name T632
Test name
Test status
Simulation time 185174378 ps
CPU time 2.56 seconds
Started Jul 10 05:46:12 PM PDT 24
Finished Jul 10 05:46:16 PM PDT 24
Peak memory 225188 kb
Host smart-33d006c1-fea7-4a45-a1ed-ff75a17c13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258199740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4258199740
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2473399086
Short name T751
Test name
Test status
Simulation time 13905160 ps
CPU time 0.8 seconds
Started Jul 10 05:46:18 PM PDT 24
Finished Jul 10 05:46:19 PM PDT 24
Peak memory 205816 kb
Host smart-1f24e554-b451-473d-96e5-9119373b8ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473399086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2473399086
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3420381912
Short name T724
Test name
Test status
Simulation time 428353467 ps
CPU time 4.42 seconds
Started Jul 10 05:46:19 PM PDT 24
Finished Jul 10 05:46:24 PM PDT 24
Peak memory 225552 kb
Host smart-4703c7b8-4655-4364-a905-0491c00bb5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420381912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3420381912
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3055294159
Short name T671
Test name
Test status
Simulation time 58423465 ps
CPU time 0.81 seconds
Started Jul 10 05:46:12 PM PDT 24
Finished Jul 10 05:46:14 PM PDT 24
Peak memory 207712 kb
Host smart-137525fc-bc58-4f87-96ec-ae2c0a236b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055294159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3055294159
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3822525966
Short name T1001
Test name
Test status
Simulation time 14723089663 ps
CPU time 53.61 seconds
Started Jul 10 05:46:19 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 256700 kb
Host smart-9abf430b-bd4c-4e0b-afe3-9c174719bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822525966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3822525966
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1204608952
Short name T644
Test name
Test status
Simulation time 54031917365 ps
CPU time 243.44 seconds
Started Jul 10 05:46:21 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 253024 kb
Host smart-31803a16-ecdd-4dd6-a536-3b9b22933b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204608952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1204608952
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3917526372
Short name T539
Test name
Test status
Simulation time 329924276 ps
CPU time 3.24 seconds
Started Jul 10 05:46:18 PM PDT 24
Finished Jul 10 05:46:23 PM PDT 24
Peak memory 224984 kb
Host smart-ddfaabe9-c5d5-48f8-97c5-4a63e2768300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917526372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3917526372
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1634955891
Short name T818
Test name
Test status
Simulation time 1910128418 ps
CPU time 18.45 seconds
Started Jul 10 05:46:18 PM PDT 24
Finished Jul 10 05:46:37 PM PDT 24
Peak memory 225524 kb
Host smart-8fe78c7b-d26a-4d22-84b0-3c5a2de7a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634955891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1634955891
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1138130714
Short name T895
Test name
Test status
Simulation time 6578588683 ps
CPU time 62.3 seconds
Started Jul 10 05:46:17 PM PDT 24
Finished Jul 10 05:47:20 PM PDT 24
Peak memory 250276 kb
Host smart-425d887e-c1bd-4795-89f7-3d559db0fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138130714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1138130714
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.640994146
Short name T734
Test name
Test status
Simulation time 85112876 ps
CPU time 3.18 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:31 PM PDT 24
Peak memory 229272 kb
Host smart-f073b640-497c-474a-942d-783ec489ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640994146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.640994146
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4244095605
Short name T195
Test name
Test status
Simulation time 7279915870 ps
CPU time 39.24 seconds
Started Jul 10 05:46:19 PM PDT 24
Finished Jul 10 05:46:59 PM PDT 24
Peak memory 234900 kb
Host smart-74e1a06b-99f0-4727-8659-3e4b96768635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244095605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4244095605
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2735433771
Short name T508
Test name
Test status
Simulation time 765753979 ps
CPU time 6.22 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 225512 kb
Host smart-146ae7af-39f0-4463-962b-ae0dd001467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735433771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2735433771
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1553147110
Short name T234
Test name
Test status
Simulation time 8234227804 ps
CPU time 8.49 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:35 PM PDT 24
Peak memory 225700 kb
Host smart-d7112a3a-02c8-4e59-ba56-fa4680704dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553147110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1553147110
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.705021463
Short name T136
Test name
Test status
Simulation time 2330699225 ps
CPU time 8.75 seconds
Started Jul 10 05:46:20 PM PDT 24
Finished Jul 10 05:46:29 PM PDT 24
Peak memory 222912 kb
Host smart-9746d020-50a0-4410-817f-83c586d8c07b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705021463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.705021463
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2936121167
Short name T52
Test name
Test status
Simulation time 3318927136 ps
CPU time 26.4 seconds
Started Jul 10 05:46:19 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 225728 kb
Host smart-e88f174d-363c-4545-b181-7c6a0053a3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936121167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2936121167
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2418811591
Short name T301
Test name
Test status
Simulation time 6766450790 ps
CPU time 20.82 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:47:02 PM PDT 24
Peak memory 221284 kb
Host smart-f30429ca-5c80-430b-b212-e685eacd4adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418811591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2418811591
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.645713090
Short name T442
Test name
Test status
Simulation time 6936691520 ps
CPU time 6.18 seconds
Started Jul 10 05:46:18 PM PDT 24
Finished Jul 10 05:46:25 PM PDT 24
Peak memory 217468 kb
Host smart-dfb4dce2-622a-4ecf-82e6-270b61a18803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645713090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.645713090
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2152907788
Short name T519
Test name
Test status
Simulation time 1274712718 ps
CPU time 3.12 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:30 PM PDT 24
Peak memory 217392 kb
Host smart-6caa4e66-18d6-454b-baf0-56f81a05f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152907788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2152907788
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1957707983
Short name T869
Test name
Test status
Simulation time 237758133 ps
CPU time 0.9 seconds
Started Jul 10 05:46:19 PM PDT 24
Finished Jul 10 05:46:21 PM PDT 24
Peak memory 206968 kb
Host smart-e50a0535-050f-4006-9e7b-17f31d5c7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957707983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1957707983
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2509465342
Short name T10
Test name
Test status
Simulation time 672511814 ps
CPU time 2.99 seconds
Started Jul 10 05:46:21 PM PDT 24
Finished Jul 10 05:46:24 PM PDT 24
Peak memory 225500 kb
Host smart-7cd493ad-c1c0-4e34-9389-d7ecee3af7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509465342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2509465342
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.669873578
Short name T702
Test name
Test status
Simulation time 48951023 ps
CPU time 0.76 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:27 PM PDT 24
Peak memory 205800 kb
Host smart-08d5d2dc-29f4-49cd-9105-26f03f4e407d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669873578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.669873578
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3038646379
Short name T260
Test name
Test status
Simulation time 1163744135 ps
CPU time 5.41 seconds
Started Jul 10 05:46:25 PM PDT 24
Finished Jul 10 05:46:32 PM PDT 24
Peak memory 233704 kb
Host smart-2d3503ae-3f49-4638-b54f-6962f28fa61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038646379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3038646379
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2036617400
Short name T943
Test name
Test status
Simulation time 47293802 ps
CPU time 0.8 seconds
Started Jul 10 05:46:17 PM PDT 24
Finished Jul 10 05:46:19 PM PDT 24
Peak memory 207496 kb
Host smart-491fb4da-8475-4e08-8fa3-afafccabeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036617400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2036617400
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2809684560
Short name T743
Test name
Test status
Simulation time 56892632424 ps
CPU time 214.91 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 251616 kb
Host smart-28ed4324-100a-4ca8-b2e4-61abb385ada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809684560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2809684560
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2742045082
Short name T922
Test name
Test status
Simulation time 65651258213 ps
CPU time 556.78 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:55:44 PM PDT 24
Peak memory 274884 kb
Host smart-8ba0916b-5872-4f25-b441-b632eaf968f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742045082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2742045082
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1515326780
Short name T255
Test name
Test status
Simulation time 20649524872 ps
CPU time 79.2 seconds
Started Jul 10 05:46:28 PM PDT 24
Finished Jul 10 05:47:48 PM PDT 24
Peak memory 242032 kb
Host smart-e42f1a38-8428-453e-8c6e-62c04903ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515326780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1515326780
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2552897670
Short name T186
Test name
Test status
Simulation time 383653412 ps
CPU time 3.99 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:31 PM PDT 24
Peak memory 233788 kb
Host smart-fc27dbd0-1435-4355-aaac-3cd7c7d3ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552897670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2552897670
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3373966069
Short name T816
Test name
Test status
Simulation time 238688257 ps
CPU time 4.03 seconds
Started Jul 10 05:46:29 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 225556 kb
Host smart-1b04906d-3e6c-4881-87ff-cbb4d576424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373966069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3373966069
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.629218015
Short name T22
Test name
Test status
Simulation time 1689904301 ps
CPU time 7.26 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 233656 kb
Host smart-beedcfc9-8b07-40c8-8f97-3782b2f4dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629218015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.629218015
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1850655832
Short name T613
Test name
Test status
Simulation time 6009432716 ps
CPU time 14.03 seconds
Started Jul 10 05:46:27 PM PDT 24
Finished Jul 10 05:46:42 PM PDT 24
Peak memory 242120 kb
Host smart-b3909fd9-9c50-4766-976a-920978a82d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850655832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1850655832
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.923465688
Short name T948
Test name
Test status
Simulation time 8800675728 ps
CPU time 19.29 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 224220 kb
Host smart-17131a4b-9ac8-4d08-9d84-0f82d87bcd51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=923465688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.923465688
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2641775377
Short name T151
Test name
Test status
Simulation time 50962192 ps
CPU time 1.05 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:29 PM PDT 24
Peak memory 208536 kb
Host smart-71c70767-fbf5-44e3-a6b5-51bd188f793d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641775377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2641775377
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1022643924
Short name T299
Test name
Test status
Simulation time 1891976837 ps
CPU time 16.04 seconds
Started Jul 10 05:46:28 PM PDT 24
Finished Jul 10 05:46:45 PM PDT 24
Peak memory 217332 kb
Host smart-045b77d4-7933-4822-8d91-d359f28aabb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022643924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1022643924
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3796507223
Short name T780
Test name
Test status
Simulation time 1124677005 ps
CPU time 6.65 seconds
Started Jul 10 05:46:25 PM PDT 24
Finished Jul 10 05:46:33 PM PDT 24
Peak memory 217312 kb
Host smart-bac5b1a3-39c7-4428-8968-8d967a84e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796507223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3796507223
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2396666370
Short name T639
Test name
Test status
Simulation time 330603978 ps
CPU time 4.54 seconds
Started Jul 10 05:46:27 PM PDT 24
Finished Jul 10 05:46:33 PM PDT 24
Peak memory 217584 kb
Host smart-eeaae26a-2cb7-47b0-86f3-9856f3cbb387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396666370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2396666370
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2892987821
Short name T932
Test name
Test status
Simulation time 13694907 ps
CPU time 0.7 seconds
Started Jul 10 05:46:29 PM PDT 24
Finished Jul 10 05:46:30 PM PDT 24
Peak memory 206544 kb
Host smart-87f2bc96-1663-4b34-a113-13933ecb9f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892987821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2892987821
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2656131420
Short name T71
Test name
Test status
Simulation time 8128817690 ps
CPU time 28.15 seconds
Started Jul 10 05:46:27 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 236108 kb
Host smart-086bfe7e-160d-4c11-8f52-290a85b2cadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656131420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2656131420
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3138031877
Short name T803
Test name
Test status
Simulation time 23422838 ps
CPU time 0.73 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:41:46 PM PDT 24
Peak memory 206260 kb
Host smart-1d424497-9e40-4d02-8d70-05d642d345e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138031877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
138031877
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2996309995
Short name T523
Test name
Test status
Simulation time 31496025 ps
CPU time 2.75 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 233788 kb
Host smart-9a9b73e1-b251-441e-be94-cd0c563df068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996309995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2996309995
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1012061083
Short name T793
Test name
Test status
Simulation time 42400829 ps
CPU time 0.79 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:41:37 PM PDT 24
Peak memory 207496 kb
Host smart-380e4977-9eb9-46f2-b71e-690d6e136e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012061083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1012061083
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3745153845
Short name T42
Test name
Test status
Simulation time 71229788046 ps
CPU time 103.49 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:43:27 PM PDT 24
Peak memory 258160 kb
Host smart-588f0e18-dd15-4d49-9223-1ef876f6946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745153845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3745153845
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2096464360
Short name T265
Test name
Test status
Simulation time 29653290950 ps
CPU time 292.42 seconds
Started Jul 10 05:41:45 PM PDT 24
Finished Jul 10 05:46:39 PM PDT 24
Peak memory 274732 kb
Host smart-0b37fc1f-13eb-4df5-9a9c-e09296dc663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096464360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2096464360
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3640597561
Short name T1003
Test name
Test status
Simulation time 2520404581 ps
CPU time 59.13 seconds
Started Jul 10 05:41:47 PM PDT 24
Finished Jul 10 05:42:46 PM PDT 24
Peak memory 256008 kb
Host smart-f0526484-5c86-4ecc-af9a-3d1dab569b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640597561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3640597561
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.533577824
Short name T138
Test name
Test status
Simulation time 11242449496 ps
CPU time 33.33 seconds
Started Jul 10 05:41:45 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 225600 kb
Host smart-334f26f6-67ab-46a3-a309-e9b7e14cd5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533577824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.533577824
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2000249549
Short name T709
Test name
Test status
Simulation time 14861343577 ps
CPU time 66.99 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:42:53 PM PDT 24
Peak memory 256088 kb
Host smart-a451c842-ac5e-4ca1-b796-c57e85eca21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000249549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2000249549
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3390604708
Short name T804
Test name
Test status
Simulation time 207065504 ps
CPU time 4.56 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 225512 kb
Host smart-38e597eb-3b1c-43c3-8225-b3ffa192fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390604708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3390604708
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.329933616
Short name T966
Test name
Test status
Simulation time 861562584 ps
CPU time 11.69 seconds
Started Jul 10 05:41:35 PM PDT 24
Finished Jul 10 05:41:48 PM PDT 24
Peak memory 233784 kb
Host smart-87868c89-2353-4acc-a21a-8effb54ebd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329933616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.329933616
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1792954619
Short name T418
Test name
Test status
Simulation time 17881847 ps
CPU time 1.07 seconds
Started Jul 10 05:41:37 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 217640 kb
Host smart-d6aa66ac-6a15-4b02-9e9f-2715f592703a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792954619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1792954619
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2992070653
Short name T279
Test name
Test status
Simulation time 1143077274 ps
CPU time 6.17 seconds
Started Jul 10 05:41:37 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 225500 kb
Host smart-b3069ddc-bc74-4b8f-ab09-2f352b86ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992070653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2992070653
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4025976904
Short name T684
Test name
Test status
Simulation time 3637823776 ps
CPU time 7.24 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 225708 kb
Host smart-c8f505e4-0c9a-4bc2-b841-e9121d68cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025976904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4025976904
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2340118288
Short name T917
Test name
Test status
Simulation time 9375216390 ps
CPU time 17.09 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 224236 kb
Host smart-2967440e-b567-4966-bff6-80a3b5d0dd11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2340118288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2340118288
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3175425370
Short name T445
Test name
Test status
Simulation time 2122461388 ps
CPU time 15.61 seconds
Started Jul 10 05:41:37 PM PDT 24
Finished Jul 10 05:41:54 PM PDT 24
Peak memory 220816 kb
Host smart-a8fa03f3-14e3-4add-9a96-6c31cd59c019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175425370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3175425370
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1400937210
Short name T886
Test name
Test status
Simulation time 18202293 ps
CPU time 0.73 seconds
Started Jul 10 05:41:38 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 206628 kb
Host smart-e160a27b-3b66-4986-bf04-e74744fec8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400937210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1400937210
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2272506464
Short name T654
Test name
Test status
Simulation time 181773319 ps
CPU time 8.76 seconds
Started Jul 10 05:41:36 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 217348 kb
Host smart-90daf1a6-cbf4-4789-85b1-2313e04eeb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272506464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2272506464
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1567809747
Short name T515
Test name
Test status
Simulation time 32790879 ps
CPU time 0.87 seconds
Started Jul 10 05:41:37 PM PDT 24
Finished Jul 10 05:41:40 PM PDT 24
Peak memory 206920 kb
Host smart-ff9f11be-aa4f-4780-939c-1c8446a2429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567809747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1567809747
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1100255042
Short name T409
Test name
Test status
Simulation time 9245224201 ps
CPU time 8.45 seconds
Started Jul 10 05:41:34 PM PDT 24
Finished Jul 10 05:41:43 PM PDT 24
Peak memory 225620 kb
Host smart-25e21cba-f934-47ce-9811-67a12d5c41f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100255042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1100255042
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.545426790
Short name T893
Test name
Test status
Simulation time 23616097 ps
CPU time 0.71 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:41:44 PM PDT 24
Peak memory 206340 kb
Host smart-eed15c1e-21d7-4284-812d-b83980c08966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545426790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.545426790
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.151293139
Short name T416
Test name
Test status
Simulation time 121095935 ps
CPU time 2.66 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 225552 kb
Host smart-5d5e0ba0-e5cd-42b7-9dc1-fbda9b974890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151293139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.151293139
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1549396329
Short name T992
Test name
Test status
Simulation time 25398990 ps
CPU time 0.77 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:41:46 PM PDT 24
Peak memory 207436 kb
Host smart-85f26ff7-e434-492e-b773-12e84ed95e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549396329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1549396329
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2673626402
Short name T243
Test name
Test status
Simulation time 4506869323 ps
CPU time 29.45 seconds
Started Jul 10 05:41:49 PM PDT 24
Finished Jul 10 05:42:19 PM PDT 24
Peak memory 250272 kb
Host smart-71cd46ee-e3a9-4d16-b09f-09fb736b8023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673626402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2673626402
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.483577306
Short name T282
Test name
Test status
Simulation time 3921062259 ps
CPU time 20.63 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:42:04 PM PDT 24
Peak memory 251364 kb
Host smart-4d220ba2-5cdb-4c58-88ad-35a2e55ad9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483577306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.483577306
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2034588819
Short name T543
Test name
Test status
Simulation time 2091767536 ps
CPU time 10.74 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:41:55 PM PDT 24
Peak memory 250116 kb
Host smart-6cfe6a19-894c-4564-ac89-f635e0718358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034588819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2034588819
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1365534768
Short name T857
Test name
Test status
Simulation time 35190823814 ps
CPU time 270.29 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:46:16 PM PDT 24
Peak memory 253928 kb
Host smart-30fd752c-ab48-481e-8718-48020e4fe54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365534768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1365534768
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.839694233
Short name T700
Test name
Test status
Simulation time 4415889525 ps
CPU time 16 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:42:01 PM PDT 24
Peak memory 225648 kb
Host smart-59e8e76b-62f1-44e8-a8bc-e446bf3b1c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839694233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.839694233
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1907023093
Short name T584
Test name
Test status
Simulation time 2306108836 ps
CPU time 10.36 seconds
Started Jul 10 05:41:49 PM PDT 24
Finished Jul 10 05:42:00 PM PDT 24
Peak memory 225684 kb
Host smart-b6ec77eb-c356-42e3-88d5-b5cc6f951dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907023093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1907023093
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1244283325
Short name T789
Test name
Test status
Simulation time 156925040 ps
CPU time 1.07 seconds
Started Jul 10 05:41:50 PM PDT 24
Finished Jul 10 05:41:52 PM PDT 24
Peak memory 217640 kb
Host smart-9c1b135a-85bd-4e7f-ab99-7975c431ae0a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244283325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1244283325
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4287208044
Short name T50
Test name
Test status
Simulation time 3939716082 ps
CPU time 6.11 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:41:52 PM PDT 24
Peak memory 233880 kb
Host smart-e6a2fddc-9230-452c-9c02-b9e4ddbb4370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287208044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4287208044
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1306596258
Short name T754
Test name
Test status
Simulation time 6538385690 ps
CPU time 17.11 seconds
Started Jul 10 05:41:45 PM PDT 24
Finished Jul 10 05:42:04 PM PDT 24
Peak memory 225628 kb
Host smart-f148f00f-da50-4551-aa63-f82e876004e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306596258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1306596258
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1834619338
Short name T535
Test name
Test status
Simulation time 1781435709 ps
CPU time 9.64 seconds
Started Jul 10 05:41:45 PM PDT 24
Finished Jul 10 05:41:56 PM PDT 24
Peak memory 223640 kb
Host smart-b0e28802-2130-483b-8cb7-a1b55d94ed90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834619338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1834619338
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.661883131
Short name T19
Test name
Test status
Simulation time 135240620236 ps
CPU time 597.34 seconds
Started Jul 10 05:41:49 PM PDT 24
Finished Jul 10 05:51:47 PM PDT 24
Peak memory 257584 kb
Host smart-5ece47f6-d0f3-4b28-9b91-529b0cf873d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661883131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.661883131
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.656052068
Short name T730
Test name
Test status
Simulation time 3476313368 ps
CPU time 18.07 seconds
Started Jul 10 05:41:46 PM PDT 24
Finished Jul 10 05:42:05 PM PDT 24
Peak memory 217692 kb
Host smart-f1b584d2-0b02-4615-b242-a7467f3ef0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656052068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.656052068
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.826916228
Short name T909
Test name
Test status
Simulation time 339175514 ps
CPU time 1.49 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:41:46 PM PDT 24
Peak memory 208096 kb
Host smart-247d9d33-92fb-403c-ae6b-1aa1c453b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826916228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.826916228
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3899997461
Short name T469
Test name
Test status
Simulation time 107889768 ps
CPU time 1.28 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 208676 kb
Host smart-360994c3-9681-4b93-a91a-2bcc404b444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899997461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3899997461
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1207065566
Short name T550
Test name
Test status
Simulation time 22739622 ps
CPU time 0.79 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 206948 kb
Host smart-80915254-a8f7-4031-bedc-7647aec3ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207065566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1207065566
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3346722217
Short name T214
Test name
Test status
Simulation time 974832418 ps
CPU time 6.02 seconds
Started Jul 10 05:41:42 PM PDT 24
Finished Jul 10 05:41:50 PM PDT 24
Peak memory 233780 kb
Host smart-3b5fa6b2-c92f-4d53-a089-f79d8ebdea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346722217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3346722217
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1364642696
Short name T434
Test name
Test status
Simulation time 21355816 ps
CPU time 0.74 seconds
Started Jul 10 05:42:00 PM PDT 24
Finished Jul 10 05:42:01 PM PDT 24
Peak memory 206392 kb
Host smart-8abe1761-2c28-41d4-98ad-348869e721ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364642696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
364642696
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1802264340
Short name T232
Test name
Test status
Simulation time 1531279099 ps
CPU time 6.45 seconds
Started Jul 10 05:41:48 PM PDT 24
Finished Jul 10 05:41:56 PM PDT 24
Peak memory 225560 kb
Host smart-ab7415c0-f3fd-4e0b-b933-c7af822d847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802264340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1802264340
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.614009785
Short name T995
Test name
Test status
Simulation time 37300397 ps
CPU time 0.76 seconds
Started Jul 10 05:41:45 PM PDT 24
Finished Jul 10 05:41:47 PM PDT 24
Peak memory 206220 kb
Host smart-6e01523a-5790-457c-84bc-190ceafc0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614009785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.614009785
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.490647826
Short name T687
Test name
Test status
Simulation time 11659375096 ps
CPU time 76.83 seconds
Started Jul 10 05:42:00 PM PDT 24
Finished Jul 10 05:43:18 PM PDT 24
Peak memory 250260 kb
Host smart-12de0e5f-f515-4093-9434-a5c5b059f6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490647826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.490647826
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1453703752
Short name T211
Test name
Test status
Simulation time 3485996146 ps
CPU time 75.62 seconds
Started Jul 10 05:41:55 PM PDT 24
Finished Jul 10 05:43:12 PM PDT 24
Peak memory 255076 kb
Host smart-f9268254-c96b-4c22-b20c-aaf403992281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453703752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1453703752
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2232457267
Short name T267
Test name
Test status
Simulation time 10835293708 ps
CPU time 104.34 seconds
Started Jul 10 05:41:55 PM PDT 24
Finished Jul 10 05:43:41 PM PDT 24
Peak memory 266328 kb
Host smart-df79f618-0bc8-46cd-b9ef-b72e7d94fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232457267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2232457267
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.169497473
Short name T694
Test name
Test status
Simulation time 410626149 ps
CPU time 5.31 seconds
Started Jul 10 05:41:48 PM PDT 24
Finished Jul 10 05:41:54 PM PDT 24
Peak memory 233720 kb
Host smart-f952bf7f-23ea-44db-b66c-38cf9d08bf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169497473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.169497473
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.698643975
Short name T853
Test name
Test status
Simulation time 59519946191 ps
CPU time 218.96 seconds
Started Jul 10 05:42:03 PM PDT 24
Finished Jul 10 05:45:43 PM PDT 24
Peak memory 255196 kb
Host smart-6ee5546a-6ff0-4c9a-88d9-6d94af49150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698643975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
698643975
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.982144130
Short name T383
Test name
Test status
Simulation time 1662527419 ps
CPU time 4.78 seconds
Started Jul 10 05:41:49 PM PDT 24
Finished Jul 10 05:41:54 PM PDT 24
Peak memory 225544 kb
Host smart-398f85e8-521b-4e4f-9aa8-e846b85a79c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982144130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.982144130
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2151159901
Short name T861
Test name
Test status
Simulation time 59654733722 ps
CPU time 145.26 seconds
Started Jul 10 05:41:47 PM PDT 24
Finished Jul 10 05:44:13 PM PDT 24
Peak memory 233812 kb
Host smart-e2bb7c40-31b9-4848-999c-5b2c65755052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151159901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2151159901
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.494895122
Short name T965
Test name
Test status
Simulation time 36152123 ps
CPU time 1.04 seconds
Started Jul 10 05:41:41 PM PDT 24
Finished Jul 10 05:41:43 PM PDT 24
Peak memory 217636 kb
Host smart-7543b1f4-b0a8-4ddb-b69c-4c85be7659d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494895122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.494895122
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.206721698
Short name T51
Test name
Test status
Simulation time 3483539930 ps
CPU time 15.64 seconds
Started Jul 10 05:41:50 PM PDT 24
Finished Jul 10 05:42:07 PM PDT 24
Peak memory 241132 kb
Host smart-28ed990c-3985-4e01-9666-8bfa5beb9844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206721698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
206721698
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.653653386
Short name T230
Test name
Test status
Simulation time 1671909199 ps
CPU time 4.62 seconds
Started Jul 10 05:41:50 PM PDT 24
Finished Jul 10 05:41:56 PM PDT 24
Peak memory 233784 kb
Host smart-76006313-55f3-42a0-a161-340743aec50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653653386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.653653386
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2552705680
Short name T417
Test name
Test status
Simulation time 5927910563 ps
CPU time 19.44 seconds
Started Jul 10 05:41:56 PM PDT 24
Finished Jul 10 05:42:16 PM PDT 24
Peak memory 223144 kb
Host smart-532ec9c1-493e-4306-8639-8ede4bb0a977
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552705680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2552705680
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1143490448
Short name T565
Test name
Test status
Simulation time 9910900431 ps
CPU time 15.13 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:42:00 PM PDT 24
Peak memory 217512 kb
Host smart-e8148423-ee3d-41e7-9233-030682156343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143490448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1143490448
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2458663785
Short name T951
Test name
Test status
Simulation time 6889197452 ps
CPU time 18.8 seconds
Started Jul 10 05:41:43 PM PDT 24
Finished Jul 10 05:42:03 PM PDT 24
Peak memory 217448 kb
Host smart-b856f797-f870-4939-bdc3-2a0793e6f7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458663785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2458663785
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1079185107
Short name T453
Test name
Test status
Simulation time 56186933 ps
CPU time 1.25 seconds
Started Jul 10 05:41:50 PM PDT 24
Finished Jul 10 05:41:52 PM PDT 24
Peak memory 217144 kb
Host smart-e5c72dc1-913b-4afa-8a62-1e6279a24752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079185107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1079185107
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1136902708
Short name T486
Test name
Test status
Simulation time 330758937 ps
CPU time 0.84 seconds
Started Jul 10 05:41:44 PM PDT 24
Finished Jul 10 05:41:46 PM PDT 24
Peak memory 207476 kb
Host smart-30ad924a-b14f-4ac2-9439-f63b093d56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136902708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1136902708
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3129802475
Short name T622
Test name
Test status
Simulation time 36292335096 ps
CPU time 12.45 seconds
Started Jul 10 05:41:48 PM PDT 24
Finished Jul 10 05:42:02 PM PDT 24
Peak memory 233852 kb
Host smart-6f4d5c28-b636-4ab8-b24c-24a99b56cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129802475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3129802475
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.195272284
Short name T478
Test name
Test status
Simulation time 15613820 ps
CPU time 0.77 seconds
Started Jul 10 05:42:03 PM PDT 24
Finished Jul 10 05:42:05 PM PDT 24
Peak memory 206696 kb
Host smart-14d413ab-2abf-42e0-9870-8211d9985538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195272284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.195272284
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2465154725
Short name T68
Test name
Test status
Simulation time 732755484 ps
CPU time 3.95 seconds
Started Jul 10 05:42:05 PM PDT 24
Finished Jul 10 05:42:10 PM PDT 24
Peak memory 225524 kb
Host smart-10dec99a-5056-4eb0-a47b-e94984540522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465154725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2465154725
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.301931493
Short name T436
Test name
Test status
Simulation time 70842304 ps
CPU time 0.86 seconds
Started Jul 10 05:41:56 PM PDT 24
Finished Jul 10 05:41:58 PM PDT 24
Peak memory 207492 kb
Host smart-bc1298e5-c8bf-4242-86ab-ac226e45e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301931493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.301931493
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2481961920
Short name T655
Test name
Test status
Simulation time 5521098844 ps
CPU time 74.56 seconds
Started Jul 10 05:42:05 PM PDT 24
Finished Jul 10 05:43:20 PM PDT 24
Peak memory 250324 kb
Host smart-0da1a0da-fa91-413b-8245-285ddf69e31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481961920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2481961920
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2559718645
Short name T36
Test name
Test status
Simulation time 255726765081 ps
CPU time 308.99 seconds
Started Jul 10 05:42:04 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 258528 kb
Host smart-86b1b0f2-1766-427d-bb1e-b199aa858b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559718645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2559718645
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1599939585
Short name T503
Test name
Test status
Simulation time 15167720839 ps
CPU time 137.62 seconds
Started Jul 10 05:42:02 PM PDT 24
Finished Jul 10 05:44:21 PM PDT 24
Peak memory 252816 kb
Host smart-94b49dc5-9baa-4ea5-a9dd-1e2b1b772a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599939585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1599939585
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.196066533
Short name T650
Test name
Test status
Simulation time 608909779 ps
CPU time 5.78 seconds
Started Jul 10 05:42:03 PM PDT 24
Finished Jul 10 05:42:09 PM PDT 24
Peak memory 225564 kb
Host smart-6e3baea0-b705-4fcb-9a7c-f088a06e1ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196066533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.196066533
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1732792021
Short name T811
Test name
Test status
Simulation time 144874345 ps
CPU time 0.97 seconds
Started Jul 10 05:42:02 PM PDT 24
Finished Jul 10 05:42:04 PM PDT 24
Peak memory 217060 kb
Host smart-180744a7-1cd3-4bfa-889e-da4b1d285a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732792021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1732792021
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1393831127
Short name T514
Test name
Test status
Simulation time 649290781 ps
CPU time 9.51 seconds
Started Jul 10 05:41:56 PM PDT 24
Finished Jul 10 05:42:07 PM PDT 24
Peak memory 233672 kb
Host smart-3ea08280-65c5-4196-8c20-c50ecbe2f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393831127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1393831127
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.88795662
Short name T444
Test name
Test status
Simulation time 8295143003 ps
CPU time 40.55 seconds
Started Jul 10 05:41:57 PM PDT 24
Finished Jul 10 05:42:38 PM PDT 24
Peak memory 225624 kb
Host smart-7b250c24-d71f-45fa-b890-1a9bc83c9456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88795662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.88795662
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.236313016
Short name T39
Test name
Test status
Simulation time 64120365 ps
CPU time 1.1 seconds
Started Jul 10 05:41:57 PM PDT 24
Finished Jul 10 05:41:59 PM PDT 24
Peak memory 217592 kb
Host smart-ebfc31fd-a3e0-4537-943f-fd4efc5bcc5d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236313016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.236313016
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2484548474
Short name T746
Test name
Test status
Simulation time 3012057106 ps
CPU time 5.13 seconds
Started Jul 10 05:41:55 PM PDT 24
Finished Jul 10 05:42:01 PM PDT 24
Peak memory 225724 kb
Host smart-a705ae64-8fce-4656-858e-1c724cb857f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484548474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2484548474
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4154367787
Short name T80
Test name
Test status
Simulation time 1771138635 ps
CPU time 8.04 seconds
Started Jul 10 05:41:58 PM PDT 24
Finished Jul 10 05:42:07 PM PDT 24
Peak memory 241724 kb
Host smart-cb92d42c-e0f3-4dc3-8e26-009cdcbf1d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154367787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4154367787
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2766662809
Short name T692
Test name
Test status
Simulation time 967599194 ps
CPU time 4.98 seconds
Started Jul 10 05:42:04 PM PDT 24
Finished Jul 10 05:42:09 PM PDT 24
Peak memory 223344 kb
Host smart-8cf94f94-8eb1-46ae-871c-2a023905aff4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2766662809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2766662809
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1527485518
Short name T631
Test name
Test status
Simulation time 3538428876 ps
CPU time 24.74 seconds
Started Jul 10 05:41:55 PM PDT 24
Finished Jul 10 05:42:20 PM PDT 24
Peak memory 217492 kb
Host smart-bdfa94d2-b22d-48d1-8a56-da4fc838de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527485518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1527485518
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3298276635
Short name T812
Test name
Test status
Simulation time 67134693778 ps
CPU time 11.33 seconds
Started Jul 10 05:41:56 PM PDT 24
Finished Jul 10 05:42:08 PM PDT 24
Peak memory 217480 kb
Host smart-77dc90ed-7e6b-40a6-8f76-ba9cce60e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298276635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3298276635
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1494064939
Short name T891
Test name
Test status
Simulation time 78338688 ps
CPU time 0.85 seconds
Started Jul 10 05:41:56 PM PDT 24
Finished Jul 10 05:41:58 PM PDT 24
Peak memory 207548 kb
Host smart-ced3f725-e531-4411-8c74-64678c3dc03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494064939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1494064939
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4246407647
Short name T747
Test name
Test status
Simulation time 79033625 ps
CPU time 0.84 seconds
Started Jul 10 05:42:03 PM PDT 24
Finished Jul 10 05:42:05 PM PDT 24
Peak memory 206936 kb
Host smart-37e5c770-1683-43e6-83c4-731e0af6af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246407647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4246407647
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4111107021
Short name T220
Test name
Test status
Simulation time 2235353103 ps
CPU time 5.77 seconds
Started Jul 10 05:42:05 PM PDT 24
Finished Jul 10 05:42:11 PM PDT 24
Peak memory 225644 kb
Host smart-5488cd1b-00e0-4cc0-b759-5f1689a36527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111107021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4111107021
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3138627325
Short name T388
Test name
Test status
Simulation time 14874613 ps
CPU time 0.74 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:18 PM PDT 24
Peak memory 206308 kb
Host smart-1953f4bd-30a4-4602-8a5a-449195012e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138627325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
138627325
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1381545450
Short name T660
Test name
Test status
Simulation time 382115997 ps
CPU time 5.08 seconds
Started Jul 10 05:42:10 PM PDT 24
Finished Jul 10 05:42:16 PM PDT 24
Peak memory 233784 kb
Host smart-547ff322-aaf9-45e1-9197-4c2228ea8d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381545450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1381545450
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1077108810
Short name T373
Test name
Test status
Simulation time 19530687 ps
CPU time 0.83 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:17 PM PDT 24
Peak memory 207496 kb
Host smart-c1163212-5930-4d46-af27-8143889c3c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077108810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1077108810
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1525321842
Short name T273
Test name
Test status
Simulation time 39249725401 ps
CPU time 279.71 seconds
Started Jul 10 05:42:10 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 250328 kb
Host smart-58bf477b-01aa-474e-a5cc-61a68993bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525321842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1525321842
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2032387171
Short name T31
Test name
Test status
Simulation time 14699752585 ps
CPU time 49.9 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:43:07 PM PDT 24
Peak memory 250736 kb
Host smart-402c03f9-32be-4f58-a57f-25469aa8f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032387171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2032387171
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1132806652
Short name T773
Test name
Test status
Simulation time 96547111355 ps
CPU time 170.79 seconds
Started Jul 10 05:42:17 PM PDT 24
Finished Jul 10 05:45:09 PM PDT 24
Peak memory 250240 kb
Host smart-68248ef5-98f0-4378-9ccf-baf9da0ae2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132806652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1132806652
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1122638806
Short name T387
Test name
Test status
Simulation time 1663200456 ps
CPU time 7.45 seconds
Started Jul 10 05:42:07 PM PDT 24
Finished Jul 10 05:42:15 PM PDT 24
Peak memory 233680 kb
Host smart-0b096d65-c76d-43a1-ac35-0e8ed2bd1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122638806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1122638806
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1920214106
Short name T156
Test name
Test status
Simulation time 37330953252 ps
CPU time 95.55 seconds
Started Jul 10 05:42:07 PM PDT 24
Finished Jul 10 05:43:44 PM PDT 24
Peak memory 250300 kb
Host smart-dd3a40cf-ae23-429c-9e65-a0abb17338f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920214106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1920214106
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1902859593
Short name T359
Test name
Test status
Simulation time 252404566 ps
CPU time 4.22 seconds
Started Jul 10 05:42:10 PM PDT 24
Finished Jul 10 05:42:15 PM PDT 24
Peak memory 222276 kb
Host smart-ad5e801f-0064-4301-a499-988af9d533f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902859593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1902859593
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3475304498
Short name T504
Test name
Test status
Simulation time 5858904399 ps
CPU time 16.66 seconds
Started Jul 10 05:42:10 PM PDT 24
Finished Jul 10 05:42:27 PM PDT 24
Peak memory 233868 kb
Host smart-94b8bb39-fce3-454a-a919-2d81c3ea0685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475304498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3475304498
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.890381955
Short name T470
Test name
Test status
Simulation time 16818534 ps
CPU time 1 seconds
Started Jul 10 05:42:09 PM PDT 24
Finished Jul 10 05:42:10 PM PDT 24
Peak memory 218824 kb
Host smart-1dd350b4-3586-43fb-b453-3ada349caa7a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890381955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.890381955
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4147409681
Short name T241
Test name
Test status
Simulation time 2005265173 ps
CPU time 8.53 seconds
Started Jul 10 05:42:07 PM PDT 24
Finished Jul 10 05:42:16 PM PDT 24
Peak memory 225588 kb
Host smart-7b340975-aec4-460e-a105-1cc8834288dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147409681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4147409681
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2103564588
Short name T875
Test name
Test status
Simulation time 1119474737 ps
CPU time 3.12 seconds
Started Jul 10 05:42:09 PM PDT 24
Finished Jul 10 05:42:13 PM PDT 24
Peak memory 233716 kb
Host smart-713655ff-8508-4d4b-8d81-82e6df1f729e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103564588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2103564588
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3138365986
Short name T360
Test name
Test status
Simulation time 665938983 ps
CPU time 5.4 seconds
Started Jul 10 05:42:08 PM PDT 24
Finished Jul 10 05:42:14 PM PDT 24
Peak memory 220292 kb
Host smart-a1fd6ba3-84c5-4bfe-b199-5d497dd2b10b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3138365986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3138365986
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1715552898
Short name T153
Test name
Test status
Simulation time 76429212526 ps
CPU time 163.31 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:44:59 PM PDT 24
Peak memory 253288 kb
Host smart-49e38109-b132-4fe0-a69b-98fef8d12265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715552898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1715552898
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4122097580
Short name T956
Test name
Test status
Simulation time 37205712217 ps
CPU time 39.24 seconds
Started Jul 10 05:42:09 PM PDT 24
Finished Jul 10 05:42:49 PM PDT 24
Peak memory 221452 kb
Host smart-2efd1ea7-0e6c-4a24-8162-4c634e412137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122097580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4122097580
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3308042278
Short name T502
Test name
Test status
Simulation time 1595509033 ps
CPU time 6.21 seconds
Started Jul 10 05:42:15 PM PDT 24
Finished Jul 10 05:42:23 PM PDT 24
Peak memory 217308 kb
Host smart-a1311016-ea0b-411c-9bbd-43a9d7dcd577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308042278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3308042278
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2621465245
Short name T562
Test name
Test status
Simulation time 497295366 ps
CPU time 4.25 seconds
Started Jul 10 05:42:09 PM PDT 24
Finished Jul 10 05:42:15 PM PDT 24
Peak memory 217328 kb
Host smart-98deccd0-1bd2-4842-b245-0da1f8be2859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621465245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2621465245
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.96122381
Short name T66
Test name
Test status
Simulation time 108151631 ps
CPU time 0.84 seconds
Started Jul 10 05:42:08 PM PDT 24
Finished Jul 10 05:42:09 PM PDT 24
Peak memory 206948 kb
Host smart-3bedc021-9168-41f5-b122-6777eba38d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96122381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.96122381
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3156209109
Short name T797
Test name
Test status
Simulation time 4798778577 ps
CPU time 22.46 seconds
Started Jul 10 05:42:10 PM PDT 24
Finished Jul 10 05:42:34 PM PDT 24
Peak memory 233880 kb
Host smart-52bc8a13-52d7-4290-9f9e-fa3f51717e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156209109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3156209109
Directory /workspace/9.spi_device_upload/latest
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