Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2939520	1			T1	298		T2	241		T3	1
all_values[1]	2939520	1			T1	298		T2	241		T3	1
all_values[2]	2939520	1			T1	298		T2	241		T3	1
all_values[3]	2939520	1			T1	298		T2	241		T3	1
all_values[4]	2939520	1			T1	298		T2	241		T3	1
all_values[5]	2939520	1			T1	298		T2	241		T3	1
all_values[6]	2939520	1			T1	298		T2	241		T3	1
all_values[7]	2939520	1			T1	298		T2	241		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22282966

1

T1

2384

T2

1928

T3

8

auto[1]

1233194

1

T9

13289

T59

117

T14

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23489635

1

T1

2384

T2

1928

T3

8

auto[1]

26525

1

T9

304

T24

202

T33

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2702458	1			T1	298		T2	241		T3	1
all_values[0]	auto[0]	auto[1]	11312	1			T9	5		T24	96		T33	6
all_values[0]	auto[1]	auto[0]	224427	1			T9	2513		T59	11		T14	4
all_values[0]	auto[1]	auto[1]	1323	1			T9	135		T59	2		T14	1
all_values[1]	auto[0]	auto[0]	2834671	1			T1	298		T2	241		T3	1
all_values[1]	auto[0]	auto[1]	8124	1			T9	7		T24	96		T33	1
all_values[1]	auto[1]	auto[0]	96097	1			T9	2558		T59	6		T14	1
all_values[1]	auto[1]	auto[1]	628	1			T9	93		T59	4		T14	3
all_values[2]	auto[0]	auto[0]	2827334	1			T1	298		T2	241		T3	1
all_values[2]	auto[0]	auto[1]	2868	1			T9	2		T24	10		T34	13
all_values[2]	auto[1]	auto[0]	108947	1			T9	2632		T59	5		T14	5
all_values[2]	auto[1]	auto[1]	371	1			T9	19		T59	12		T14	3
all_values[3]	auto[0]	auto[0]	2748685	1			T1	298		T2	241		T3	1
all_values[3]	auto[0]	auto[1]	168	1			T9	5		T59	2		T14	3
all_values[3]	auto[1]	auto[0]	190437	1			T9	2648		T59	10		T14	2
all_values[3]	auto[1]	auto[1]	230	1			T9	4		T59	12		T14	1
all_values[4]	auto[0]	auto[0]	2815717	1			T1	298		T2	241		T3	1
all_values[4]	auto[0]	auto[1]	206	1			T9	7		T59	6		T14	2
all_values[4]	auto[1]	auto[0]	123391	1			T9	5		T59	4		T14	5
all_values[4]	auto[1]	auto[1]	206	1			T9	1		T59	10		T14	3
all_values[5]	auto[0]	auto[0]	2720824	1			T1	298		T2	241		T3	1
all_values[5]	auto[0]	auto[1]	183	1			T9	5		T59	4		T14	3
all_values[5]	auto[1]	auto[0]	218357	1			T9	8		T59	14		T14	7
all_values[5]	auto[1]	auto[1]	156	1			T9	3		T59	4		T14	1
all_values[6]	auto[0]	auto[0]	2792609	1			T1	298		T2	241		T3	1
all_values[6]	auto[0]	auto[1]	191	1			T9	4		T59	13		T14	1
all_values[6]	auto[1]	auto[0]	146519	1			T9	7		T59	2		T14	3
all_values[6]	auto[1]	auto[1]	201	1			T9	7		T59	7		T14	3
all_values[7]	auto[0]	auto[0]	2817439	1			T1	298		T2	241		T3	1
all_values[7]	auto[0]	auto[1]	177	1			T9	1		T59	3		T14	3
all_values[7]	auto[1]	auto[0]	121723	1			T9	2650		T59	9		T14	2
all_values[7]	auto[1]	auto[1]	181	1			T9	6		T59	5		T14	1