Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34967	1			T1	2		T2	65		T3	2
auto[SpiFlashAddrCfg]	7999	1			T1	2		T2	6		T3	2
auto[SpiFlashAddr3b]	9496	1			T1	6		T2	10		T3	4
auto[SpiFlashAddr4b]	7827	1			T1	4		T2	18		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33655

1

T1

14

T2

74

T3

8

auto[1]

26634

1

T2

25

T7

279

T9

71

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31444

1

T1

6

T2

67

T3

4

auto[1]

28845

1

T1

8

T2

32

T3

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40000	1			T1	4		T2	70		T3	6
values[1]	1186	1			T2	1		T7	2		T9	3
values[2]	1604	1			T7	5		T9	7		T24	4
values[3]	1447	1			T1	2		T2	5		T7	8
values[4]	1514	1			T1	2		T2	4		T7	5
values[5]	1401	1			T2	1		T7	12		T9	4
values[6]	1565	1			T2	2		T7	14		T9	6
values[7]	1512	1			T2	2		T3	2		T6	2
values[8]	10060	1			T1	6		T2	14		T7	53

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26631

1

T1

14

T3

8

T6

2

auto[1]

33658

1

T2

99

T7

412

T24

111

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56807

1

T1

14

T2

96

T3

8

write

3482

1

T2

3

T7

20

T9

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19806

1

T1

8

T2

33

T3

2

valids[0x1]

40483

1

T1

6

T2

66

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1694	1			T2	3		T7	9		T9	4
internal_process_ops[0x5a]	1710	1			T2	1		T3	4		T7	7
internal_process_ops[0x05]	20574	1			T2	43		T7	184		T9	79
internal_process_ops[0x35]	1651	1			T2	3		T7	13		T9	3
internal_process_ops[0x15]	1674	1			T1	2		T2	4		T7	9
internal_process_ops[0x03]	1133	1			T1	2		T7	8		T9	9
internal_process_ops[0x0b]	988	1			T7	2		T9	5		T12	4
internal_process_ops[0x3b]	1003	1			T6	2		T7	1		T9	2
internal_process_ops[0x6b]	958	1			T2	1		T7	5		T9	6
internal_process_ops[0xbb]	1081	1			T1	4		T2	1		T9	9
internal_process_ops[0xeb]	1057	1			T2	2		T7	3		T9	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58585

1

T1

14

T2

99

T3

8

auto[1]

1704

1

T7

9

T9

3

T24

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57760

1

T1

14

T2

97

T3

8

auto[1]

2529

1

T2

2

T7

12

T9

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8362

1

T1

2

T3

2

T9

84

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5747

1

T9

39

T30

20

T31

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1863

1

T1

2

T3

2

T9

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1622

1

T9

11

T30

14

T31

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2181

1

T1

6

T3

4

T9

25

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1993

1

T9

9

T30

22

T33

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1892

1

T1

4

T6

2

T9

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1571

1

T9

9

T30

13

T31

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T9

1

T41

1

T47

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

83

1

T9

3

T30

1

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

64

1

T33

1

T14

1

T48

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

75

1

T30

2

T31

1

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T30

1

T33

2

T14

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

69

1

T41

1

T47

6

T48

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T9

3

T30

1

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

79

1

T30

3

T33

1

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T9

3

T25

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

72

1

T47

2

T15

1

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T30

1

T33

2

T47

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

119

1

T15

1

T48

2

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T9

1

T14

1

T15

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

66

1

T30

1

T14

2

T15

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T30

1

T33

1

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T30

1

T33

4

T14

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11754

1

T2

59

T7

59

T24

38

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8279

1

T2

6

T7

212

T24

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1841

1

T2

5

T7

30

T24

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1804

1

T2

1

T7

20

T24

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2262

1

T2

3

T7

14

T24

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2156

1

T2

5

T7

16

T24

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1783

1

T2

5

T7

19

T24

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1697

1

T2

12

T7

22

T24

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T7

1

T24

3

T34

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T24

1

T40

6

T13

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

128

1

T40

2

T13

2

T57

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

151

1

T7

1

T35

5

T57

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T7

2

T24

1

T40

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

129

1

T7

3

T40

3

T15

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

135

1

T7

2

T24

1

T34

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

142

1

T7

1

T40

1

T35

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

134

1

T2

2

T7

2

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

144

1

T34

2

T35

1

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

150

1

T7

3

T35

1

T13

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T7

1

T35

1

T13

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T7

1

T24

3

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

137

1

T7

2

T40

2

T13

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

124

1

T2

1

T40

2

T34

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

141

1

T7

1

T40

6

T35

7

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3357	1			T9	32		T46	2		T30	40
auto[0]	values[0]	valids[0x1]	13333	1			T1	4		T3	6		T9	118
auto[0]	values[1]	valids[0x1]	533	1			T9	3		T12	4		T30	6
auto[0]	values[2]	valids[0x0]	529	1			T9	2		T30	4		T33	3
auto[0]	values[2]	valids[0x1]	270	1			T9	5		T30	4		T33	3
auto[0]	values[3]	valids[0x0]	464	1			T9	2		T12	10		T30	2
auto[0]	values[3]	valids[0x1]	259	1			T1	2		T9	3		T30	1
auto[0]	values[4]	valids[0x0]	515	1			T1	2		T9	2		T30	3
auto[0]	values[4]	valids[0x1]	252	1			T9	4		T30	3		T41	2
auto[0]	values[5]	valids[0x0]	412	1			T9	3		T30	3		T33	6
auto[0]	values[5]	valids[0x1]	223	1			T9	1		T30	3		T86	2
auto[0]	values[6]	valids[0x0]	500	1			T9	5		T25	2		T30	5
auto[0]	values[6]	valids[0x1]	293	1			T9	1		T33	2		T41	1
auto[0]	values[7]	valids[0x0]	503	1			T3	2		T6	2		T9	1
auto[0]	values[7]	valids[0x1]	253	1			T12	4		T30	4		T33	5
auto[0]	values[8]	valids[0x0]	3135	1			T1	6		T9	19		T12	6
auto[0]	values[8]	valids[0x1]	1800	1			T9	12		T11	2		T30	30
auto[1]	values[0]	valids[0x0]	4662	1			T2	11		T7	50		T24	23
auto[1]	values[0]	valids[0x1]	18648	1			T2	59		T7	255		T24	43
auto[1]	values[1]	valids[0x1]	653	1			T2	1		T7	2		T24	4
auto[1]	values[2]	valids[0x0]	466	1			T7	3		T24	3		T40	3
auto[1]	values[2]	valids[0x1]	339	1			T7	2		T24	1		T40	1
auto[1]	values[3]	valids[0x0]	427	1			T2	3		T7	3		T24	1
auto[1]	values[3]	valids[0x1]	297	1			T2	2		T7	5		T40	1
auto[1]	values[4]	valids[0x0]	434	1			T2	3		T7	5		T24	1
auto[1]	values[4]	valids[0x1]	313	1			T2	1		T40	4		T34	2
auto[1]	values[5]	valids[0x0]	472	1			T2	1		T7	3		T24	1
auto[1]	values[5]	valids[0x1]	294	1			T7	9		T40	3		T35	4
auto[1]	values[6]	valids[0x0]	461	1			T2	2		T7	13		T24	11
auto[1]	values[6]	valids[0x1]	311	1			T7	1		T24	1		T40	2
auto[1]	values[7]	valids[0x0]	457	1			T7	4		T40	2		T34	2
auto[1]	values[7]	valids[0x1]	299	1			T2	2		T7	4		T24	3
auto[1]	values[8]	valids[0x0]	3012	1			T2	13		T7	35		T24	14
auto[1]	values[8]	valids[0x1]	2113	1			T2	1		T7	18		T24	5