Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3434804

1

T1

513

T2

4980

T3

1

auto[1]

32014

1

T2

39

T7

172

T9

73

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

883263

1

T1

1

T2

14

T3

1

auto[1]

2583555

1

T1

512

T2

5005

T7

13602

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	609175	1			T1	513		T2	3004		T3	1
auto[524288:1048575]	418487	1			T2	1		T7	1887		T8	577
auto[1048576:1572863]	403410	1			T2	551		T7	1045		T9	261
auto[1572864:2097151]	374928	1			T2	951		T7	2315		T9	2814
auto[2097152:2621439]	412944	1			T7	8		T12	188		T24	3810
auto[2621440:3145727]	376410	1			T7	258		T9	7		T12	731
auto[3145728:3670015]	425725	1			T7	10		T8	1		T9	1628
auto[3670016:4194303]	445739	1			T2	512		T7	2844		T8	1422

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619040

1

T1

513

T2

5019

T3

1

auto[1]

847778

1

T4

10

T7

15

T8

2561

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2969898

1

T1

513

T2

4781

T3

1

auto[1]

496920

1

T2

238

T7

4502

T9

813

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	181450	1			T1	1		T2	4		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	357154	1			T1	512		T2	3000		T7	3193
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	106653	1			T2	1		T7	3		T8	577
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	246682	1			T7	1320		T9	6		T24	384
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	93968	1			T2	1		T7	6		T9	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	242172	1			T2	550		T7	1026		T9	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	95955	1			T2	6		T7	6		T9	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	205791	1			T2	681		T7	961		T9	2784
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	88211	1			T7	1		T12	188		T24	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	254354	1			T24	2940		T30	903		T40	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	82549	1			T7	1		T9	6		T12	731
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	253895	1			T7	256		T40	654		T33	771
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95432	1			T7	1		T8	1		T9	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	263830	1			T7	3		T9	805		T30	121
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	123431	1			T7	6		T8	1422		T9	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	250952	1			T2	512		T7	2301		T9	1132
auto[0]	auto[1]	auto[0:524287]	auto[0]	1176	1			T7	9		T30	14		T33	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	65404	1			T7	2009		T33	3		T35	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3265	1			T7	2		T30	96		T31	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	57627	1			T7	562		T30	899		T31	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2728	1			T30	13		T40	21		T35	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60306	1			T30	351		T33	256		T35	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	681	1			T7	12		T9	1		T40	42
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	68032	1			T2	225		T7	1288		T40	495
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1421	1			T7	2		T30	8		T40	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	64765	1			T7	1		T24	869		T30	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	522	1			T7	1		T9	1		T40	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	35481	1			T35	493		T47	1		T43	513
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	722	1			T7	1		T9	7		T30	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	61981	1			T7	5		T9	775		T33	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	655	1			T7	3		T9	2		T30	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	67559	1			T7	517		T9	1		T40	2153
auto[1]	auto[0]	auto[0:524287]	auto[0]	575	1			T7	3		T24	1		T25	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2691	1			T7	49		T25	64		T35	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	506	1			T9	2		T30	3		T40	7
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3107	1			T9	5		T31	11		T33	18
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	388	1			T7	2		T9	1		T40	12
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3459	1			T7	11		T9	1		T40	87
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	416	1			T2	1		T9	2		T24	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3325	1			T2	25		T9	23		T24	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	474	1			T33	5		T13	5		T57	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2851	1			T33	9		T13	31		T57	34
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	448	1			T30	4		T40	9		T33	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3147	1			T30	5		T33	11		T35	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	486	1			T9	2		T30	4		T33	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2904	1			T9	10		T13	5		T57	39
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	421	1			T7	1		T9	1		T40	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2221	1			T7	16		T33	5		T34	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	105	1			T7	3		T35	1		T81	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	620	1			T7	35		T35	1		T81	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	128	1			T30	19		T34	1		T35	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	519	1			T30	256		T34	1		T35	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	66	1			T35	1		T47	1		T15	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	323	1			T35	1		T47	1		T15	33
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	109	1			T2	1		T7	2		T40	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	619	1			T2	12		T7	46		T40	35
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	74	1			T7	1		T30	4		T35	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	794	1			T7	3		T30	5		T48	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	64	1			T40	2		T35	3		T47	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	304	1			T35	1		T43	1		T251	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	89	1			T9	2		T15	1		T181	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	281	1			T9	19		T15	1		T196	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	95	1			T9	1		T30	9		T40	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	405	1			T9	4		T47	1		T264	22

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2101504	1			T1	513		T2	4755		T3	1
auto[0]	auto[0]	auto[1]	840975	1			T4	10		T7	4		T8	2561
auto[0]	auto[1]	auto[0]	486340	1			T2	225		T7	4409		T9	787
auto[0]	auto[1]	auto[1]	5985	1			T7	3		T35	1		T15	2
auto[1]	auto[0]	auto[0]	26735	1			T2	26		T7	77		T9	47
auto[1]	auto[0]	auto[1]	684	1			T7	5		T25	2		T30	4
auto[1]	auto[1]	auto[0]	4461	1			T2	13		T7	87		T9	26
auto[1]	auto[1]	auto[1]	134	1			T7	3		T30	3		T40	2