Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2939520	1			T1	298		T2	241		T3	1
all_pins[1]	2939520	1			T1	298		T2	241		T3	1
all_pins[2]	2939520	1			T1	298		T2	241		T3	1
all_pins[3]	2939520	1			T1	298		T2	241		T3	1
all_pins[4]	2939520	1			T1	298		T2	241		T3	1
all_pins[5]	2939520	1			T1	298		T2	241		T3	1
all_pins[6]	2939520	1			T1	298		T2	241		T3	1
all_pins[7]	2939520	1			T1	298		T2	241		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23363848	1			T1	2384		T2	1928		T3	8
values[0x1]	152312	1			T9	288		T59	56		T14	16
transitions[0x0=>0x1]	150911	1			T9	169		T59	38		T14	13
transitions[0x1=>0x0]	150924	1			T9	169		T59	39		T14	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2938104	1			T1	298		T2	241		T3	1
all_pins[0]	values[0x1]	1416	1			T9	146		T59	2		T14	1
all_pins[0]	transitions[0x0=>0x1]	1179	1			T9	50		T59	2		T14	1
all_pins[0]	transitions[0x1=>0x0]	426	1			T9	4		T59	4		T14	3
all_pins[1]	values[0x0]	2938857	1			T1	298		T2	241		T3	1
all_pins[1]	values[0x1]	663	1			T9	100		T59	4		T14	3
all_pins[1]	transitions[0x0=>0x1]	465	1			T9	84		T59	3		T14	2
all_pins[1]	transitions[0x1=>0x0]	187	1			T9	5		T59	11		T14	2
all_pins[2]	values[0x0]	2939135	1			T1	298		T2	241		T3	1
all_pins[2]	values[0x1]	385	1			T9	21		T59	12		T14	3
all_pins[2]	transitions[0x0=>0x1]	318	1			T9	19		T59	5		T14	3
all_pins[2]	transitions[0x1=>0x0]	163	1			T9	2		T59	5		T14	1
all_pins[3]	values[0x0]	2939290	1			T1	298		T2	241		T3	1
all_pins[3]	values[0x1]	230	1			T9	4		T59	12		T14	1
all_pins[3]	transitions[0x0=>0x1]	163	1			T9	3		T59	7		T16	5
all_pins[3]	transitions[0x1=>0x0]	139	1			T59	5		T14	2		T16	7
all_pins[4]	values[0x0]	2939314	1			T1	298		T2	241		T3	1
all_pins[4]	values[0x1]	206	1			T9	1		T59	10		T14	3
all_pins[4]	transitions[0x0=>0x1]	162	1			T9	1		T59	8		T14	3
all_pins[4]	transitions[0x1=>0x0]	2811	1			T9	3		T59	2		T14	1
all_pins[5]	values[0x0]	2936665	1			T1	298		T2	241		T3	1
all_pins[5]	values[0x1]	2855	1			T9	3		T59	4		T14	1
all_pins[5]	transitions[0x0=>0x1]	2165	1			T9	2		T59	3		T14	1
all_pins[5]	transitions[0x1=>0x0]	145686	1			T9	6		T59	6		T14	3
all_pins[6]	values[0x0]	2793144	1			T1	298		T2	241		T3	1
all_pins[6]	values[0x1]	146376	1			T9	7		T59	7		T14	3
all_pins[6]	transitions[0x0=>0x1]	146328	1			T9	5		T59	7		T14	3
all_pins[6]	transitions[0x1=>0x0]	133	1			T9	4		T59	5		T14	1
all_pins[7]	values[0x0]	2939339	1			T1	298		T2	241		T3	1
all_pins[7]	values[0x1]	181	1			T9	6		T59	5		T14	1
all_pins[7]	transitions[0x0=>0x1]	131	1			T9	5		T59	3		T16	3
all_pins[7]	transitions[0x1=>0x0]	1379	1			T9	145		T59	1		T16	6