Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15006

1

T1

14

T3

8

T6

2

auto[1]

11625

1

T9

71

T30

78

T31

24

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3201	1			T9	80		T25	72		T30	20
values[1]	3687	1			T41	40		T47	21		T15	40
values[2]	3019	1			T9	48		T30	20		T86	26
values[3]	3731	1			T33	26		T41	20		T14	21
values[4]	2716	1			T1	14		T9	50		T46	2
values[5]	3041	1			T6	2		T188	4		T41	20
values[6]	3395	1			T3	8		T9	35		T12	24
values[7]	3841	1			T11	2		T30	60		T33	97

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3338	1			T6	2		T9	35		T30	40
values[1]	3288	1			T9	60		T33	35		T41	20
values[2]	3079	1			T9	46		T25	72		T30	20
values[3]	3395	1			T9	50		T33	20		T14	20
values[4]	3251	1			T9	22		T11	2		T12	24
values[5]	3133	1			T30	40		T33	22		T56	4
values[6]	3702	1			T3	8		T30	40		T86	26
values[7]	3445	1			T1	14		T30	40		T31	32

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	146	1			T48	11		T164	21		T260	14
auto[0]	values[0]	values[1]	262	1			T9	31		T14	31		T171	6
auto[0]	values[0]	values[2]	249	1			T9	13		T25	72		T170	8
auto[0]	values[0]	values[3]	187	1			T33	6		T48	7		T42	13
auto[0]	values[0]	values[4]	170	1			T33	7		T47	18		T43	19
auto[0]	values[0]	values[5]	227	1			T56	4		T42	14		T43	9
auto[0]	values[0]	values[6]	301	1			T47	65		T187	13		T162	12
auto[0]	values[0]	values[7]	235	1			T30	18		T41	11		T14	13
auto[0]	values[1]	values[0]	229	1			T41	10		T19	8		T265	8
auto[0]	values[1]	values[1]	236	1			T43	29		T178	15		T175	17
auto[0]	values[1]	values[2]	102	1			T41	10		T15	14		T170	15
auto[0]	values[1]	values[3]	440	1			T15	9		T92	17		T190	20
auto[0]	values[1]	values[4]	433	1			T47	14		T48	11		T92	16
auto[0]	values[1]	values[5]	157	1			T43	9		T176	13		T195	4
auto[0]	values[1]	values[6]	305	1			T42	8		T178	10		T164	12
auto[0]	values[1]	values[7]	205	1			T176	24		T170	13		T257	4
auto[0]	values[2]	values[0]	233	1			T165	13		T181	11		T266	22
auto[0]	values[2]	values[1]	201	1			T14	15		T48	10		T267	22
auto[0]	values[2]	values[2]	137	1			T9	18		T33	16		T268	2
auto[0]	values[2]	values[3]	178	1			T43	17		T178	11		T206	11
auto[0]	values[2]	values[4]	192	1			T9	15		T43	8		T197	13
auto[0]	values[2]	values[5]	185	1			T30	12		T58	12		T187	30
auto[0]	values[2]	values[6]	284	1			T86	26		T41	8		T15	28
auto[0]	values[2]	values[7]	307	1			T31	8		T47	11		T48	23
auto[0]	values[3]	values[0]	114	1			T42	12		T176	13		T125	8
auto[0]	values[3]	values[1]	152	1			T42	12		T186	8		T134	29
auto[0]	values[3]	values[2]	275	1			T33	18		T41	12		T187	11
auto[0]	values[3]	values[3]	333	1			T171	15		T269	14		T213	11
auto[0]	values[3]	values[4]	285	1			T92	10		T171	4		T196	14
auto[0]	values[3]	values[5]	283	1			T47	16		T48	11		T184	28
auto[0]	values[3]	values[6]	330	1			T14	9		T178	9		T176	8
auto[0]	values[3]	values[7]	280	1			T15	28		T176	16		T170	12
auto[0]	values[4]	values[0]	136	1			T169	18		T192	36		T270	2
auto[0]	values[4]	values[1]	282	1			T15	72		T42	58		T180	10
auto[0]	values[4]	values[2]	187	1			T30	11		T14	8		T15	8
auto[0]	values[4]	values[3]	156	1			T9	49		T48	16		T178	11
auto[0]	values[4]	values[4]	93	1			T46	2		T271	6		T133	16
auto[0]	values[4]	values[5]	315	1			T30	14		T33	13		T48	5
auto[0]	values[4]	values[6]	173	1			T30	24		T15	15		T181	10
auto[0]	values[4]	values[7]	214	1			T1	14		T178	11		T19	8
auto[0]	values[5]	values[0]	212	1			T6	2		T174	8		T170	10
auto[0]	values[5]	values[1]	242	1			T42	14		T134	44		T205	9
auto[0]	values[5]	values[2]	302	1			T188	4		T41	11		T92	11
auto[0]	values[5]	values[3]	156	1			T14	12		T15	12		T196	14
auto[0]	values[5]	values[4]	248	1			T15	8		T181	22		T186	7
auto[0]	values[5]	values[5]	96	1			T201	22		T43	5		T176	4
auto[0]	values[5]	values[6]	205	1			T48	17		T176	11		T170	11
auto[0]	values[5]	values[7]	149	1			T189	4		T42	8		T43	8
auto[0]	values[6]	values[0]	405	1			T9	16		T33	15		T41	6
auto[0]	values[6]	values[1]	144	1			T41	11		T176	12		T133	12
auto[0]	values[6]	values[2]	182	1			T33	14		T47	8		T92	12
auto[0]	values[6]	values[3]	228	1			T47	11		T176	31		T165	16
auto[0]	values[6]	values[4]	168	1			T12	24		T15	16		T170	7
auto[0]	values[6]	values[5]	180	1			T171	14		T182	14		T181	16
auto[0]	values[6]	values[6]	199	1			T3	8		T178	13		T272	2
auto[0]	values[6]	values[7]	309	1			T30	10		T41	15		T194	4
auto[0]	values[7]	values[0]	388	1			T30	22		T33	5		T42	10
auto[0]	values[7]	values[1]	440	1			T33	11		T47	20		T178	8
auto[0]	values[7]	values[2]	214	1			T47	7		T48	12		T43	10
auto[0]	values[7]	values[3]	171	1			T93	6		T48	13		T42	21
auto[0]	values[7]	values[4]	183	1			T11	2		T30	11		T15	28
auto[0]	values[7]	values[5]	385	1			T178	9		T171	20		T165	10
auto[0]	values[7]	values[6]	349	1			T42	11		T176	11		T186	30
auto[0]	values[7]	values[7]	242	1			T14	5		T47	10		T48	22
auto[1]	values[0]	values[0]	104	1			T48	26		T164	2		T51	14
auto[1]	values[0]	values[1]	184	1			T9	29		T14	9		T171	14
auto[1]	values[0]	values[2]	136	1			T9	7		T170	12		T263	18
auto[1]	values[0]	values[3]	244	1			T33	14		T48	13		T42	90
auto[1]	values[0]	values[4]	233	1			T33	13		T47	10		T43	5
auto[1]	values[0]	values[5]	190	1			T42	6		T43	11		T164	11
auto[1]	values[0]	values[6]	191	1			T47	15		T187	18		T186	15
auto[1]	values[0]	values[7]	142	1			T30	2		T41	9		T14	10
auto[1]	values[1]	values[0]	135	1			T41	10		T19	12		T133	10
auto[1]	values[1]	values[1]	184	1			T43	18		T178	6		T175	46
auto[1]	values[1]	values[2]	88	1			T41	10		T15	6		T170	5
auto[1]	values[1]	values[3]	184	1			T15	11		T92	3		T171	7
auto[1]	values[1]	values[4]	235	1			T47	7		T48	18		T92	4
auto[1]	values[1]	values[5]	166	1			T43	11		T176	29		T183	13
auto[1]	values[1]	values[6]	362	1			T42	29		T178	10		T164	9
auto[1]	values[1]	values[7]	226	1			T176	9		T170	7		T183	6
auto[1]	values[2]	values[0]	111	1			T165	7		T181	9		T183	6
auto[1]	values[2]	values[1]	109	1			T14	5		T48	38		T125	10
auto[1]	values[2]	values[2]	210	1			T9	8		T33	4		T95	26
auto[1]	values[2]	values[3]	124	1			T43	6		T178	14		T206	30
auto[1]	values[2]	values[4]	188	1			T9	7		T43	12		T197	7
auto[1]	values[2]	values[5]	79	1			T30	8		T187	8		T19	5
auto[1]	values[2]	values[6]	320	1			T41	12		T15	154		T171	35
auto[1]	values[2]	values[7]	161	1			T31	24		T47	9		T48	8
auto[1]	values[3]	values[0]	173	1			T42	119		T176	7		T125	12
auto[1]	values[3]	values[1]	146	1			T42	44		T186	12		T134	23
auto[1]	values[3]	values[2]	193	1			T33	8		T41	8		T187	65
auto[1]	values[3]	values[3]	440	1			T171	5		T213	9		T125	14
auto[1]	values[3]	values[4]	175	1			T92	10		T171	46		T196	9
auto[1]	values[3]	values[5]	136	1			T47	7		T48	9		T197	6
auto[1]	values[3]	values[6]	148	1			T14	12		T178	12		T176	12
auto[1]	values[3]	values[7]	268	1			T15	12		T176	12		T170	8
auto[1]	values[4]	values[0]	121	1			T94	14		T192	9		T273	4
auto[1]	values[4]	values[1]	135	1			T15	7		T42	8		T170	11
auto[1]	values[4]	values[2]	231	1			T30	9		T14	29		T15	15
auto[1]	values[4]	values[3]	95	1			T9	1		T48	4		T178	9
auto[1]	values[4]	values[4]	93	1			T133	4		T221	7		T222	6
auto[1]	values[4]	values[5]	188	1			T30	6		T33	9		T48	15
auto[1]	values[4]	values[6]	135	1			T30	16		T15	39		T181	10
auto[1]	values[4]	values[7]	162	1			T178	17		T19	12		T133	8
auto[1]	values[5]	values[0]	181	1			T170	10		T274	10		T125	20
auto[1]	values[5]	values[1]	281	1			T42	6		T134	17		T205	84
auto[1]	values[5]	values[2]	245	1			T41	9		T92	9		T187	52
auto[1]	values[5]	values[3]	74	1			T14	8		T15	8		T196	8
auto[1]	values[5]	values[4]	202	1			T15	12		T181	18		T186	30
auto[1]	values[5]	values[5]	129	1			T43	19		T176	16		T204	8
auto[1]	values[5]	values[6]	214	1			T48	3		T176	13		T170	9
auto[1]	values[5]	values[7]	105	1			T42	13		T43	12		T176	11
auto[1]	values[6]	values[0]	381	1			T9	19		T33	5		T41	14
auto[1]	values[6]	values[1]	104	1			T41	9		T176	8		T133	8
auto[1]	values[6]	values[2]	111	1			T33	9		T47	12		T92	8
auto[1]	values[6]	values[3]	275	1			T47	12		T176	9		T165	58
auto[1]	values[6]	values[4]	248	1			T15	99		T170	13		T196	29
auto[1]	values[6]	values[5]	177	1			T171	6		T182	6		T181	4
auto[1]	values[6]	values[6]	69	1			T178	10		T183	10		T275	6
auto[1]	values[6]	values[7]	215	1			T30	10		T41	5		T92	5
auto[1]	values[7]	values[0]	269	1			T30	18		T33	57		T42	64
auto[1]	values[7]	values[1]	186	1			T33	24		T47	7		T178	12
auto[1]	values[7]	values[2]	217	1			T47	15		T48	37		T43	10
auto[1]	values[7]	values[3]	110	1			T48	16		T42	28		T187	7
auto[1]	values[7]	values[4]	105	1			T30	9		T15	8		T171	6
auto[1]	values[7]	values[5]	240	1			T178	11		T171	4		T191	6
auto[1]	values[7]	values[6]	117	1			T42	9		T176	61		T186	12
auto[1]	values[7]	values[7]	225	1			T14	16		T47	31		T48	2