Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	375	1			T9	3		T11	2		T12	4
auto[ReadAddrCrossIntoMailbox]	283	1			T9	3		T12	4		T30	3
auto[ReadAddrCrossOutOfMailbox]	278	1			T9	1		T12	8		T31	1
auto[ReadAddrCrossAllMailbox]	207	1			T9	1		T12	6		T33	4
auto[ReadAddrOutsideMailbox]	3190	1			T1	6		T6	2		T9	26

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2108

1

T1

3

T6

1

T9

22

auto[1]

2225

1

T1

3

T6

1

T9

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	783	1			T1	2		T9	9		T11	2
read_ops[0x0b]	688	1			T9	5		T12	4		T30	11
read_ops[0x3b]	717	1			T6	2		T9	2		T12	8
read_ops[0x6b]	685	1			T9	6		T12	2		T30	2
read_ops[0xbb]	722	1			T1	4		T9	9		T12	6
read_ops[0xeb]	738	1			T9	3		T30	10		T31	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T9	1		T11	1		T15	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T11	1		T31	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T12	1		T33	1		T42	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T12	1		T31	1		T14	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T12	1		T48	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T9	1		T12	1		T14	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T42	1		T178	1		T276	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T41	1		T164	1		T181	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T1	1		T9	5		T30	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T1	1		T9	2		T30	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T41	1		T48	2		T176	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T178	1		T187	1		T197	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T47	2		T48	1		T125	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T9	1		T30	1		T170	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T47	2		T15	2		T48	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T41	1		T48	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T12	1		T42	2		T43	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T12	1		T14	1		T47	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	230	1			T9	3		T12	1		T30	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T9	1		T12	1		T30	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T12	2		T48	1		T43	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T12	2		T33	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T42	1		T178	1		T171	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T178	4		T276	1		T175	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T12	2		T15	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T12	2		T14	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T48	1		T42	1		T277	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T33	2		T41	1		T48	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T6	1		T41	4		T14	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T6	1		T9	2		T30	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T41	1		T47	1		T201	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T9	1		T14	1		T201	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T41	1		T47	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T33	1		T14	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T170	1		T181	1		T206	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T92	1		T170	1		T181	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T12	1		T48	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	1		T92	1		T176	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T9	3		T30	2		T86	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T9	2		T86	1		T31	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T42	1		T176	1		T170	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T14	1		T47	1		T15	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T9	1		T12	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T12	1		T33	1		T14	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T12	1		T14	1		T15	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T12	1		T31	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T12	1		T43	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T9	1		T12	1		T33	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T1	2		T9	6		T30	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T1	2		T9	1		T30	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T9	1		T30	1		T47	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T278	1		T171	1		T176	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T9	1		T15	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T30	2		T14	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T41	1		T42	3		T178	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T47	1		T178	2		T174	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T42	1		T197	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T41	1		T43	1		T176	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T9	1		T30	3		T31	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T30	4		T33	4		T41	3