Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3425	1			T1	14		T30	20		T31	32
values[1]	3342	1			T46	2		T30	40		T33	42
values[2]	3121	1			T9	72		T30	40		T33	20
values[3]	3588	1			T3	8		T9	20		T30	60
values[4]	2930	1			T9	29		T11	2		T30	20
values[5]	3555	1			T9	26		T12	24		T25	72
values[6]	3847	1			T6	2		T41	40		T14	60
values[7]	2823	1			T9	66		T33	62		T41	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3532	1			T3	8		T30	40		T33	20
values[1]	3001	1			T1	14		T9	35		T12	24
values[2]	3523	1			T31	32		T41	20		T14	44
values[3]	3542	1			T9	29		T30	20		T86	26
values[4]	3330	1			T6	2		T9	26		T30	40
values[5]	3570	1			T9	72		T47	89		T169	18
values[6]	3137	1			T9	31		T25	72		T46	2
values[7]	2996	1			T9	20		T11	2		T30	60

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25974

1

T1

14

T3

8

T6

2

auto[1]

657

1

T9

3

T30

8

T31

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[5]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	424	1			T33	19		T42	126		T170	20
auto[0]	values[0]	values[1]	348	1			T1	14		T56	4		T93	6
auto[0]	values[0]	values[2]	461	1			T31	31		T14	20		T15	53
auto[0]	values[0]	values[3]	605	1			T48	49		T171	20		T164	23
auto[0]	values[0]	values[4]	569	1			T14	20		T48	20		T170	18
auto[0]	values[0]	values[5]	298	1			T125	20		T172	122		T173	49
auto[0]	values[0]	values[6]	353	1			T30	20		T174	8		T175	39
auto[0]	values[0]	values[7]	286	1			T33	25		T176	22		T177	4
auto[0]	values[1]	values[0]	335	1			T30	20		T41	20		T178	21
auto[0]	values[1]	values[1]	577	1			T15	55		T178	23		T171	20
auto[0]	values[1]	values[2]	269	1			T15	20		T179	2		T165	32
auto[0]	values[1]	values[3]	400	1			T30	18		T33	19		T14	21
auto[0]	values[1]	values[4]	356	1			T43	23		T180	10		T181	20
auto[0]	values[1]	values[5]	601	1			T47	26		T169	18		T42	25
auto[0]	values[1]	values[6]	372	1			T46	2		T33	21		T42	64
auto[0]	values[1]	values[7]	328	1			T48	48		T178	20		T176	40
auto[0]	values[2]	values[0]	587	1			T15	79		T176	40		T181	20
auto[0]	values[2]	values[1]	274	1			T30	16		T182	20		T183	20
auto[0]	values[2]	values[2]	396	1			T184	28		T185	24		T186	31
auto[0]	values[2]	values[3]	226	1			T43	20		T187	30		T181	20
auto[0]	values[2]	values[4]	316	1			T48	23		T92	20		T176	18
auto[0]	values[2]	values[5]	635	1			T9	71		T47	37		T42	37
auto[0]	values[2]	values[6]	266	1			T15	42		T182	19		T181	18
auto[0]	values[2]	values[7]	326	1			T30	18		T33	20		T58	12
auto[0]	values[3]	values[0]	639	1			T3	8		T188	4		T42	23
auto[0]	values[3]	values[1]	194	1			T189	4		T15	43		T190	20
auto[0]	values[3]	values[2]	507	1			T15	62		T42	101		T178	19
auto[0]	values[3]	values[3]	481	1			T14	39		T47	53		T42	20
auto[0]	values[3]	values[4]	389	1			T30	20		T187	38		T191	6
auto[0]	values[3]	values[5]	455	1			T15	70		T186	25		T125	30
auto[0]	values[3]	values[6]	462	1			T33	20		T15	20		T171	43
auto[0]	values[3]	values[7]	400	1			T9	20		T30	40		T41	20
auto[0]	values[4]	values[0]	403	1			T87	12		T192	33		T193	82
auto[0]	values[4]	values[1]	456	1			T41	20		T42	27		T164	20
auto[0]	values[4]	values[2]	373	1			T194	4		T187	32		T186	29
auto[0]	values[4]	values[3]	418	1			T9	27		T48	17		T92	20
auto[0]	values[4]	values[4]	315	1			T30	20		T48	20		T178	20
auto[0]	values[4]	values[5]	189	1			T181	20		T175	21		T186	19
auto[0]	values[4]	values[6]	308	1			T176	40		T195	4		T175	17
auto[0]	values[4]	values[7]	387	1			T11	2		T33	23		T47	21
auto[0]	values[5]	values[0]	377	1			T30	20		T187	64		T196	59
auto[0]	values[5]	values[1]	380	1			T12	24		T43	24		T176	20
auto[0]	values[5]	values[2]	523	1			T41	20		T43	22		T197	20
auto[0]	values[5]	values[3]	390	1			T86	26		T41	19		T47	40
auto[0]	values[5]	values[4]	393	1			T9	26		T47	21		T42	54
auto[0]	values[5]	values[5]	419	1			T171	46		T182	19		T181	18
auto[0]	values[5]	values[6]	600	1			T25	72		T33	35		T47	22
auto[0]	values[5]	values[7]	406	1			T43	20		T178	21		T198	20
auto[0]	values[6]	values[0]	354	1			T41	20		T14	34		T175	18
auto[0]	values[6]	values[1]	313	1			T41	20		T48	49		T178	20
auto[0]	values[6]	values[2]	497	1			T14	22		T47	80		T15	20
auto[0]	values[6]	values[3]	623	1			T43	20		T178	20		T187	146
auto[0]	values[6]	values[4]	520	1			T6	2		T15	117		T94	14
auto[0]	values[6]	values[5]	624	1			T47	23		T42	20		T43	22
auto[0]	values[6]	values[6]	350	1			T48	18		T42	43		T170	19
auto[0]	values[6]	values[7]	462	1			T15	17		T48	47		T43	20
auto[0]	values[7]	values[0]	335	1			T170	18		T164	46		T192	32
auto[0]	values[7]	values[1]	386	1			T9	35		T41	19		T171	20
auto[0]	values[7]	values[2]	426	1			T178	21		T199	10		T125	28
auto[0]	values[7]	values[3]	312	1			T170	20		T200	12		T196	23
auto[0]	values[7]	values[4]	401	1			T41	20		T201	22		T43	22
auto[0]	values[7]	values[5]	237	1			T48	29		T162	12		T202	22
auto[0]	values[7]	values[6]	344	1			T9	31		T33	60		T14	20
auto[0]	values[7]	values[7]	318	1			T92	20		T175	21		T203	24
auto[1]	values[0]	values[0]	11	1			T33	1		T42	5		T196	1
auto[1]	values[0]	values[1]	14	1			T181	3		T204	1		T205	3
auto[1]	values[0]	values[2]	7	1			T31	1		T14	1		T15	1
auto[1]	values[0]	values[3]	15	1			T206	4		T207	6		T208	3
auto[1]	values[0]	values[4]	13	1			T170	2		T181	1		T209	3
auto[1]	values[0]	values[6]	13	1			T210	1		T204	3		T211	1
auto[1]	values[0]	values[7]	8	1			T33	1		T176	2		T212	1
auto[1]	values[1]	values[0]	15	1			T175	1		T192	1		T206	1
auto[1]	values[1]	values[1]	20	1			T15	1		T170	2		T210	4
auto[1]	values[1]	values[2]	5	1			T175	2		T213	3		-	-
auto[1]	values[1]	values[3]	12	1			T30	2		T33	1		T178	1
auto[1]	values[1]	values[4]	9	1			T43	1		T125	1		T214	2
auto[1]	values[1]	values[5]	26	1			T47	1		T42	1		T95	4
auto[1]	values[1]	values[6]	11	1			T33	1		T42	2		T134	5
auto[1]	values[1]	values[7]	6	1			T48	1		T170	1		T187	1
auto[1]	values[2]	values[0]	9	1			T206	2		T208	2		T215	1
auto[1]	values[2]	values[1]	12	1			T30	4		T183	1		T205	3
auto[1]	values[2]	values[2]	8	1			T186	1		T207	1		T216	2
auto[1]	values[2]	values[3]	6	1			T187	1		T192	1		T217	1
auto[1]	values[2]	values[4]	14	1			T48	1		T176	2		T196	3
auto[1]	values[2]	values[5]	22	1			T9	1		T47	2		T92	1
auto[1]	values[2]	values[6]	6	1			T182	1		T181	2		T134	2
auto[1]	values[2]	values[7]	18	1			T30	2		T48	2		T92	3
auto[1]	values[3]	values[0]	9	1			T176	1		T133	1		T204	2
auto[1]	values[3]	values[1]	2	1			T51	1		T214	1		-	-
auto[1]	values[3]	values[2]	11	1			T15	2		T42	2		T178	2
auto[1]	values[3]	values[3]	11	1			T14	1		T47	5		T134	2
auto[1]	values[3]	values[4]	5	1			T211	1		T218	2		T219	2
auto[1]	values[3]	values[5]	13	1			T15	3		T125	1		T217	4
auto[1]	values[3]	values[6]	4	1			T171	1		T165	1		T220	1
auto[1]	values[3]	values[7]	6	1			T178	1		T183	2		T221	1
auto[1]	values[4]	values[0]	8	1			T183	3		T222	4		T220	1
auto[1]	values[4]	values[1]	8	1			T42	1		T209	2		T134	2
auto[1]	values[4]	values[2]	8	1			T187	1		T213	1		T125	2
auto[1]	values[4]	values[3]	16	1			T9	2		T48	3		T171	1
auto[1]	values[4]	values[4]	5	1			T176	1		T51	1		T223	1
auto[1]	values[4]	values[5]	14	1			T186	1		T224	8		T225	1
auto[1]	values[4]	values[6]	15	1			T176	2		T175	3		T220	1
auto[1]	values[4]	values[7]	7	1			T204	3		T226	2		T227	1
auto[1]	values[5]	values[0]	6	1			T187	1		T196	3		T192	1
auto[1]	values[5]	values[1]	8	1			T134	3		T210	2		T228	1
auto[1]	values[5]	values[2]	9	1			T43	1		T229	2		T220	1
auto[1]	values[5]	values[3]	9	1			T41	1		T19	1		T222	4
auto[1]	values[5]	values[4]	8	1			T47	2		T42	2		T230	2
auto[1]	values[5]	values[5]	14	1			T171	4		T182	1		T181	2
auto[1]	values[5]	values[6]	7	1			T178	2		T206	1		T205	1
auto[1]	values[5]	values[7]	6	1			T133	1		T134	2		T159	3
auto[1]	values[6]	values[0]	12	1			T14	3		T175	2		T214	2
auto[1]	values[6]	values[1]	2	1			T192	1		T231	1		-	-
auto[1]	values[6]	values[2]	13	1			T14	1		T47	2		T181	1
auto[1]	values[6]	values[3]	14	1			T187	3		T205	2		T232	1
auto[1]	values[6]	values[4]	5	1			T15	1		T134	1		T223	1
auto[1]	values[6]	values[5]	20	1			T43	2		T187	3		T186	3
auto[1]	values[6]	values[6]	13	1			T48	2		T42	3		T170	1
auto[1]	values[6]	values[7]	25	1			T15	3		T48	1		T176	1
auto[1]	values[7]	values[0]	8	1			T170	2		T164	1		T192	1
auto[1]	values[7]	values[1]	7	1			T41	1		T133	1		T51	2
auto[1]	values[7]	values[2]	10	1			T125	1		T133	1		T232	2
auto[1]	values[7]	values[3]	4	1			T75	2		T160	1		T233	1
auto[1]	values[7]	values[4]	12	1			T43	1		T196	4		T51	1
auto[1]	values[7]	values[5]	3	1			T48	2		T212	1		-	-
auto[1]	values[7]	values[6]	13	1			T33	2		T197	3		T234	1
auto[1]	values[7]	values[7]	7	1			T207	3		T160	2		T223	1