Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	825	1			T9	21		T59	24		T14	11
all_values[1]	825	1			T9	21		T59	24		T14	11
all_values[2]	825	1			T9	21		T59	24		T14	11
all_values[3]	825	1			T9	21		T59	24		T14	11
all_values[4]	825	1			T9	21		T59	24		T14	11
all_values[5]	825	1			T9	21		T59	24		T14	11
all_values[6]	825	1			T9	21		T59	24		T14	11
all_values[7]	825	1			T9	21		T59	24		T14	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3534

1

T9

87

T59

98

T14

50

auto[1]

3066

1

T9

81

T59

94

T14

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2711

1

T9

79

T59

61

T14

45

auto[1]

3889

1

T9

89

T59

131

T14

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3820

1

T9

103

T59

98

T14

61

auto[1]

2780

1

T9

65

T59

94

T14

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T9	6		T59	5		T14	5
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T9	3		T59	2		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	154	1			T9	5		T59	4		T14	3
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T9	1		T59	2		T14	1
all_values[0]	auto[1]	auto[0]	auto[1]	202	1			T9	6		T59	9		T14	1
all_values[0]	auto[1]	auto[1]	auto[1]	144	1			T59	2		T14	1		T16	6
all_values[1]	auto[0]	auto[0]	auto[0]	192	1			T9	2		T59	7		T14	1
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T9	2		T59	5		T14	3
all_values[1]	auto[0]	auto[1]	auto[0]	149	1			T9	3		T59	2		T14	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T9	2		T59	1		T14	3
all_values[1]	auto[1]	auto[0]	auto[1]	176	1			T9	7		T59	6		T14	2
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T9	5		T59	3		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	158	1			T9	2		T59	3		T14	3
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T9	1		T14	2		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T9	7		T14	2		T16	4
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T9	2		T59	5		T14	1
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T9	1		T59	8		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	178	1			T9	8		T59	8		T14	2
all_values[3]	auto[0]	auto[0]	auto[0]	167	1			T9	5		T59	2		T14	4
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T9	2		T59	1		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T9	5		T59	6		T14	3
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T9	2		T59	4		T16	4
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T9	2		T59	2		T14	3
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T9	5		T59	9		T16	5
all_values[4]	auto[0]	auto[0]	auto[0]	177	1			T9	8		T59	2		T14	1
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T9	2		T59	4		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T9	4		T59	2		T14	4
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T59	4		T16	4		T17	4
all_values[4]	auto[1]	auto[0]	auto[1]	199	1			T9	6		T59	4		T14	2
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T9	1		T59	8		T14	3
all_values[5]	auto[0]	auto[0]	auto[0]	247	1			T9	8		T59	8		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	239	1			T9	5		T59	8		T14	6
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T9	6		T59	2		T14	4
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T9	2		T59	6		T16	4
all_values[6]	auto[0]	auto[0]	auto[0]	194	1			T9	3		T59	1		T14	4
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T9	4		T59	4		T16	2
all_values[6]	auto[0]	auto[1]	auto[0]	115	1			T9	3		T14	1		T16	8
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T9	2		T59	2		T14	2
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T9	4		T59	10		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T9	5		T59	7		T14	2
all_values[7]	auto[0]	auto[0]	auto[0]	192	1			T9	4		T59	7		T14	6
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T14	2		T16	1		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T9	9		T59	4		T16	7
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T9	1		T59	3		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	178	1			T9	3		T59	6		T14	1
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T9	4		T59	4		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal