Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1717

1

T9

8

T24

3

T26

1

auto[1]

1752

1

T9

12

T24

2

T26

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1980

1

T9

20

T24

5

T27

11

auto[1]

1489

1

T26

2

T29

11

T33

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2726

1

T9

13

T24

3

T26

2

auto[1]

743

1

T9

7

T24

2

T27

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	677	1			T9	2		T24	2		T29	3
valid[1]	679	1			T9	4		T27	3		T29	1
valid[2]	701	1			T9	8		T24	2		T27	1
valid[3]	694	1			T9	2		T24	1		T26	2
valid[4]	718	1			T9	4		T27	6		T29	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T24	1		T32	1		T34	2
auto[0]	auto[0]	valid[0]	auto[1]	135	1			T84	4		T302	4		T303	1
auto[0]	auto[0]	valid[1]	auto[0]	132	1			T9	2		T34	1		T35	2
auto[0]	auto[0]	valid[1]	auto[1]	134	1			T29	1		T84	2		T85	1
auto[0]	auto[0]	valid[2]	auto[0]	113	1			T9	1		T32	1		T35	2
auto[0]	auto[0]	valid[2]	auto[1]	137	1			T84	2		T85	1		T302	3
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T9	1		T24	1		T35	2
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T26	1		T29	1		T47	1
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T27	4		T35	1		T49	1
auto[0]	auto[0]	valid[4]	auto[1]	172	1			T29	3		T84	1		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T9	2		T35	1		T49	1
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T29	3		T84	3		T85	1
auto[0]	auto[1]	valid[1]	auto[0]	130	1			T9	2		T27	2		T34	1
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T83	1		T84	2		T85	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T9	2		T24	1		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	158	1			T29	2		T84	1		T85	1
auto[0]	auto[1]	valid[3]	auto[0]	117	1			T27	1		T35	1		T49	1
auto[0]	auto[1]	valid[3]	auto[1]	159	1			T26	1		T15	1		T302	2
auto[0]	auto[1]	valid[4]	auto[0]	147	1			T9	3		T27	1		T33	1
auto[0]	auto[1]	valid[4]	auto[1]	133	1			T29	1		T33	1		T83	1
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T24	1		T35	1		T49	1
auto[1]	auto[0]	valid[1]	auto[0]	58	1			T27	1		T35	1		T49	1
auto[1]	auto[0]	valid[2]	auto[0]	96	1			T9	2		T33	1		T34	2
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T9	1		T49	1		T13	1
auto[1]	auto[0]	valid[4]	auto[0]	82	1			T9	1		T27	1		T32	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T49	1		T13	1		T290	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T35	2		T13	4		T15	4
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T9	3		T24	1		T49	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T35	1		T14	1		T297	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T33	1		T49	1		T13	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal