Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49060

1

T9

407

T24

115

T27

289

auto[1]

15333

1

T26

2

T27

29

T29

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46806

1

T9

263

T24

71

T26

2

auto[1]

17587

1

T9

144

T24

44

T27

103

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32973	1			T9	213		T24	63		T26	2
others[1]	5371	1			T9	42		T24	10		T27	27
others[2]	5507	1			T9	33		T24	9		T27	31
others[3]	6171	1			T9	36		T24	12		T27	27
interest[1]	3656	1			T9	21		T24	8		T27	14
interest[4]	21663	1			T9	135		T24	41		T26	2
interest[64]	10715	1			T9	62		T24	13		T27	57

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16040	1			T9	139		T24	39		T27	95
auto[0]	auto[0]	others[1]	2628	1			T9	22		T24	8		T27	12
auto[0]	auto[0]	others[2]	2712	1			T9	18		T24	5		T27	20
auto[0]	auto[0]	others[3]	3048	1			T9	29		T24	6		T27	16
auto[0]	auto[0]	interest[1]	1826	1			T9	14		T24	6		T27	8
auto[0]	auto[0]	interest[4]	10449	1			T9	90		T24	25		T27	69
auto[0]	auto[0]	interest[64]	5219	1			T9	41		T24	7		T27	35
auto[0]	auto[1]	others[0]	8049	1			T26	2		T27	15		T29	11
auto[0]	auto[1]	others[1]	1253	1			T27	4		T33	1		T34	2
auto[0]	auto[1]	others[2]	1272	1			T27	2		T33	2		T34	1
auto[0]	auto[1]	others[3]	1424	1			T27	2		T33	9		T47	6
auto[0]	auto[1]	interest[1]	811	1			T27	2		T33	3		T47	3
auto[0]	auto[1]	interest[4]	5425	1			T26	2		T27	11		T29	11
auto[0]	auto[1]	interest[64]	2524	1			T27	4		T33	7		T34	1
auto[1]	auto[0]	others[0]	8884	1			T9	74		T24	24		T27	52
auto[1]	auto[0]	others[1]	1490	1			T9	20		T24	2		T27	11
auto[1]	auto[0]	others[2]	1523	1			T9	15		T24	4		T27	9
auto[1]	auto[0]	others[3]	1699	1			T9	7		T24	6		T27	9
auto[1]	auto[0]	interest[1]	1019	1			T9	7		T24	2		T27	4
auto[1]	auto[0]	interest[4]	5789	1			T9	45		T24	16		T27	31
auto[1]	auto[0]	interest[64]	2972	1			T9	21		T24	6		T27	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal