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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.45 94.08 98.62 89.36 97.29 95.43 99.21


Total test records in report: 1151
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T1037 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.438405941 Jul 11 04:51:19 PM PDT 24 Jul 11 04:51:45 PM PDT 24 4639366567 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1861824247 Jul 11 04:51:43 PM PDT 24 Jul 11 04:51:59 PM PDT 24 611486528 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1623802197 Jul 11 04:51:33 PM PDT 24 Jul 11 04:51:35 PM PDT 24 22045976 ps
T107 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1028337022 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:10 PM PDT 24 126982714 ps
T112 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2050840003 Jul 11 04:52:05 PM PDT 24 Jul 11 04:52:11 PM PDT 24 38927685 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3843500866 Jul 11 04:51:22 PM PDT 24 Jul 11 04:51:27 PM PDT 24 14672260 ps
T140 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3372234025 Jul 11 04:51:53 PM PDT 24 Jul 11 04:51:57 PM PDT 24 151465199 ps
T1041 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3499275587 Jul 11 04:52:08 PM PDT 24 Jul 11 04:52:17 PM PDT 24 114397393 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2558727285 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:48 PM PDT 24 14711754 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.949661726 Jul 11 04:51:34 PM PDT 24 Jul 11 04:51:56 PM PDT 24 329375455 ps
T106 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.329514245 Jul 11 04:51:50 PM PDT 24 Jul 11 04:51:57 PM PDT 24 1092908733 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1119761438 Jul 11 04:51:35 PM PDT 24 Jul 11 04:51:42 PM PDT 24 379283031 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.223226830 Jul 11 04:51:45 PM PDT 24 Jul 11 04:52:05 PM PDT 24 3076408164 ps
T1043 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2589429665 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 58808840 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1866534951 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:08 PM PDT 24 172305346 ps
T149 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3857228309 Jul 11 04:51:56 PM PDT 24 Jul 11 04:52:02 PM PDT 24 1129681244 ps
T1045 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.555101014 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 16352781 ps
T103 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.301160566 Jul 11 04:51:53 PM PDT 24 Jul 11 04:51:59 PM PDT 24 565331895 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3391850188 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:51 PM PDT 24 682715968 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3583601223 Jul 11 04:52:12 PM PDT 24 Jul 11 04:52:23 PM PDT 24 387030132 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.511997937 Jul 11 04:51:36 PM PDT 24 Jul 11 04:51:42 PM PDT 24 114230051 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3553701862 Jul 11 04:51:34 PM PDT 24 Jul 11 04:51:39 PM PDT 24 43599115 ps
T115 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2925929293 Jul 11 04:51:47 PM PDT 24 Jul 11 04:51:51 PM PDT 24 20533951 ps
T1049 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3273682111 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:14 PM PDT 24 39188367 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1222005343 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:08 PM PDT 24 51651414 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3121560090 Jul 11 04:51:53 PM PDT 24 Jul 11 04:51:55 PM PDT 24 16971820 ps
T100 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1299724141 Jul 11 04:52:01 PM PDT 24 Jul 11 04:52:09 PM PDT 24 195545318 ps
T1052 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2643818686 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 16607628 ps
T116 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.592317933 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:49 PM PDT 24 211852146 ps
T150 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2961647051 Jul 11 04:51:39 PM PDT 24 Jul 11 04:51:44 PM PDT 24 569239472 ps
T1053 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3481715362 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 47075163 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4093505919 Jul 11 04:51:37 PM PDT 24 Jul 11 04:51:40 PM PDT 24 35169943 ps
T1055 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2417411984 Jul 11 04:51:55 PM PDT 24 Jul 11 04:52:01 PM PDT 24 670647081 ps
T101 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2600152344 Jul 11 04:52:00 PM PDT 24 Jul 11 04:52:15 PM PDT 24 612590852 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2776878711 Jul 11 04:51:38 PM PDT 24 Jul 11 04:51:44 PM PDT 24 127672463 ps
T1057 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1078169268 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 37579344 ps
T1058 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1491582109 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 49599675 ps
T117 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3504276262 Jul 11 04:52:01 PM PDT 24 Jul 11 04:52:03 PM PDT 24 63657842 ps
T1059 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4079941784 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:06 PM PDT 24 27315111 ps
T1060 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1507083463 Jul 11 04:52:13 PM PDT 24 Jul 11 04:52:21 PM PDT 24 266144476 ps
T1061 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1477492266 Jul 11 04:52:12 PM PDT 24 Jul 11 04:52:20 PM PDT 24 13046335 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3224045682 Jul 11 04:52:05 PM PDT 24 Jul 11 04:52:11 PM PDT 24 37143126 ps
T1063 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2714412799 Jul 11 04:52:17 PM PDT 24 Jul 11 04:52:28 PM PDT 24 37845639 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4053929908 Jul 11 04:51:42 PM PDT 24 Jul 11 04:51:45 PM PDT 24 35344303 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3702580873 Jul 11 04:51:42 PM PDT 24 Jul 11 04:51:45 PM PDT 24 222380269 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1491698783 Jul 11 04:51:43 PM PDT 24 Jul 11 04:51:47 PM PDT 24 23804794 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3438202471 Jul 11 04:51:47 PM PDT 24 Jul 11 04:51:54 PM PDT 24 104095127 ps
T236 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3163668384 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:27 PM PDT 24 291117115 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.980738087 Jul 11 04:51:24 PM PDT 24 Jul 11 04:51:43 PM PDT 24 1212107697 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3934967423 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:06 PM PDT 24 47311224 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3628254414 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:15 PM PDT 24 136450825 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1338542146 Jul 11 04:51:56 PM PDT 24 Jul 11 04:51:58 PM PDT 24 21433322 ps
T151 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.778065546 Jul 11 04:52:17 PM PDT 24 Jul 11 04:52:49 PM PDT 24 3804786454 ps
T1069 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2464249999 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:23 PM PDT 24 81788772 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3926465598 Jul 11 04:51:43 PM PDT 24 Jul 11 04:52:10 PM PDT 24 1284222144 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1811372174 Jul 11 04:51:22 PM PDT 24 Jul 11 04:51:26 PM PDT 24 20278562 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3174782332 Jul 11 04:51:34 PM PDT 24 Jul 11 04:51:38 PM PDT 24 23797323 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2821443370 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:10 PM PDT 24 68456732 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3526705176 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:12 PM PDT 24 149943628 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.810936261 Jul 11 04:52:12 PM PDT 24 Jul 11 04:52:23 PM PDT 24 772458484 ps
T237 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.926908965 Jul 11 04:52:06 PM PDT 24 Jul 11 04:52:33 PM PDT 24 3313290854 ps
T121 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3311885093 Jul 11 04:51:54 PM PDT 24 Jul 11 04:51:58 PM PDT 24 149034417 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4121747871 Jul 11 04:51:33 PM PDT 24 Jul 11 04:51:37 PM PDT 24 360600175 ps
T1077 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.99347338 Jul 11 04:52:10 PM PDT 24 Jul 11 04:52:17 PM PDT 24 24205089 ps
T152 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1015907003 Jul 11 04:51:18 PM PDT 24 Jul 11 04:51:45 PM PDT 24 4353193672 ps
T122 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3352627962 Jul 11 04:52:00 PM PDT 24 Jul 11 04:52:03 PM PDT 24 26830525 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1090862915 Jul 11 04:51:19 PM PDT 24 Jul 11 04:51:24 PM PDT 24 33855730 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1898629000 Jul 11 04:51:54 PM PDT 24 Jul 11 04:51:58 PM PDT 24 90750168 ps
T235 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2875087170 Jul 11 04:51:43 PM PDT 24 Jul 11 04:51:49 PM PDT 24 218120823 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3249941424 Jul 11 04:51:50 PM PDT 24 Jul 11 04:51:53 PM PDT 24 152646176 ps
T1081 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2950519072 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 23044423 ps
T153 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1381953149 Jul 11 04:52:12 PM PDT 24 Jul 11 04:52:22 PM PDT 24 76564106 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.11208882 Jul 11 04:52:05 PM PDT 24 Jul 11 04:52:12 PM PDT 24 89219001 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1658856102 Jul 11 04:51:22 PM PDT 24 Jul 11 04:51:28 PM PDT 24 35972062 ps
T1084 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2231374700 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:08 PM PDT 24 284705237 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3445470036 Jul 11 04:51:44 PM PDT 24 Jul 11 04:52:02 PM PDT 24 674831616 ps
T1085 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2124712300 Jul 11 04:52:15 PM PDT 24 Jul 11 04:52:25 PM PDT 24 33958275 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1105628074 Jul 11 04:51:51 PM PDT 24 Jul 11 04:52:00 PM PDT 24 1117008544 ps
T1087 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3145306829 Jul 11 04:52:13 PM PDT 24 Jul 11 04:52:22 PM PDT 24 18120406 ps
T1088 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1366661784 Jul 11 04:51:54 PM PDT 24 Jul 11 04:51:58 PM PDT 24 227868420 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.374748264 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:50 PM PDT 24 82123759 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1844440337 Jul 11 04:52:15 PM PDT 24 Jul 11 04:52:25 PM PDT 24 19071370 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1902385304 Jul 11 04:51:52 PM PDT 24 Jul 11 04:51:56 PM PDT 24 455403515 ps
T239 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2512716315 Jul 11 04:51:53 PM PDT 24 Jul 11 04:52:13 PM PDT 24 1499608474 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.359812249 Jul 11 04:52:01 PM PDT 24 Jul 11 04:52:03 PM PDT 24 36537459 ps
T1093 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4262602518 Jul 11 04:52:15 PM PDT 24 Jul 11 04:52:25 PM PDT 24 22013984 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1137973932 Jul 11 04:52:13 PM PDT 24 Jul 11 04:52:22 PM PDT 24 84463188 ps
T241 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1181750680 Jul 11 04:51:38 PM PDT 24 Jul 11 04:51:47 PM PDT 24 112020560 ps
T1095 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.477388157 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 13413858 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.157600974 Jul 11 04:51:34 PM PDT 24 Jul 11 04:51:40 PM PDT 24 473267949 ps
T1097 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1806193595 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:06 PM PDT 24 128836470 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3272465402 Jul 11 04:52:18 PM PDT 24 Jul 11 04:52:31 PM PDT 24 113196318 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1208415260 Jul 11 04:51:34 PM PDT 24 Jul 11 04:51:36 PM PDT 24 41718619 ps
T1100 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4139256297 Jul 11 04:51:48 PM PDT 24 Jul 11 04:51:52 PM PDT 24 46784324 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.334674141 Jul 11 04:51:39 PM PDT 24 Jul 11 04:52:07 PM PDT 24 1290974350 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1760408823 Jul 11 04:52:05 PM PDT 24 Jul 11 04:52:12 PM PDT 24 230078054 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2378127874 Jul 11 04:51:35 PM PDT 24 Jul 11 04:51:39 PM PDT 24 57083383 ps
T155 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.72569590 Jul 11 04:52:07 PM PDT 24 Jul 11 04:52:19 PM PDT 24 2559172937 ps
T1104 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.255271887 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:14 PM PDT 24 49377627 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1749029623 Jul 11 04:51:35 PM PDT 24 Jul 11 04:51:38 PM PDT 24 13662311 ps
T242 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.590230329 Jul 11 04:51:51 PM PDT 24 Jul 11 04:52:01 PM PDT 24 375894101 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3522466649 Jul 11 04:51:48 PM PDT 24 Jul 11 04:51:53 PM PDT 24 425427376 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1693103919 Jul 11 04:51:33 PM PDT 24 Jul 11 04:51:47 PM PDT 24 202777855 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1640604244 Jul 11 04:51:44 PM PDT 24 Jul 11 04:52:08 PM PDT 24 294801583 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3462292630 Jul 11 04:51:21 PM PDT 24 Jul 11 04:51:27 PM PDT 24 20649796 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3875023770 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:09 PM PDT 24 318154418 ps
T1111 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1522978567 Jul 11 04:51:54 PM PDT 24 Jul 11 04:51:57 PM PDT 24 22087065 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2412280879 Jul 11 04:51:59 PM PDT 24 Jul 11 04:52:03 PM PDT 24 143870242 ps
T79 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3834459118 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:48 PM PDT 24 285104791 ps
T1113 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1525608825 Jul 11 04:51:43 PM PDT 24 Jul 11 04:51:48 PM PDT 24 83424983 ps
T1114 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1905253545 Jul 11 04:52:14 PM PDT 24 Jul 11 04:52:22 PM PDT 24 82057664 ps
T1115 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.58387638 Jul 11 04:51:53 PM PDT 24 Jul 11 04:51:55 PM PDT 24 14049411 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1431312940 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:04 PM PDT 24 14351903 ps
T1117 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2104479998 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:10 PM PDT 24 150057074 ps
T1118 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.386177534 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:18 PM PDT 24 549959206 ps
T1119 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2795217094 Jul 11 04:52:10 PM PDT 24 Jul 11 04:52:15 PM PDT 24 58395642 ps
T1120 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1051065171 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 25969756 ps
T1121 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1913012787 Jul 11 04:52:00 PM PDT 24 Jul 11 04:52:03 PM PDT 24 48351466 ps
T1122 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3691055403 Jul 11 04:51:41 PM PDT 24 Jul 11 04:51:55 PM PDT 24 616714964 ps
T1123 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1459042266 Jul 11 04:51:55 PM PDT 24 Jul 11 04:51:58 PM PDT 24 427481537 ps
T1124 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2515215333 Jul 11 04:51:59 PM PDT 24 Jul 11 04:52:01 PM PDT 24 92171308 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2838810963 Jul 11 04:51:44 PM PDT 24 Jul 11 04:52:20 PM PDT 24 2177776604 ps
T1126 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.947125475 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:14 PM PDT 24 12530166 ps
T1127 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3429489846 Jul 11 04:51:43 PM PDT 24 Jul 11 04:51:47 PM PDT 24 27083552 ps
T1128 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4101201824 Jul 11 04:52:17 PM PDT 24 Jul 11 04:52:30 PM PDT 24 89638754 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3541267319 Jul 11 04:51:54 PM PDT 24 Jul 11 04:51:57 PM PDT 24 74979127 ps
T1130 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1503877954 Jul 11 04:52:16 PM PDT 24 Jul 11 04:52:26 PM PDT 24 15794989 ps
T80 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.52450381 Jul 11 04:51:36 PM PDT 24 Jul 11 04:51:40 PM PDT 24 186163131 ps
T1131 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3504933430 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:08 PM PDT 24 103604512 ps
T1132 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2948415808 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 23262591 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1081929502 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:53 PM PDT 24 105930988 ps
T240 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2359337119 Jul 11 04:51:35 PM PDT 24 Jul 11 04:51:55 PM PDT 24 1246379790 ps
T1134 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1369350220 Jul 11 04:52:02 PM PDT 24 Jul 11 04:52:11 PM PDT 24 106480422 ps
T1135 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.307476808 Jul 11 04:52:04 PM PDT 24 Jul 11 04:52:10 PM PDT 24 70730344 ps
T1136 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.345655899 Jul 11 04:52:13 PM PDT 24 Jul 11 04:52:23 PM PDT 24 36983345 ps
T1137 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2372618170 Jul 11 04:51:45 PM PDT 24 Jul 11 04:51:51 PM PDT 24 1736184365 ps
T238 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1920115886 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:35 PM PDT 24 1948719781 ps
T1138 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1576963142 Jul 11 04:52:10 PM PDT 24 Jul 11 04:52:16 PM PDT 24 92251232 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1027568123 Jul 11 04:51:44 PM PDT 24 Jul 11 04:51:50 PM PDT 24 198022368 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2754370134 Jul 11 04:51:39 PM PDT 24 Jul 11 04:51:42 PM PDT 24 299555692 ps
T1141 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2914519118 Jul 11 04:51:35 PM PDT 24 Jul 11 04:51:39 PM PDT 24 95961679 ps
T1142 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.855357400 Jul 11 04:52:01 PM PDT 24 Jul 11 04:52:05 PM PDT 24 281248198 ps
T1143 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1282851407 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:18 PM PDT 24 12819135 ps
T1144 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.895162647 Jul 11 04:52:11 PM PDT 24 Jul 11 04:52:20 PM PDT 24 342705276 ps
T1145 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2539297124 Jul 11 04:51:47 PM PDT 24 Jul 11 04:51:54 PM PDT 24 100410466 ps
T1146 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3635328002 Jul 11 04:52:09 PM PDT 24 Jul 11 04:52:14 PM PDT 24 14495358 ps
T1147 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.538370600 Jul 11 04:52:00 PM PDT 24 Jul 11 04:52:02 PM PDT 24 46117630 ps
T1148 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.842439313 Jul 11 04:51:39 PM PDT 24 Jul 11 04:51:41 PM PDT 24 71339008 ps
T1149 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1493603265 Jul 11 04:51:47 PM PDT 24 Jul 11 04:51:52 PM PDT 24 107686858 ps
T1150 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1992983585 Jul 11 04:52:03 PM PDT 24 Jul 11 04:52:11 PM PDT 24 802477950 ps
T1151 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1200876037 Jul 11 04:52:07 PM PDT 24 Jul 11 04:52:13 PM PDT 24 103659021 ps

Test location /workspace/coverage/default/2.spi_device_stress_all.3696066676
Short name T9
Test name
Test status
Simulation time 11003179663 ps
CPU time 64.14 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 258296 kb
Host smart-e5d48bbc-d56c-4870-b8d0-b5e30e866bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696066676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3696066676
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.359085857
Short name T15
Test name
Test status
Simulation time 214468282359 ps
CPU time 502.65 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:40:36 PM PDT 24
Peak memory 290360 kb
Host smart-d36dc51a-8dd6-4129-bfc5-98905ac0e834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359085857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.359085857
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2600152344
Short name T101
Test name
Test status
Simulation time 612590852 ps
CPU time 14.76 seconds
Started Jul 11 04:52:00 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 215388 kb
Host smart-71e6e330-e46e-41fa-ace9-f08c9a367254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600152344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2600152344
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4015971122
Short name T178
Test name
Test status
Simulation time 156763562851 ps
CPU time 759.34 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:46:07 PM PDT 24
Peak memory 264268 kb
Host smart-cde22d0e-b4f1-4944-8e15-b7a77fe68120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015971122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4015971122
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3257287384
Short name T13
Test name
Test status
Simulation time 10264312328 ps
CPU time 113.14 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:35:27 PM PDT 24
Peak memory 265848 kb
Host smart-be98bff7-f174-427d-beb4-e8af3b9280ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257287384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3257287384
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3051503783
Short name T62
Test name
Test status
Simulation time 15250678 ps
CPU time 0.72 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 216960 kb
Host smart-5510bb40-07d1-4a2b-9bab-daf5d63084f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051503783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3051503783
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1297020981
Short name T42
Test name
Test status
Simulation time 5196082914 ps
CPU time 130.92 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:36:30 PM PDT 24
Peak memory 288224 kb
Host smart-ae3d6108-a53c-4679-9386-1a81d1b31cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297020981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1297020981
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4056585156
Short name T105
Test name
Test status
Simulation time 1039394805 ps
CPU time 5.01 seconds
Started Jul 11 04:52:05 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 215700 kb
Host smart-5aee3fdf-0ada-4eb8-b38f-92c6911d67d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056585156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4056585156
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.550035547
Short name T133
Test name
Test status
Simulation time 51918225271 ps
CPU time 500.15 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:42:12 PM PDT 24
Peak memory 279016 kb
Host smart-25550ccd-20f4-4bc0-a964-434ceea645e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550035547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.550035547
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3597468203
Short name T48
Test name
Test status
Simulation time 292642447724 ps
CPU time 552.87 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:42:02 PM PDT 24
Peak memory 257536 kb
Host smart-6127c625-bffd-4af8-8800-7634c318b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597468203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3597468203
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3627555608
Short name T175
Test name
Test status
Simulation time 76845672537 ps
CPU time 727.56 seconds
Started Jul 11 04:32:42 PM PDT 24
Finished Jul 11 04:45:16 PM PDT 24
Peak memory 274952 kb
Host smart-a20a276b-ffeb-4532-ab57-561f87fc9408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627555608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3627555608
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.723575764
Short name T51
Test name
Test status
Simulation time 234311678905 ps
CPU time 460.42 seconds
Started Jul 11 04:33:44 PM PDT 24
Finished Jul 11 04:41:45 PM PDT 24
Peak memory 282856 kb
Host smart-797a69cf-082c-4cb2-8742-001195a2ef33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723575764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.723575764
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.512441801
Short name T336
Test name
Test status
Simulation time 77371785 ps
CPU time 0.72 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:04 PM PDT 24
Peak memory 206284 kb
Host smart-82351aaa-989e-4dd5-bf47-25971ab335e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512441801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.512441801
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4037102197
Short name T142
Test name
Test status
Simulation time 1943970358 ps
CPU time 18.47 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:32:14 PM PDT 24
Peak memory 233732 kb
Host smart-1f7b835d-b590-4f7a-8d39-883882c4573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037102197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4037102197
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4186445619
Short name T30
Test name
Test status
Simulation time 10109641408 ps
CPU time 60.43 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 257320 kb
Host smart-b856bcae-6ea4-42fb-a82f-3ebe34671047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186445619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4186445619
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.198882124
Short name T77
Test name
Test status
Simulation time 23172097 ps
CPU time 1.33 seconds
Started Jul 11 04:51:36 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 207264 kb
Host smart-1ce3bc6a-92fc-4397-87e7-ff43975ee395
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198882124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.198882124
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2117687792
Short name T181
Test name
Test status
Simulation time 7199328255 ps
CPU time 79.23 seconds
Started Jul 11 04:33:45 PM PDT 24
Finished Jul 11 04:35:24 PM PDT 24
Peak memory 258424 kb
Host smart-0d98f4ea-5186-4518-9cba-967b352730c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117687792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2117687792
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3895606630
Short name T192
Test name
Test status
Simulation time 3050600033 ps
CPU time 76.95 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:33:30 PM PDT 24
Peak memory 265876 kb
Host smart-d47080f6-d6d3-4e1e-8f7e-9555ea97d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895606630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3895606630
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1360014394
Short name T679
Test name
Test status
Simulation time 102587198 ps
CPU time 1 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:32:40 PM PDT 24
Peak memory 218872 kb
Host smart-8f26e1c6-1d6a-4880-9e90-5fe77b7e9994
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360014394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1360014394
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2016683537
Short name T125
Test name
Test status
Simulation time 107939509010 ps
CPU time 239.91 seconds
Started Jul 11 04:32:56 PM PDT 24
Finished Jul 11 04:37:19 PM PDT 24
Peak memory 250140 kb
Host smart-346e5003-f1b0-4539-ba37-4bcf32a11d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016683537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2016683537
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2991071643
Short name T67
Test name
Test status
Simulation time 383638289 ps
CPU time 1.15 seconds
Started Jul 11 04:31:26 PM PDT 24
Finished Jul 11 04:31:47 PM PDT 24
Peak memory 236292 kb
Host smart-016a15c4-1be9-43d0-a954-01842eed9d57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991071643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2991071643
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1739188176
Short name T186
Test name
Test status
Simulation time 63225929909 ps
CPU time 186.4 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:36:44 PM PDT 24
Peak memory 253968 kb
Host smart-ed0a2c2f-77a7-4eb6-bf31-e4b8f03bf822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739188176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1739188176
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2403355747
Short name T160
Test name
Test status
Simulation time 171739000983 ps
CPU time 436.31 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:41:01 PM PDT 24
Peak memory 266220 kb
Host smart-213f971e-48aa-4fbd-b422-e7b94ca7aec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403355747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2403355747
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3932498739
Short name T211
Test name
Test status
Simulation time 273824046326 ps
CPU time 456.7 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:41:18 PM PDT 24
Peak memory 252600 kb
Host smart-d23a9a72-ab3b-45e5-a591-195cae71fbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932498739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3932498739
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.758357513
Short name T134
Test name
Test status
Simulation time 98688002097 ps
CPU time 562.16 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:43:46 PM PDT 24
Peak memory 286856 kb
Host smart-816e8abb-f70e-4a21-88a7-85c53d39c40e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758357513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.758357513
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1973922225
Short name T29
Test name
Test status
Simulation time 303962132 ps
CPU time 0.83 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:21 PM PDT 24
Peak memory 206908 kb
Host smart-40ae7871-7d71-4205-b2e4-6a4561998f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973922225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1973922225
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2974093043
Short name T19
Test name
Test status
Simulation time 51564147590 ps
CPU time 475.75 seconds
Started Jul 11 04:31:51 PM PDT 24
Finished Jul 11 04:40:10 PM PDT 24
Peak memory 266708 kb
Host smart-78d68b18-05f5-4904-b3a9-0a7d4fd31eea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974093043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2974093043
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1319340803
Short name T928
Test name
Test status
Simulation time 14668617727 ps
CPU time 188.21 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 258080 kb
Host smart-6214c445-9ec0-4de3-be92-c3d0de4c5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319340803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1319340803
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3184865740
Short name T183
Test name
Test status
Simulation time 66557179920 ps
CPU time 678.88 seconds
Started Jul 11 04:33:45 PM PDT 24
Finished Jul 11 04:45:24 PM PDT 24
Peak memory 258484 kb
Host smart-959f88a8-188e-40b3-8a44-bd169c583b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184865740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3184865740
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2283026315
Short name T279
Test name
Test status
Simulation time 2301306919 ps
CPU time 14.3 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:34:38 PM PDT 24
Peak memory 225600 kb
Host smart-e46af8ff-d96d-4f38-94f6-e6c8c310d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283026315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2283026315
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.329514245
Short name T106
Test name
Test status
Simulation time 1092908733 ps
CPU time 4.63 seconds
Started Jul 11 04:51:50 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 215700 kb
Host smart-3a2688e4-cb09-4b27-8066-4cce30fed311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329514245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.329514245
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1015907003
Short name T152
Test name
Test status
Simulation time 4353193672 ps
CPU time 25.48 seconds
Started Jul 11 04:51:18 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 215588 kb
Host smart-e02af77c-2bb8-48f1-a84f-938b819abfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015907003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1015907003
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3130283857
Short name T368
Test name
Test status
Simulation time 27722169711 ps
CPU time 122.29 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:35:36 PM PDT 24
Peak memory 250348 kb
Host smart-430419e9-33d8-4b9d-80a0-b406acb79d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130283857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3130283857
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.271678283
Short name T288
Test name
Test status
Simulation time 1940098523 ps
CPU time 27.12 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:34:12 PM PDT 24
Peak memory 217504 kb
Host smart-dbc78c13-bb81-4e05-9775-6f266f6070de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271678283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.271678283
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2783279598
Short name T11
Test name
Test status
Simulation time 118635585 ps
CPU time 2.85 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:25 PM PDT 24
Peak memory 233620 kb
Host smart-4932fd8a-16e0-438b-8aba-0062a528afdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783279598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2783279598
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2719247758
Short name T99
Test name
Test status
Simulation time 290814751 ps
CPU time 20.27 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:25 PM PDT 24
Peak memory 215628 kb
Host smart-78d763ec-03c8-46a3-977b-6c11fad2cf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719247758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2719247758
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.888876861
Short name T227
Test name
Test status
Simulation time 23403450606 ps
CPU time 225.92 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:37:59 PM PDT 24
Peak memory 257380 kb
Host smart-0c38a601-2654-4fb8-9bae-06b5fa421397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888876861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.888876861
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1131949415
Short name T285
Test name
Test status
Simulation time 2344380586 ps
CPU time 10 seconds
Started Jul 11 04:34:11 PM PDT 24
Finished Jul 11 04:34:45 PM PDT 24
Peak memory 225528 kb
Host smart-7d7ab4a2-76bd-4c80-b195-968c007c542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131949415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1131949415
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2693866447
Short name T82
Test name
Test status
Simulation time 20848890083 ps
CPU time 71.39 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:34:22 PM PDT 24
Peak memory 250356 kb
Host smart-bd19ba8f-0651-4cb1-a3d4-05f2375068b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693866447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2693866447
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.364007942
Short name T212
Test name
Test status
Simulation time 5659745034 ps
CPU time 79.62 seconds
Started Jul 11 04:31:41 PM PDT 24
Finished Jul 11 04:33:20 PM PDT 24
Peak memory 253600 kb
Host smart-58c44a1a-b3a1-4339-b8aa-a7018e219c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364007942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.364007942
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1175895255
Short name T171
Test name
Test status
Simulation time 6679629703 ps
CPU time 81.72 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:34:04 PM PDT 24
Peak memory 250280 kb
Host smart-2192d731-2b83-4b3e-aa3f-025ac689ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175895255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1175895255
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2221790262
Short name T246
Test name
Test status
Simulation time 314383652 ps
CPU time 2.34 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 225440 kb
Host smart-b2e4a7e2-9da5-4484-b304-abbcf3880abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221790262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2221790262
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1328060870
Short name T304
Test name
Test status
Simulation time 34788025237 ps
CPU time 315.88 seconds
Started Jul 11 04:32:33 PM PDT 24
Finished Jul 11 04:38:19 PM PDT 24
Peak memory 250712 kb
Host smart-cbebf9c2-a088-495a-ac2c-096c4c551ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328060870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1328060870
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1034285266
Short name T206
Test name
Test status
Simulation time 31263303021 ps
CPU time 212.33 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:36:00 PM PDT 24
Peak memory 253556 kb
Host smart-ce7359e5-f2e4-4b76-a8a2-a245ef3a8b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034285266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1034285266
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3694616916
Short name T200
Test name
Test status
Simulation time 6208657233 ps
CPU time 13.52 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 225604 kb
Host smart-f216d641-ca16-4fe0-a551-a8b9c3a8f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694616916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3694616916
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.157600974
Short name T1096
Test name
Test status
Simulation time 473267949 ps
CPU time 3.46 seconds
Started Jul 11 04:51:34 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 215616 kb
Host smart-8cedcb1f-299d-4cf6-8eea-87e2818bab29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157600974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.157600974
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1127362003
Short name T36
Test name
Test status
Simulation time 733428777295 ps
CPU time 490.12 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:40:43 PM PDT 24
Peak memory 291064 kb
Host smart-7ef5d189-e540-4429-9deb-a4b03c3cabcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127362003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1127362003
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.980738087
Short name T119
Test name
Test status
Simulation time 1212107697 ps
CPU time 14.71 seconds
Started Jul 11 04:51:24 PM PDT 24
Finished Jul 11 04:51:43 PM PDT 24
Peak memory 215488 kb
Host smart-5302b257-a1f2-47d6-bac2-49d356fc743d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980738087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.980738087
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.438405941
Short name T1037
Test name
Test status
Simulation time 4639366567 ps
CPU time 24.54 seconds
Started Jul 11 04:51:19 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 207180 kb
Host smart-ba45e88f-7f9c-408c-b467-bc2c3ab532f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438405941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.438405941
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2263333984
Short name T1033
Test name
Test status
Simulation time 50429321 ps
CPU time 0.95 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 206752 kb
Host smart-96028f37-fd80-4fe1-8b33-90dc13fdfab3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263333984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2263333984
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2776878711
Short name T1056
Test name
Test status
Simulation time 127672463 ps
CPU time 3.63 seconds
Started Jul 11 04:51:38 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 216996 kb
Host smart-cc99ecce-3f07-444a-963a-b17442472546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776878711 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2776878711
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3462292630
Short name T1109
Test name
Test status
Simulation time 20649796 ps
CPU time 1.21 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 207164 kb
Host smart-a007a293-aaa0-4429-978c-fe3aefcb74f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462292630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
462292630
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3843500866
Short name T1040
Test name
Test status
Simulation time 14672260 ps
CPU time 0.75 seconds
Started Jul 11 04:51:22 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 204196 kb
Host smart-3772aec6-c23d-4ef5-99a8-ce20cf4d7e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843500866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
843500866
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1658856102
Short name T1083
Test name
Test status
Simulation time 35972062 ps
CPU time 1.67 seconds
Started Jul 11 04:51:22 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 215456 kb
Host smart-33598031-6cb2-477d-9b0a-39a478be02ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658856102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1658856102
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1811372174
Short name T1071
Test name
Test status
Simulation time 20278562 ps
CPU time 0.68 seconds
Started Jul 11 04:51:22 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 204108 kb
Host smart-59bd022c-61d6-44d1-95b8-c88309ae1f69
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811372174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1811372174
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.511997937
Short name T1047
Test name
Test status
Simulation time 114230051 ps
CPU time 2.94 seconds
Started Jul 11 04:51:36 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 215496 kb
Host smart-54e5cbe7-c320-42c7-bd18-31a989d45c9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511997937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.511997937
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1090862915
Short name T1078
Test name
Test status
Simulation time 33855730 ps
CPU time 2.09 seconds
Started Jul 11 04:51:19 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 216800 kb
Host smart-648fde06-1a82-4c85-845c-5d3c3fb04737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090862915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
090862915
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.949661726
Short name T113
Test name
Test status
Simulation time 329375455 ps
CPU time 20.83 seconds
Started Jul 11 04:51:34 PM PDT 24
Finished Jul 11 04:51:56 PM PDT 24
Peak memory 215456 kb
Host smart-4422b6b2-73b9-4c85-a560-21010b32793e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949661726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.949661726
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3691055403
Short name T1122
Test name
Test status
Simulation time 616714964 ps
CPU time 13.27 seconds
Started Jul 11 04:51:41 PM PDT 24
Finished Jul 11 04:51:55 PM PDT 24
Peak memory 215304 kb
Host smart-f1bb5c6e-ccad-429e-98f9-58049547eb9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691055403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3691055403
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4121747871
Short name T1076
Test name
Test status
Simulation time 360600175 ps
CPU time 2.52 seconds
Started Jul 11 04:51:33 PM PDT 24
Finished Jul 11 04:51:37 PM PDT 24
Peak memory 216400 kb
Host smart-071a8ba2-0dcb-4872-a9dc-a82e2813fb97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121747871 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4121747871
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2914519118
Short name T1141
Test name
Test status
Simulation time 95961679 ps
CPU time 1.78 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:39 PM PDT 24
Peak memory 215512 kb
Host smart-34a1b7c6-7b98-498b-9205-304625707f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914519118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
914519118
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.842439313
Short name T1148
Test name
Test status
Simulation time 71339008 ps
CPU time 0.74 seconds
Started Jul 11 04:51:39 PM PDT 24
Finished Jul 11 04:51:41 PM PDT 24
Peak memory 203988 kb
Host smart-55e9766a-0e72-4d31-96e2-e033d8c86444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842439313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.842439313
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2378127874
Short name T1103
Test name
Test status
Simulation time 57083383 ps
CPU time 1.22 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:39 PM PDT 24
Peak memory 215532 kb
Host smart-d242aba5-d42b-4429-b3f4-6322d75ecef1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378127874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2378127874
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1749029623
Short name T1105
Test name
Test status
Simulation time 13662311 ps
CPU time 0.65 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:38 PM PDT 24
Peak memory 203796 kb
Host smart-a0f41596-6401-401f-89bd-a96f5eff328c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749029623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1749029623
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2490515494
Short name T139
Test name
Test status
Simulation time 543316143 ps
CPU time 3.04 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:41 PM PDT 24
Peak memory 215456 kb
Host smart-2111af87-96b0-44b3-bdbe-47fb6f54ee36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490515494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2490515494
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1693103919
Short name T1107
Test name
Test status
Simulation time 202777855 ps
CPU time 12.86 seconds
Started Jul 11 04:51:33 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 215352 kb
Host smart-912d3d5f-d944-4de7-8bb9-1899f6ec3aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693103919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1693103919
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2482640049
Short name T109
Test name
Test status
Simulation time 500117274 ps
CPU time 3.99 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 218360 kb
Host smart-d35269f5-dfaf-4620-be4b-0c929cbf72fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482640049 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2482640049
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.538370600
Short name T1147
Test name
Test status
Simulation time 46117630 ps
CPU time 2.11 seconds
Started Jul 11 04:52:00 PM PDT 24
Finished Jul 11 04:52:02 PM PDT 24
Peak memory 215528 kb
Host smart-26b75725-6031-4a7b-b61b-7997d73b862a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538370600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.538370600
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3121560090
Short name T1051
Test name
Test status
Simulation time 16971820 ps
CPU time 0.74 seconds
Started Jul 11 04:51:53 PM PDT 24
Finished Jul 11 04:51:55 PM PDT 24
Peak memory 204248 kb
Host smart-910c4429-9dfa-498f-99bf-66a5b7dbe40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121560090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3121560090
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3541267319
Short name T1129
Test name
Test status
Simulation time 74979127 ps
CPU time 1.87 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 215404 kb
Host smart-bcd83691-a325-4949-a710-29bb79902970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541267319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3541267319
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2515215333
Short name T1124
Test name
Test status
Simulation time 92171308 ps
CPU time 1.5 seconds
Started Jul 11 04:51:59 PM PDT 24
Finished Jul 11 04:52:01 PM PDT 24
Peak memory 215696 kb
Host smart-7a697515-5dc7-407c-be28-21d10a484a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515215333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2515215333
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1105628074
Short name T1086
Test name
Test status
Simulation time 1117008544 ps
CPU time 7.96 seconds
Started Jul 11 04:51:51 PM PDT 24
Finished Jul 11 04:52:00 PM PDT 24
Peak memory 215760 kb
Host smart-4b751a37-fd7c-41b3-80b1-7be1929726fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105628074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1105628074
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3504933430
Short name T1131
Test name
Test status
Simulation time 103604512 ps
CPU time 2.65 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 217896 kb
Host smart-57475166-5169-4da5-b644-78878c576642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504933430 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3504933430
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2231374700
Short name T1084
Test name
Test status
Simulation time 284705237 ps
CPU time 1.88 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 207204 kb
Host smart-738f61e9-7c03-4790-bacf-e3543c394eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231374700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2231374700
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1222005343
Short name T1050
Test name
Test status
Simulation time 51651414 ps
CPU time 0.76 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 203948 kb
Host smart-a2a5b571-b6a6-48be-a7f7-de9150255d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222005343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1222005343
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3499275587
Short name T1041
Test name
Test status
Simulation time 114397393 ps
CPU time 3.9 seconds
Started Jul 11 04:52:08 PM PDT 24
Finished Jul 11 04:52:17 PM PDT 24
Peak memory 215460 kb
Host smart-73be2d3d-2c24-43ae-8a3c-e23747d073ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499275587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3499275587
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2821443370
Short name T1073
Test name
Test status
Simulation time 68456732 ps
CPU time 1.28 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 215700 kb
Host smart-f9efd756-a97e-4f54-aa94-5a0db6fcd3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821443370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2821443370
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3163668384
Short name T236
Test name
Test status
Simulation time 291117115 ps
CPU time 18.19 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:27 PM PDT 24
Peak memory 215416 kb
Host smart-15b8f7b3-bde9-4fcc-a29b-4c1444440da9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163668384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3163668384
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3934967423
Short name T1067
Test name
Test status
Simulation time 47311224 ps
CPU time 1.87 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 215420 kb
Host smart-b6bac20b-1183-4683-b61a-4ae66a8d0ac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934967423 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3934967423
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3628254414
Short name T120
Test name
Test status
Simulation time 136450825 ps
CPU time 2.3 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 215324 kb
Host smart-8b54bc20-b6f6-4b5d-b5e1-529d7d034598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628254414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3628254414
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3224045682
Short name T1062
Test name
Test status
Simulation time 37143126 ps
CPU time 0.68 seconds
Started Jul 11 04:52:05 PM PDT 24
Finished Jul 11 04:52:11 PM PDT 24
Peak memory 203888 kb
Host smart-c3030f04-3ec5-49f3-8d54-34f1ade0cc9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224045682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3224045682
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3875023770
Short name T1110
Test name
Test status
Simulation time 318154418 ps
CPU time 4.03 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:09 PM PDT 24
Peak memory 215312 kb
Host smart-2b868a60-6d76-4ef3-8328-57e19c4638cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875023770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3875023770
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1200876037
Short name T1151
Test name
Test status
Simulation time 103659021 ps
CPU time 1.44 seconds
Started Jul 11 04:52:07 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 215748 kb
Host smart-68c3b910-2a99-406f-a67d-f116e6f90b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200876037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1200876037
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1369350220
Short name T1134
Test name
Test status
Simulation time 106480422 ps
CPU time 6.46 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:11 PM PDT 24
Peak memory 215612 kb
Host smart-4e482cc3-8cd3-4f72-9b15-bc25e999945d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369350220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1369350220
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1137973932
Short name T1094
Test name
Test status
Simulation time 84463188 ps
CPU time 1.66 seconds
Started Jul 11 04:52:13 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 215528 kb
Host smart-d679fd47-6d54-4dcc-9401-d92407744841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137973932 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1137973932
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.307476808
Short name T1135
Test name
Test status
Simulation time 70730344 ps
CPU time 1.15 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 215416 kb
Host smart-a56c7d4b-304f-44c1-aea7-eb6a88eee6b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307476808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.307476808
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2032815222
Short name T1030
Test name
Test status
Simulation time 23989282 ps
CPU time 0.76 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 203956 kb
Host smart-331d86ce-8219-41a5-9d2d-03dbe3e43b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032815222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2032815222
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4079941784
Short name T1059
Test name
Test status
Simulation time 27315111 ps
CPU time 1.81 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 215376 kb
Host smart-4a9e94dc-b0ec-4db9-89a4-7c74e528298e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079941784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4079941784
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1913012787
Short name T1121
Test name
Test status
Simulation time 48351466 ps
CPU time 1.69 seconds
Started Jul 11 04:52:00 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 215656 kb
Host smart-ef1d19f4-3311-45b9-910d-f372bbf083af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913012787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1913012787
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1866534951
Short name T1044
Test name
Test status
Simulation time 172305346 ps
CPU time 1.92 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 216520 kb
Host smart-9b4efdc1-9228-4fa5-8006-d2230b94fc14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866534951 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1866534951
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3352627962
Short name T122
Test name
Test status
Simulation time 26830525 ps
CPU time 1.86 seconds
Started Jul 11 04:52:00 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 207184 kb
Host smart-fd78e933-44af-4ce2-a63e-3f229a49fd26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352627962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3352627962
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1824881650
Short name T1027
Test name
Test status
Simulation time 187403379 ps
CPU time 0.7 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 204308 kb
Host smart-ce9e8f2e-eb54-43d7-9d36-b696c616c79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824881650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1824881650
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2104479998
Short name T1117
Test name
Test status
Simulation time 150057074 ps
CPU time 1.69 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 215520 kb
Host smart-ff3b4d8e-7b0d-4f81-ab54-ca1724251634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104479998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2104479998
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.386177534
Short name T1118
Test name
Test status
Simulation time 549959206 ps
CPU time 15.05 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 215636 kb
Host smart-77ca4045-ee3f-4b85-842f-397db9c34346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386177534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.386177534
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3326065902
Short name T111
Test name
Test status
Simulation time 35459224 ps
CPU time 2.36 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:07 PM PDT 24
Peak memory 217060 kb
Host smart-6c8cb7ef-a8a8-4914-bea3-6cc9ceb6d8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326065902 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3326065902
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1806193595
Short name T1097
Test name
Test status
Simulation time 128836470 ps
CPU time 1.4 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 215516 kb
Host smart-42502ace-9990-4ecd-b05c-267f4a0ddc18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806193595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1806193595
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3162431999
Short name T1028
Test name
Test status
Simulation time 17613948 ps
CPU time 0.81 seconds
Started Jul 11 04:52:06 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 204232 kb
Host smart-4866998b-5530-4a11-8230-5a6cdef6ecd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162431999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3162431999
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3526705176
Short name T1074
Test name
Test status
Simulation time 149943628 ps
CPU time 4.2 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 215492 kb
Host smart-8df9de45-2ca2-42ea-b710-7e19c816e650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526705176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3526705176
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.855357400
Short name T1142
Test name
Test status
Simulation time 281248198 ps
CPU time 2.57 seconds
Started Jul 11 04:52:01 PM PDT 24
Finished Jul 11 04:52:05 PM PDT 24
Peak memory 215936 kb
Host smart-ddd77fb5-0b2c-4f36-9b6a-771dd36e74c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855357400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.855357400
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.926908965
Short name T237
Test name
Test status
Simulation time 3313290854 ps
CPU time 21.98 seconds
Started Jul 11 04:52:06 PM PDT 24
Finished Jul 11 04:52:33 PM PDT 24
Peak memory 215920 kb
Host smart-4de0f816-808d-4714-bfd5-fd5ca0cc4b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926908965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.926908965
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2409904036
Short name T96
Test name
Test status
Simulation time 55849646 ps
CPU time 4.03 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 219092 kb
Host smart-f4d61630-064a-433d-a2a0-529aaf27e91a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409904036 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2409904036
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2050840003
Short name T112
Test name
Test status
Simulation time 38927685 ps
CPU time 2.22 seconds
Started Jul 11 04:52:05 PM PDT 24
Finished Jul 11 04:52:11 PM PDT 24
Peak memory 215408 kb
Host smart-918f5ab6-9bb7-4ec9-acf0-f5328602aa33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050840003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2050840003
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.359812249
Short name T1092
Test name
Test status
Simulation time 36537459 ps
CPU time 0.75 seconds
Started Jul 11 04:52:01 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 203936 kb
Host smart-bb4d3448-f556-468c-88a9-6295d58c241a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359812249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.359812249
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1760408823
Short name T1102
Test name
Test status
Simulation time 230078054 ps
CPU time 2.91 seconds
Started Jul 11 04:52:05 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 215388 kb
Host smart-60e150ef-4e68-418e-b340-60d6435f7b42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760408823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1760408823
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1028337022
Short name T107
Test name
Test status
Simulation time 126982714 ps
CPU time 3.59 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 215724 kb
Host smart-15ad4e25-aedb-4c3d-b22f-8edd3c6cfe0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028337022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1028337022
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.72569590
Short name T155
Test name
Test status
Simulation time 2559172937 ps
CPU time 7.26 seconds
Started Jul 11 04:52:07 PM PDT 24
Finished Jul 11 04:52:19 PM PDT 24
Peak memory 216660 kb
Host smart-0c828e0b-7a39-44a2-bb27-6a9b62a2cbd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72569590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.72569590
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1992983585
Short name T1150
Test name
Test status
Simulation time 802477950 ps
CPU time 3.78 seconds
Started Jul 11 04:52:03 PM PDT 24
Finished Jul 11 04:52:11 PM PDT 24
Peak memory 216944 kb
Host smart-9d004ff5-7ad9-448a-9762-7a187806ab54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992983585 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1992983585
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3504276262
Short name T117
Test name
Test status
Simulation time 63657842 ps
CPU time 1.19 seconds
Started Jul 11 04:52:01 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 215424 kb
Host smart-075dbca0-922b-48db-9f26-c6a94eb3df4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504276262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3504276262
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1431312940
Short name T1116
Test name
Test status
Simulation time 14351903 ps
CPU time 0.8 seconds
Started Jul 11 04:52:02 PM PDT 24
Finished Jul 11 04:52:04 PM PDT 24
Peak memory 204032 kb
Host smart-75c1005c-dfcd-4cf3-a783-c36fbb2ccfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431312940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1431312940
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.11208882
Short name T1082
Test name
Test status
Simulation time 89219001 ps
CPU time 1.64 seconds
Started Jul 11 04:52:05 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 215396 kb
Host smart-a0dbdbb0-c4da-445b-b6bd-c4c4a145776c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sp
i_device_same_csr_outstanding.11208882
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2606061383
Short name T98
Test name
Test status
Simulation time 289255763 ps
CPU time 4.98 seconds
Started Jul 11 04:52:04 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 216660 kb
Host smart-8718885b-5c01-4863-aacd-56f17b6ff70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606061383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2606061383
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1299724141
Short name T100
Test name
Test status
Simulation time 195545318 ps
CPU time 6.55 seconds
Started Jul 11 04:52:01 PM PDT 24
Finished Jul 11 04:52:09 PM PDT 24
Peak memory 215572 kb
Host smart-f72082b4-ca96-4d40-a744-e1f44aba3e22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299724141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1299724141
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4101201824
Short name T1128
Test name
Test status
Simulation time 89638754 ps
CPU time 2.77 seconds
Started Jul 11 04:52:17 PM PDT 24
Finished Jul 11 04:52:30 PM PDT 24
Peak memory 216604 kb
Host smart-0b0ed7b2-5797-4842-b1c7-f4cadbabd619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101201824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4101201824
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1381953149
Short name T153
Test name
Test status
Simulation time 76564106 ps
CPU time 2.02 seconds
Started Jul 11 04:52:12 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 219512 kb
Host smart-60d4b4db-2c1a-4ace-acde-c3ca83fb1881
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381953149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1381953149
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1576963142
Short name T1138
Test name
Test status
Simulation time 92251232 ps
CPU time 0.7 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:16 PM PDT 24
Peak memory 203888 kb
Host smart-aec68dd2-922b-413d-9793-4b90acf7a7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576963142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1576963142
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3272465402
Short name T1098
Test name
Test status
Simulation time 113196318 ps
CPU time 3.29 seconds
Started Jul 11 04:52:18 PM PDT 24
Finished Jul 11 04:52:31 PM PDT 24
Peak memory 215504 kb
Host smart-65349720-3f4d-41c4-b19f-221e717b6a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272465402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3272465402
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3583601223
Short name T156
Test name
Test status
Simulation time 387030132 ps
CPU time 4.54 seconds
Started Jul 11 04:52:12 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 215756 kb
Host smart-1ec697d0-b6c8-455e-9653-4d980cb9ca5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583601223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3583601223
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.778065546
Short name T151
Test name
Test status
Simulation time 3804786454 ps
CPU time 22.19 seconds
Started Jul 11 04:52:17 PM PDT 24
Finished Jul 11 04:52:49 PM PDT 24
Peak memory 215468 kb
Host smart-1a8d15aa-4cb8-40a6-80b7-92749fb80337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778065546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.778065546
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2275710813
Short name T110
Test name
Test status
Simulation time 368761741 ps
CPU time 1.83 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:19 PM PDT 24
Peak memory 215396 kb
Host smart-b5be1f78-a7a2-4006-b8a0-4c24a0ba4599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275710813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2275710813
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.345655899
Short name T1136
Test name
Test status
Simulation time 36983345 ps
CPU time 2.45 seconds
Started Jul 11 04:52:13 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 215372 kb
Host smart-5aa867a8-0445-4797-ab78-7410fc8bb4f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345655899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.345655899
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1844440337
Short name T1090
Test name
Test status
Simulation time 19071370 ps
CPU time 0.8 seconds
Started Jul 11 04:52:15 PM PDT 24
Finished Jul 11 04:52:25 PM PDT 24
Peak memory 204128 kb
Host smart-de04c372-71bf-4da5-8729-71e69923cdad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844440337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1844440337
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.810936261
Short name T1075
Test name
Test status
Simulation time 772458484 ps
CPU time 4.38 seconds
Started Jul 11 04:52:12 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 215344 kb
Host smart-fb6dbe91-8382-4124-9333-c764baf20bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810936261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.810936261
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.895162647
Short name T1144
Test name
Test status
Simulation time 342705276 ps
CPU time 4.43 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:20 PM PDT 24
Peak memory 215640 kb
Host smart-b5d44b8d-cc35-4590-96df-1a44d6bec559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895162647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.895162647
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1920115886
Short name T238
Test name
Test status
Simulation time 1948719781 ps
CPU time 21.88 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:35 PM PDT 24
Peak memory 215700 kb
Host smart-c56abe4c-1eae-4c28-a94b-46eb29fa88b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920115886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1920115886
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1470357802
Short name T1035
Test name
Test status
Simulation time 254815386 ps
CPU time 7.06 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 215516 kb
Host smart-1aa1ce38-5b36-48e7-874c-05ccaab10e87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470357802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1470357802
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.334674141
Short name T1101
Test name
Test status
Simulation time 1290974350 ps
CPU time 26.22 seconds
Started Jul 11 04:51:39 PM PDT 24
Finished Jul 11 04:52:07 PM PDT 24
Peak memory 207224 kb
Host smart-08369054-a980-49db-a465-458e09bce97a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334674141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.334674141
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.52450381
Short name T80
Test name
Test status
Simulation time 186163131 ps
CPU time 1.46 seconds
Started Jul 11 04:51:36 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 207212 kb
Host smart-9953a0b9-e7aa-4c66-8be8-2b43f45f5548
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52450381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
hw_reset.52450381
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3553701862
Short name T1048
Test name
Test status
Simulation time 43599115 ps
CPU time 2.74 seconds
Started Jul 11 04:51:34 PM PDT 24
Finished Jul 11 04:51:39 PM PDT 24
Peak memory 218192 kb
Host smart-8c2f5beb-5e8a-4eb0-8ee4-654bfae0d5c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553701862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3553701862
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3174782332
Short name T1072
Test name
Test status
Simulation time 23797323 ps
CPU time 1.14 seconds
Started Jul 11 04:51:34 PM PDT 24
Finished Jul 11 04:51:38 PM PDT 24
Peak memory 207500 kb
Host smart-97345b82-f8f7-4b89-8eb8-f86a20caba80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174782332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
174782332
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4093505919
Short name T1054
Test name
Test status
Simulation time 35169943 ps
CPU time 0.69 seconds
Started Jul 11 04:51:37 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 204176 kb
Host smart-ce86eb75-c5d2-478c-ac2d-3388942b306b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093505919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
093505919
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2754370134
Short name T1140
Test name
Test status
Simulation time 299555692 ps
CPU time 1.35 seconds
Started Jul 11 04:51:39 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 215424 kb
Host smart-db49de12-044d-4523-9088-0eb7e7b114b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754370134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2754370134
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1623802197
Short name T1039
Test name
Test status
Simulation time 22045976 ps
CPU time 0.68 seconds
Started Jul 11 04:51:33 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 203880 kb
Host smart-cd20f90d-d48f-446c-819b-b3a1b14e1f9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623802197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1623802197
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2961647051
Short name T150
Test name
Test status
Simulation time 569239472 ps
CPU time 3.11 seconds
Started Jul 11 04:51:39 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 215780 kb
Host smart-6d4b47db-1aeb-4387-b516-3a9986501f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961647051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2961647051
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1119761438
Short name T108
Test name
Test status
Simulation time 379283031 ps
CPU time 3.78 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 217640 kb
Host smart-238885f5-f885-4399-8f7b-49d8c8c9c262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119761438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
119761438
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1181750680
Short name T241
Test name
Test status
Simulation time 112020560 ps
CPU time 6.86 seconds
Started Jul 11 04:51:38 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 215320 kb
Host smart-8cd35bce-5e07-4fce-b8f6-44fdc3844c71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181750680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1181750680
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2939864260
Short name T1036
Test name
Test status
Simulation time 150793950 ps
CPU time 0.73 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:16 PM PDT 24
Peak memory 203968 kb
Host smart-8ba5df71-4272-495a-bd74-2e6de4e4464a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939864260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2939864260
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1905253545
Short name T1114
Test name
Test status
Simulation time 82057664 ps
CPU time 0.77 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 203948 kb
Host smart-bc543642-0062-4724-a4e4-dd04e7a6cb52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905253545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1905253545
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.99347338
Short name T1077
Test name
Test status
Simulation time 24205089 ps
CPU time 0.7 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:17 PM PDT 24
Peak memory 204164 kb
Host smart-c920a6ea-0b04-458d-b955-72bdcb17eeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99347338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.99347338
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2948415808
Short name T1132
Test name
Test status
Simulation time 23262591 ps
CPU time 0.71 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 203904 kb
Host smart-ead7670c-d51e-457c-946e-fe952d5c51c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948415808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2948415808
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2643818686
Short name T1052
Test name
Test status
Simulation time 16607628 ps
CPU time 0.78 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 203972 kb
Host smart-8b018089-0d60-4668-8e70-40b08b842386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643818686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2643818686
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3273682111
Short name T1049
Test name
Test status
Simulation time 39188367 ps
CPU time 0.67 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:14 PM PDT 24
Peak memory 203868 kb
Host smart-34140d44-9308-4f0f-b762-f469ed80ef52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273682111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3273682111
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4043411292
Short name T1029
Test name
Test status
Simulation time 24605192 ps
CPU time 0.73 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 203964 kb
Host smart-3523da31-10ef-4368-a717-042cb7ae7adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043411292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4043411292
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1051065171
Short name T1120
Test name
Test status
Simulation time 25969756 ps
CPU time 0.71 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 203924 kb
Host smart-bd0c411a-94ac-4a0d-9db9-b02b003c7acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051065171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1051065171
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3635328002
Short name T1146
Test name
Test status
Simulation time 14495358 ps
CPU time 0.77 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:14 PM PDT 24
Peak memory 203896 kb
Host smart-bc31db09-9fd6-4de4-9ecf-c074955cd05e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635328002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3635328002
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.255271887
Short name T1104
Test name
Test status
Simulation time 49377627 ps
CPU time 0.77 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:14 PM PDT 24
Peak memory 203968 kb
Host smart-7d9133a3-50d4-4f27-8097-d09db90ae0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255271887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.255271887
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3926465598
Short name T1070
Test name
Test status
Simulation time 1284222144 ps
CPU time 23.4 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 215464 kb
Host smart-2508a854-4dee-4675-ac6b-39abe30b4493
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926465598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3926465598
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2838810963
Short name T1125
Test name
Test status
Simulation time 2177776604 ps
CPU time 32.88 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:52:20 PM PDT 24
Peak memory 207244 kb
Host smart-f883fed9-a27d-43d8-9052-c3a6a8be3ea9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838810963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2838810963
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3834459118
Short name T79
Test name
Test status
Simulation time 285104791 ps
CPU time 1.41 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 207248 kb
Host smart-89eb8725-a620-4920-9aa4-e583f0a20142
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834459118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3834459118
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3438202471
Short name T1066
Test name
Test status
Simulation time 104095127 ps
CPU time 3.83 seconds
Started Jul 11 04:51:47 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 217260 kb
Host smart-28f1d2c8-eaeb-4c03-914f-32a7a0d9fa7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438202471 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3438202471
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3522466649
Short name T1106
Test name
Test status
Simulation time 425427376 ps
CPU time 2.45 seconds
Started Jul 11 04:51:48 PM PDT 24
Finished Jul 11 04:51:53 PM PDT 24
Peak memory 215480 kb
Host smart-516e2942-c882-4ccc-b341-e9e72d4a6f1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522466649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
522466649
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1208415260
Short name T1099
Test name
Test status
Simulation time 41718619 ps
CPU time 0.71 seconds
Started Jul 11 04:51:34 PM PDT 24
Finished Jul 11 04:51:36 PM PDT 24
Peak memory 203944 kb
Host smart-50bfe04a-1e51-4965-aa16-f375c361e216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208415260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
208415260
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1525608825
Short name T1113
Test name
Test status
Simulation time 83424983 ps
CPU time 1.33 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 215412 kb
Host smart-97427d4f-fd57-431c-9b79-c3c6cc54163c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525608825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1525608825
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2847478885
Short name T1026
Test name
Test status
Simulation time 18034463 ps
CPU time 0.68 seconds
Started Jul 11 04:51:46 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 203800 kb
Host smart-ad5c004f-99b5-4318-8f1a-f3a6a97c5881
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847478885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2847478885
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3391850188
Short name T1046
Test name
Test status
Simulation time 682715968 ps
CPU time 3.82 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 215508 kb
Host smart-7f944271-a2c7-46a0-af8b-370fcff22c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391850188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3391850188
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.353261711
Short name T97
Test name
Test status
Simulation time 127584603 ps
CPU time 3.22 seconds
Started Jul 11 04:51:36 PM PDT 24
Finished Jul 11 04:51:41 PM PDT 24
Peak memory 215708 kb
Host smart-37443b99-827a-47b0-aa7a-94e896435a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353261711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.353261711
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2359337119
Short name T240
Test name
Test status
Simulation time 1246379790 ps
CPU time 17.07 seconds
Started Jul 11 04:51:35 PM PDT 24
Finished Jul 11 04:51:55 PM PDT 24
Peak memory 215308 kb
Host smart-156b6b93-6c9d-4a2f-98b4-d997a0a83af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359337119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2359337119
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2464249999
Short name T1069
Test name
Test status
Simulation time 81788772 ps
CPU time 0.72 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 204184 kb
Host smart-03327ef0-926f-4a53-a385-c2d4ca239e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464249999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2464249999
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2589429665
Short name T1043
Test name
Test status
Simulation time 58808840 ps
CPU time 0.77 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 203992 kb
Host smart-a9b43d98-8b84-4ed0-b9ba-b8dc9307cf7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589429665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2589429665
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.947125475
Short name T1126
Test name
Test status
Simulation time 12530166 ps
CPU time 0.76 seconds
Started Jul 11 04:52:09 PM PDT 24
Finished Jul 11 04:52:14 PM PDT 24
Peak memory 203968 kb
Host smart-d6fce094-b643-4b43-974b-03878253dd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947125475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.947125475
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2124712300
Short name T1085
Test name
Test status
Simulation time 33958275 ps
CPU time 0.7 seconds
Started Jul 11 04:52:15 PM PDT 24
Finished Jul 11 04:52:25 PM PDT 24
Peak memory 204268 kb
Host smart-da73cf31-9001-414e-95ad-951427d16b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124712300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2124712300
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2841518161
Short name T1031
Test name
Test status
Simulation time 37415717 ps
CPU time 0.81 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:16 PM PDT 24
Peak memory 204156 kb
Host smart-8b3adedb-347a-4ae6-8901-488604e717e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841518161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2841518161
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4262602518
Short name T1093
Test name
Test status
Simulation time 22013984 ps
CPU time 0.73 seconds
Started Jul 11 04:52:15 PM PDT 24
Finished Jul 11 04:52:25 PM PDT 24
Peak memory 203928 kb
Host smart-426e0a5d-dd93-4614-bfb9-538a500e4229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262602518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4262602518
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.477388157
Short name T1095
Test name
Test status
Simulation time 13413858 ps
CPU time 0.71 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 203856 kb
Host smart-f9808ab1-ac2e-4e81-a60f-919b3c064108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477388157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.477388157
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2714412799
Short name T1063
Test name
Test status
Simulation time 37845639 ps
CPU time 0.68 seconds
Started Jul 11 04:52:17 PM PDT 24
Finished Jul 11 04:52:28 PM PDT 24
Peak memory 203900 kb
Host smart-60d5b754-70ad-4af7-a055-192025a16bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714412799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2714412799
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1282851407
Short name T1143
Test name
Test status
Simulation time 12819135 ps
CPU time 0.73 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 204032 kb
Host smart-d5243529-7c60-44b5-9d31-f8698b3e71d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282851407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1282851407
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3481715362
Short name T1053
Test name
Test status
Simulation time 47075163 ps
CPU time 0.7 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 203828 kb
Host smart-aa9eee1f-b6d9-482c-88fd-c5299f0151e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481715362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3481715362
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.223226830
Short name T114
Test name
Test status
Simulation time 3076408164 ps
CPU time 16.78 seconds
Started Jul 11 04:51:45 PM PDT 24
Finished Jul 11 04:52:05 PM PDT 24
Peak memory 215444 kb
Host smart-ee7d57df-eafe-469a-b636-7d60a354cb9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223226830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.223226830
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1861824247
Short name T1038
Test name
Test status
Simulation time 611486528 ps
CPU time 13.8 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:59 PM PDT 24
Peak memory 215264 kb
Host smart-0bc55bbb-6d9f-431d-8e76-9e265f982c64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861824247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1861824247
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3903205370
Short name T78
Test name
Test status
Simulation time 88960036 ps
CPU time 1.24 seconds
Started Jul 11 04:51:46 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 207136 kb
Host smart-44467dd6-ca67-49fb-9907-cce18ab15177
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903205370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3903205370
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2372618170
Short name T1137
Test name
Test status
Simulation time 1736184365 ps
CPU time 2.6 seconds
Started Jul 11 04:51:45 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 216632 kb
Host smart-6b4fc065-5f57-43e2-bdd3-2814936d3e38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372618170 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2372618170
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1027568123
Short name T1139
Test name
Test status
Simulation time 198022368 ps
CPU time 2.39 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 215452 kb
Host smart-14300646-90d5-4d52-93c4-0e98c7098ad7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027568123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
027568123
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2558727285
Short name T1042
Test name
Test status
Simulation time 14711754 ps
CPU time 0.75 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 203832 kb
Host smart-4a8732ed-dd19-4428-8103-9e5cd4a85d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558727285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
558727285
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3702580873
Short name T118
Test name
Test status
Simulation time 222380269 ps
CPU time 2.28 seconds
Started Jul 11 04:51:42 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 215440 kb
Host smart-95fa465b-0e32-4c33-bcf8-85d0e86e7ac1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702580873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3702580873
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4053929908
Short name T1064
Test name
Test status
Simulation time 35344303 ps
CPU time 0.73 seconds
Started Jul 11 04:51:42 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 203864 kb
Host smart-2ef40c20-a69a-4586-aeba-3a0fc0573fb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053929908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4053929908
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2539297124
Short name T1145
Test name
Test status
Simulation time 100410466 ps
CPU time 4.01 seconds
Started Jul 11 04:51:47 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 215280 kb
Host smart-7370d42b-5060-4e82-a73a-081e69f19bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539297124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2539297124
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3445470036
Short name T154
Test name
Test status
Simulation time 674831616 ps
CPU time 15.2 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:52:02 PM PDT 24
Peak memory 215788 kb
Host smart-620e0b2c-8ed0-4075-8600-f560e2f27d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445470036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3445470036
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1491582109
Short name T1058
Test name
Test status
Simulation time 49599675 ps
CPU time 0.71 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 204172 kb
Host smart-76fe254a-3c7f-4b1e-ba00-f76cf96a99dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491582109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1491582109
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1503877954
Short name T1130
Test name
Test status
Simulation time 15794989 ps
CPU time 0.71 seconds
Started Jul 11 04:52:16 PM PDT 24
Finished Jul 11 04:52:26 PM PDT 24
Peak memory 203812 kb
Host smart-e0cd1433-3ebb-4c3e-bfc2-475f5ab985b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503877954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1503877954
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3145306829
Short name T1087
Test name
Test status
Simulation time 18120406 ps
CPU time 0.68 seconds
Started Jul 11 04:52:13 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 203920 kb
Host smart-46aa4de8-2bcd-488c-a0bd-975fa21fdfa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145306829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3145306829
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1078169268
Short name T1057
Test name
Test status
Simulation time 37579344 ps
CPU time 0.74 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 204232 kb
Host smart-b09d85f9-3cfb-42ef-9c03-f54d655be84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078169268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1078169268
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1123906771
Short name T1034
Test name
Test status
Simulation time 45664661 ps
CPU time 0.73 seconds
Started Jul 11 04:52:12 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 203916 kb
Host smart-8f335ccf-dbc3-4abf-bb1b-d949d36eba00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123906771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1123906771
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1477492266
Short name T1061
Test name
Test status
Simulation time 13046335 ps
CPU time 0.72 seconds
Started Jul 11 04:52:12 PM PDT 24
Finished Jul 11 04:52:20 PM PDT 24
Peak memory 203940 kb
Host smart-3fba5974-2056-4fc5-b75a-5aa3940fa3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477492266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1477492266
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1507083463
Short name T1060
Test name
Test status
Simulation time 266144476 ps
CPU time 0.81 seconds
Started Jul 11 04:52:13 PM PDT 24
Finished Jul 11 04:52:21 PM PDT 24
Peak memory 204172 kb
Host smart-b8348540-7207-4bb0-b91c-bc2040abc22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507083463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1507083463
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2950519072
Short name T1081
Test name
Test status
Simulation time 23044423 ps
CPU time 0.71 seconds
Started Jul 11 04:52:14 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 204184 kb
Host smart-33303e35-6f5e-4a43-a471-e36a1ccb23d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950519072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2950519072
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.555101014
Short name T1045
Test name
Test status
Simulation time 16352781 ps
CPU time 0.76 seconds
Started Jul 11 04:52:11 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 204268 kb
Host smart-18c31de0-78bd-4793-a1f5-53af6ddaa9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555101014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.555101014
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2795217094
Short name T1119
Test name
Test status
Simulation time 58395642 ps
CPU time 0.69 seconds
Started Jul 11 04:52:10 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 204212 kb
Host smart-a0ae3d0a-e453-449d-a2eb-39bb289f69ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795217094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2795217094
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1493603265
Short name T1149
Test name
Test status
Simulation time 107686858 ps
CPU time 2.6 seconds
Started Jul 11 04:51:47 PM PDT 24
Finished Jul 11 04:51:52 PM PDT 24
Peak memory 217084 kb
Host smart-efd4817a-bbd0-4b31-a29d-7ff0b816ca95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493603265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1493603265
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2925929293
Short name T115
Test name
Test status
Simulation time 20533951 ps
CPU time 1.47 seconds
Started Jul 11 04:51:47 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 215452 kb
Host smart-7824f525-0263-4bb9-8048-166e1692e5f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925929293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
925929293
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3249941424
Short name T1080
Test name
Test status
Simulation time 152646176 ps
CPU time 0.72 seconds
Started Jul 11 04:51:50 PM PDT 24
Finished Jul 11 04:51:53 PM PDT 24
Peak memory 203852 kb
Host smart-7792a0dd-5685-4098-aad6-93dd17157d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249941424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
249941424
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.374748264
Short name T1089
Test name
Test status
Simulation time 82123759 ps
CPU time 2.55 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 215468 kb
Host smart-933d4f4e-2473-4812-a321-8be233f2f858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374748264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.374748264
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3564075654
Short name T104
Test name
Test status
Simulation time 262562215 ps
CPU time 4.27 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 215676 kb
Host smart-3546cca6-583c-4ad5-861d-4811a96253e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564075654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
564075654
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1081929502
Short name T1133
Test name
Test status
Simulation time 105930988 ps
CPU time 6.47 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:53 PM PDT 24
Peak memory 215468 kb
Host smart-552d6f5d-c44b-4a9c-893f-567c16b8fb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081929502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1081929502
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1491698783
Short name T1065
Test name
Test status
Simulation time 23804794 ps
CPU time 1.73 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 216592 kb
Host smart-aa4ec5ec-8561-4fce-b537-0cf2e6bc175c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491698783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1491698783
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.592317933
Short name T116
Test name
Test status
Simulation time 211852146 ps
CPU time 1.33 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:51:49 PM PDT 24
Peak memory 207152 kb
Host smart-962286cd-de06-47ef-8c58-1bd782f58b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592317933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.592317933
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4139256297
Short name T1100
Test name
Test status
Simulation time 46784324 ps
CPU time 0.73 seconds
Started Jul 11 04:51:48 PM PDT 24
Finished Jul 11 04:51:52 PM PDT 24
Peak memory 203920 kb
Host smart-ba624ba0-e871-4e6c-ad88-0f89a091630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139256297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
139256297
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3429489846
Short name T1127
Test name
Test status
Simulation time 27083552 ps
CPU time 1.88 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 215396 kb
Host smart-2504bd30-d027-49a8-affc-1dfc958f59b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429489846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3429489846
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2875087170
Short name T235
Test name
Test status
Simulation time 218120823 ps
CPU time 3.02 seconds
Started Jul 11 04:51:43 PM PDT 24
Finished Jul 11 04:51:49 PM PDT 24
Peak memory 215840 kb
Host smart-962eb4ba-8337-464d-a194-c82928f0b7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875087170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
875087170
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1640604244
Short name T1108
Test name
Test status
Simulation time 294801583 ps
CPU time 19.99 seconds
Started Jul 11 04:51:44 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 215492 kb
Host smart-9575026d-7c14-4212-b115-4c0ae8b85ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640604244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1640604244
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1459042266
Short name T1123
Test name
Test status
Simulation time 427481537 ps
CPU time 1.62 seconds
Started Jul 11 04:51:55 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 215504 kb
Host smart-0f54030b-d974-43d1-bf49-6049ce9882af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459042266 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1459042266
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1898629000
Short name T1079
Test name
Test status
Simulation time 90750168 ps
CPU time 2.51 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 215436 kb
Host smart-e5301a8d-42cd-41bb-bb63-6d064c9bfcab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898629000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
898629000
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1338542146
Short name T1068
Test name
Test status
Simulation time 21433322 ps
CPU time 0.68 seconds
Started Jul 11 04:51:56 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 203876 kb
Host smart-69260675-18a1-468b-b633-4f506bc60b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338542146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
338542146
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3372234025
Short name T140
Test name
Test status
Simulation time 151465199 ps
CPU time 1.98 seconds
Started Jul 11 04:51:53 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 215400 kb
Host smart-86879353-30db-4ca2-9acb-7d9bf77a8c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372234025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3372234025
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1086689029
Short name T102
Test name
Test status
Simulation time 73358195 ps
CPU time 2.62 seconds
Started Jul 11 04:51:45 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 215828 kb
Host smart-51fef5bc-585e-4c1b-8b92-1824d3530cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086689029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
086689029
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.590230329
Short name T242
Test name
Test status
Simulation time 375894101 ps
CPU time 8.27 seconds
Started Jul 11 04:51:51 PM PDT 24
Finished Jul 11 04:52:01 PM PDT 24
Peak memory 215388 kb
Host smart-5fc666b7-fb28-4f8c-ac32-82baf3823b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590230329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.590230329
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1902385304
Short name T1091
Test name
Test status
Simulation time 455403515 ps
CPU time 2.8 seconds
Started Jul 11 04:51:52 PM PDT 24
Finished Jul 11 04:51:56 PM PDT 24
Peak memory 216608 kb
Host smart-82b6bb19-9734-4cf7-b9ed-5713a4a00d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902385304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1902385304
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1522978567
Short name T1111
Test name
Test status
Simulation time 22087065 ps
CPU time 1.4 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 207228 kb
Host smart-fdbcc1a2-3716-4640-8b2b-38f2d484adfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522978567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
522978567
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2651419481
Short name T1032
Test name
Test status
Simulation time 12894556 ps
CPU time 0.69 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:56 PM PDT 24
Peak memory 204264 kb
Host smart-5f50a8f0-fecf-4cae-b267-e083e94eb27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651419481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
651419481
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1366661784
Short name T1088
Test name
Test status
Simulation time 227868420 ps
CPU time 2.94 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 215740 kb
Host smart-9d49eca3-1385-4e7f-a9ea-0f344c1ad078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366661784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1366661784
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.301160566
Short name T103
Test name
Test status
Simulation time 565331895 ps
CPU time 4.49 seconds
Started Jul 11 04:51:53 PM PDT 24
Finished Jul 11 04:51:59 PM PDT 24
Peak memory 215672 kb
Host smart-a7d39c99-d2be-4883-994c-bb8a2b52d5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301160566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.301160566
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2412280879
Short name T1112
Test name
Test status
Simulation time 143870242 ps
CPU time 3.64 seconds
Started Jul 11 04:51:59 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 218792 kb
Host smart-3d3cba61-a3f1-42f0-b024-396a860003a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412280879 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2412280879
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3311885093
Short name T121
Test name
Test status
Simulation time 149034417 ps
CPU time 1.84 seconds
Started Jul 11 04:51:54 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 215424 kb
Host smart-4a94209f-46dc-49bc-9f92-be5d8f13b73a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311885093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
311885093
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.58387638
Short name T1115
Test name
Test status
Simulation time 14049411 ps
CPU time 0.69 seconds
Started Jul 11 04:51:53 PM PDT 24
Finished Jul 11 04:51:55 PM PDT 24
Peak memory 203904 kb
Host smart-983a5a96-29e0-41f9-a6b9-fe4b0e6e5cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58387638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.58387638
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3857228309
Short name T149
Test name
Test status
Simulation time 1129681244 ps
CPU time 4.82 seconds
Started Jul 11 04:51:56 PM PDT 24
Finished Jul 11 04:52:02 PM PDT 24
Peak memory 215444 kb
Host smart-a1e87064-7b70-48d1-af23-4f06cefabd1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857228309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3857228309
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2417411984
Short name T1055
Test name
Test status
Simulation time 670647081 ps
CPU time 4.57 seconds
Started Jul 11 04:51:55 PM PDT 24
Finished Jul 11 04:52:01 PM PDT 24
Peak memory 215640 kb
Host smart-867e8e3b-6052-42f8-9094-449fd2518a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417411984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
417411984
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2512716315
Short name T239
Test name
Test status
Simulation time 1499608474 ps
CPU time 18.6 seconds
Started Jul 11 04:51:53 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 216420 kb
Host smart-8a8de95c-d516-47c0-9c4c-f6961cda9f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512716315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2512716315
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3676582991
Short name T676
Test name
Test status
Simulation time 12796219 ps
CPU time 0.7 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:13 PM PDT 24
Peak memory 205672 kb
Host smart-d78745cb-8e1f-49e7-9fac-5e1f1959f371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676582991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
676582991
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1513201747
Short name T882
Test name
Test status
Simulation time 108030636 ps
CPU time 2.78 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:31:58 PM PDT 24
Peak memory 233744 kb
Host smart-f9acbaca-abe5-47cb-8a84-8f740cc02a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513201747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1513201747
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2516519985
Short name T22
Test name
Test status
Simulation time 17487618 ps
CPU time 0.78 seconds
Started Jul 11 04:31:30 PM PDT 24
Finished Jul 11 04:31:49 PM PDT 24
Peak memory 207416 kb
Host smart-16a512e7-0677-42cf-ac8e-492e7d947d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516519985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2516519985
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2040360145
Short name T712
Test name
Test status
Simulation time 5045790275 ps
CPU time 36.4 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 250156 kb
Host smart-7d3277c4-02a2-4a16-b55d-30018487b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040360145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2040360145
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2062632329
Short name T787
Test name
Test status
Simulation time 42125320576 ps
CPU time 53.11 seconds
Started Jul 11 04:31:25 PM PDT 24
Finished Jul 11 04:32:38 PM PDT 24
Peak memory 233924 kb
Host smart-8fcc8b60-ca7b-4a2b-a156-5e9d75a2317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062632329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2062632329
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2483190594
Short name T768
Test name
Test status
Simulation time 969269458 ps
CPU time 17.88 seconds
Started Jul 11 04:31:45 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 225616 kb
Host smart-dfeaa545-6959-4901-9184-cdac05f3016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483190594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2483190594
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1927492124
Short name T764
Test name
Test status
Simulation time 304313572 ps
CPU time 4.05 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:12 PM PDT 24
Peak memory 225472 kb
Host smart-3b2681dc-475f-4113-9f1e-bf84c0d5ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927492124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1927492124
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3885758783
Short name T809
Test name
Test status
Simulation time 42704206488 ps
CPU time 141.59 seconds
Started Jul 11 04:31:38 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 253432 kb
Host smart-992547ca-0e9f-4404-a98f-0633703be660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885758783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3885758783
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3929028951
Short name T548
Test name
Test status
Simulation time 558495671 ps
CPU time 5.28 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:32:01 PM PDT 24
Peak memory 233712 kb
Host smart-76cddd84-4984-489d-89fe-bea519c9aea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929028951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3929028951
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2807038553
Short name T194
Test name
Test status
Simulation time 4286660054 ps
CPU time 47.38 seconds
Started Jul 11 04:31:33 PM PDT 24
Finished Jul 11 04:32:39 PM PDT 24
Peak memory 225668 kb
Host smart-1fee27fd-f677-4f3b-a313-5cf3f379fbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807038553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2807038553
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.520282885
Short name T983
Test name
Test status
Simulation time 42797722 ps
CPU time 1 seconds
Started Jul 11 04:31:39 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 217632 kb
Host smart-2b326ddb-361d-4593-816d-c81c75ef192f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520282885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.520282885
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.456092757
Short name T224
Test name
Test status
Simulation time 2099227992 ps
CPU time 4.23 seconds
Started Jul 11 04:31:35 PM PDT 24
Finished Jul 11 04:31:57 PM PDT 24
Peak memory 233696 kb
Host smart-87ce3514-735b-45ff-913f-f754a10541e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456092757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
456092757
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3758156504
Short name T701
Test name
Test status
Simulation time 1379591882 ps
CPU time 3.55 seconds
Started Jul 11 04:31:36 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 233724 kb
Host smart-e67535be-4c2c-4679-99d6-755d3ed83408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758156504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3758156504
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4227834453
Short name T535
Test name
Test status
Simulation time 8508233371 ps
CPU time 14.37 seconds
Started Jul 11 04:31:29 PM PDT 24
Finished Jul 11 04:32:02 PM PDT 24
Peak memory 220208 kb
Host smart-640e5e39-0c36-4df1-a3a0-13dbaf9e5d55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4227834453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4227834453
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3765702222
Short name T14
Test name
Test status
Simulation time 2878998534 ps
CPU time 64.83 seconds
Started Jul 11 04:31:20 PM PDT 24
Finished Jul 11 04:32:44 PM PDT 24
Peak memory 251400 kb
Host smart-458fb6bd-2466-4764-8ae7-9427866d5b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765702222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3765702222
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1733088383
Short name T591
Test name
Test status
Simulation time 10914773445 ps
CPU time 21.08 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:33 PM PDT 24
Peak memory 217636 kb
Host smart-ca3fd5eb-c018-49ec-aa34-55650656bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733088383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1733088383
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1877553786
Short name T770
Test name
Test status
Simulation time 102683225 ps
CPU time 1.27 seconds
Started Jul 11 04:31:39 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 208248 kb
Host smart-fdf6df85-81af-4caa-8664-d43483957a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877553786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1877553786
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2190705630
Short name T613
Test name
Test status
Simulation time 29887074 ps
CPU time 0.67 seconds
Started Jul 11 04:31:38 PM PDT 24
Finished Jul 11 04:31:57 PM PDT 24
Peak memory 206548 kb
Host smart-e8ffbe69-5744-46ad-b315-d4f69846bf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190705630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2190705630
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2318938663
Short name T677
Test name
Test status
Simulation time 96830497 ps
CPU time 0.76 seconds
Started Jul 11 04:31:54 PM PDT 24
Finished Jul 11 04:32:19 PM PDT 24
Peak memory 206832 kb
Host smart-018c46d2-1628-4bd0-840f-53223f698d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318938663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2318938663
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.249906020
Short name T177
Test name
Test status
Simulation time 926206287 ps
CPU time 3.38 seconds
Started Jul 11 04:31:48 PM PDT 24
Finished Jul 11 04:32:15 PM PDT 24
Peak memory 225392 kb
Host smart-c964a7e9-c295-4fc8-9d5e-f44b4b44d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249906020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.249906020
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3052316134
Short name T721
Test name
Test status
Simulation time 33298779 ps
CPU time 0.69 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:32:06 PM PDT 24
Peak memory 206224 kb
Host smart-af5899ff-bb76-48ba-bb57-a65a11156424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052316134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
052316134
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2256813335
Short name T820
Test name
Test status
Simulation time 714864539 ps
CPU time 9.37 seconds
Started Jul 11 04:31:29 PM PDT 24
Finished Jul 11 04:31:57 PM PDT 24
Peak memory 233688 kb
Host smart-5dda58fd-75f4-4e56-8a60-3c0c2c59fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256813335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2256813335
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1960013645
Short name T503
Test name
Test status
Simulation time 19974482 ps
CPU time 0.71 seconds
Started Jul 11 04:31:35 PM PDT 24
Finished Jul 11 04:31:54 PM PDT 24
Peak memory 206340 kb
Host smart-baf3344e-3b95-4a1b-b2bb-bb24259ec4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960013645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1960013645
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3742015978
Short name T2
Test name
Test status
Simulation time 1604940518 ps
CPU time 19.21 seconds
Started Jul 11 04:31:45 PM PDT 24
Finished Jul 11 04:32:25 PM PDT 24
Peak memory 238556 kb
Host smart-fa007f09-ff76-412f-aec9-efd0f4e3d825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742015978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3742015978
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2936992721
Short name T136
Test name
Test status
Simulation time 77802553644 ps
CPU time 78.21 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:33:13 PM PDT 24
Peak memory 257852 kb
Host smart-9235001e-6e7b-473a-a289-236392172d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936992721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2936992721
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1998316760
Short name T292
Test name
Test status
Simulation time 35678397380 ps
CPU time 295.29 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:37:16 PM PDT 24
Peak memory 254680 kb
Host smart-3d4def5b-578f-4a18-83ad-cde2df8e1bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998316760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1998316760
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.151625813
Short name T390
Test name
Test status
Simulation time 15531056246 ps
CPU time 135.56 seconds
Started Jul 11 04:31:51 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 266660 kb
Host smart-fbf1333a-075e-41a0-ba3a-c75c9c35e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151625813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
151625813
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2061041659
Short name T687
Test name
Test status
Simulation time 1077327941 ps
CPU time 4.59 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:05 PM PDT 24
Peak memory 233620 kb
Host smart-18033165-2cf9-4eba-8ffa-a6f5444e0518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061041659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2061041659
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.202416894
Short name T277
Test name
Test status
Simulation time 2767417620 ps
CPU time 35.76 seconds
Started Jul 11 04:31:34 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 233708 kb
Host smart-3dda246f-ab5d-4093-b99f-d61cf3ea2253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202416894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.202416894
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3047217508
Short name T994
Test name
Test status
Simulation time 254465986 ps
CPU time 1 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:14 PM PDT 24
Peak memory 217520 kb
Host smart-bc4b494a-dd4c-44a8-958e-d32cb0317482
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047217508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3047217508
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3886290396
Short name T633
Test name
Test status
Simulation time 17971296625 ps
CPU time 11.89 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 225588 kb
Host smart-75dd8969-0215-4f6e-9a09-c1fbad6a21cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886290396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3886290396
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.578415670
Short name T790
Test name
Test status
Simulation time 565398030 ps
CPU time 4.25 seconds
Started Jul 11 04:31:20 PM PDT 24
Finished Jul 11 04:31:44 PM PDT 24
Peak memory 233676 kb
Host smart-7fa246fc-f546-4c23-b2d0-a344251bc885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578415670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.578415670
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.13205657
Short name T874
Test name
Test status
Simulation time 8120524366 ps
CPU time 19.75 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 224260 kb
Host smart-f88a0e9e-c9a7-4373-b466-f2d61a240e6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13205657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.13205657
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3976851041
Short name T63
Test name
Test status
Simulation time 63543177 ps
CPU time 1.05 seconds
Started Jul 11 04:31:38 PM PDT 24
Finished Jul 11 04:31:58 PM PDT 24
Peak memory 236680 kb
Host smart-b13b8cb4-d726-46ee-8534-3fbed4ff32db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976851041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3976851041
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.611780234
Short name T620
Test name
Test status
Simulation time 93505376306 ps
CPU time 47.08 seconds
Started Jul 11 04:31:38 PM PDT 24
Finished Jul 11 04:32:44 PM PDT 24
Peak memory 217376 kb
Host smart-42f573ef-8340-43d0-93b1-abb2eb4d0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611780234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.611780234
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3783063919
Short name T610
Test name
Test status
Simulation time 12588366 ps
CPU time 0.67 seconds
Started Jul 11 04:31:45 PM PDT 24
Finished Jul 11 04:32:07 PM PDT 24
Peak memory 206528 kb
Host smart-728a377c-7f5a-4bee-a8a2-a87ad52b2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783063919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3783063919
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2968676493
Short name T73
Test name
Test status
Simulation time 27817593 ps
CPU time 1.09 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:03 PM PDT 24
Peak memory 217200 kb
Host smart-f24a13de-1842-4e2a-97fa-754784fef472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968676493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2968676493
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2771073514
Short name T974
Test name
Test status
Simulation time 81782656 ps
CPU time 0.72 seconds
Started Jul 11 04:31:39 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 206852 kb
Host smart-3f093471-3be8-4291-8fcd-1df7fbef7707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771073514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2771073514
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.285561458
Short name T570
Test name
Test status
Simulation time 448644430 ps
CPU time 2.67 seconds
Started Jul 11 04:31:39 PM PDT 24
Finished Jul 11 04:32:01 PM PDT 24
Peak memory 225532 kb
Host smart-f13a5661-7495-44bd-822b-740b4fc4888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285561458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.285561458
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.454732947
Short name T879
Test name
Test status
Simulation time 23757593 ps
CPU time 0.74 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:17 PM PDT 24
Peak memory 205676 kb
Host smart-e91e1677-5207-481d-9faf-debd62fbd944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454732947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.454732947
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.797043042
Short name T162
Test name
Test status
Simulation time 1274017383 ps
CPU time 13.39 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 233636 kb
Host smart-00d50b3e-dd70-43c0-8ae4-e336268b609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797043042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.797043042
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.384067487
Short name T383
Test name
Test status
Simulation time 30110699 ps
CPU time 0.71 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 206684 kb
Host smart-76d11218-f50a-4a20-8da0-3caab673a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384067487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.384067487
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2848635517
Short name T523
Test name
Test status
Simulation time 10028149075 ps
CPU time 24.27 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:57 PM PDT 24
Peak memory 241424 kb
Host smart-016bf4e2-4398-4e68-a2ce-1badc3337247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848635517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2848635517
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1659596629
Short name T773
Test name
Test status
Simulation time 82598482207 ps
CPU time 175.32 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:35:21 PM PDT 24
Peak memory 257396 kb
Host smart-50ca8bcb-37c2-4fc5-bc8d-5e7ce5f7c676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659596629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1659596629
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3283783655
Short name T209
Test name
Test status
Simulation time 27470563540 ps
CPU time 96.74 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 252464 kb
Host smart-424efb7b-760e-47c0-b79e-347373407e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283783655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3283783655
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3246865756
Short name T283
Test name
Test status
Simulation time 2269244545 ps
CPU time 11.74 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 233804 kb
Host smart-903e09ff-0049-424b-9c67-d182d52cb079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246865756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3246865756
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3340844802
Short name T221
Test name
Test status
Simulation time 40529585666 ps
CPU time 128.14 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:34:41 PM PDT 24
Peak memory 269188 kb
Host smart-532f801f-07a6-4a1d-a599-ed8759762e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340844802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3340844802
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1032101714
Short name T384
Test name
Test status
Simulation time 4697789101 ps
CPU time 10.57 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 225652 kb
Host smart-c315cb47-8582-4a32-b0bc-ea03ed591ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032101714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1032101714
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3425010473
Short name T1024
Test name
Test status
Simulation time 46397350528 ps
CPU time 59.69 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 241440 kb
Host smart-018f6063-0d65-4166-a4ef-27a16aed5705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425010473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3425010473
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.135456268
Short name T627
Test name
Test status
Simulation time 5965811473 ps
CPU time 19.96 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:33:03 PM PDT 24
Peak memory 241716 kb
Host smart-293770ca-f173-4650-b783-b6c5f8151969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135456268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.135456268
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1698363921
Short name T126
Test name
Test status
Simulation time 90961655 ps
CPU time 2.99 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 233664 kb
Host smart-f4298446-d588-4696-ae1d-b86144e23c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698363921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1698363921
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.459839108
Short name T341
Test name
Test status
Simulation time 77102953 ps
CPU time 3.7 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:46 PM PDT 24
Peak memory 224080 kb
Host smart-3932d620-1403-4f8d-8cfd-a24b38abd24c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459839108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.459839108
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3054449721
Short name T20
Test name
Test status
Simulation time 200928311 ps
CPU time 0.82 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 207512 kb
Host smart-906e2875-2c27-4545-872c-95652b726397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054449721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3054449721
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2907595140
Short name T921
Test name
Test status
Simulation time 7457931943 ps
CPU time 17.98 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 217724 kb
Host smart-1feb5c5c-ed87-40e9-827d-404be9fdefaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907595140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2907595140
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1158935733
Short name T845
Test name
Test status
Simulation time 13827590 ps
CPU time 0.7 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 206508 kb
Host smart-f1093021-74b3-42ef-b3b8-cc1e896578f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158935733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1158935733
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.690313416
Short name T807
Test name
Test status
Simulation time 36806028 ps
CPU time 1.09 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 208320 kb
Host smart-47362286-9cc8-4cf0-a4b4-f2995daddea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690313416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.690313416
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2188231383
Short name T788
Test name
Test status
Simulation time 58500155 ps
CPU time 0.83 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:40 PM PDT 24
Peak memory 206916 kb
Host smart-5ada5c7e-8f35-42e3-b635-a86751d76942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188231383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2188231383
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3863912232
Short name T329
Test name
Test status
Simulation time 3167010645 ps
CPU time 6.92 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:30 PM PDT 24
Peak memory 233760 kb
Host smart-6c229085-7c6c-4b1f-b7e5-17f585c593e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863912232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3863912232
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2339356746
Short name T982
Test name
Test status
Simulation time 27819275 ps
CPU time 0.72 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 206312 kb
Host smart-b38e362f-b05d-412b-b104-2fa9026964f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339356746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2339356746
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1861199985
Short name T496
Test name
Test status
Simulation time 348128952 ps
CPU time 4.82 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 233604 kb
Host smart-fa5bd3be-392e-495c-92f1-d2f2563222d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861199985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1861199985
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2705238630
Short name T526
Test name
Test status
Simulation time 13101702 ps
CPU time 0.72 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 206328 kb
Host smart-e2cc50c3-a785-47f5-a02f-45ea88d05ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705238630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2705238630
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2247918116
Short name T205
Test name
Test status
Simulation time 33148707210 ps
CPU time 266.94 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:36:50 PM PDT 24
Peak memory 266656 kb
Host smart-ca2dace5-4c05-4d02-9c4b-cd78666ad26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247918116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2247918116
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2016523519
Short name T47
Test name
Test status
Simulation time 88963921347 ps
CPU time 711.69 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:44:23 PM PDT 24
Peak memory 257492 kb
Host smart-5eb6b3c0-231c-44e2-839a-a63441313292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016523519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2016523519
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1210425856
Short name T784
Test name
Test status
Simulation time 95778060 ps
CPU time 4.78 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:32:41 PM PDT 24
Peak memory 233768 kb
Host smart-ab40673e-e8a3-4d45-90d9-27bfe6ad0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210425856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1210425856
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2632424992
Short name T756
Test name
Test status
Simulation time 43821312 ps
CPU time 0.73 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:43 PM PDT 24
Peak memory 216820 kb
Host smart-0eef975a-7923-45a5-b83f-da6e6e220339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632424992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2632424992
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2161537687
Short name T485
Test name
Test status
Simulation time 655169926 ps
CPU time 4.9 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 233620 kb
Host smart-52a1f89b-f8be-4380-9d81-498c20a0afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161537687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2161537687
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3869436297
Short name T960
Test name
Test status
Simulation time 5694232999 ps
CPU time 29.91 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:33:03 PM PDT 24
Peak memory 225528 kb
Host smart-4105a9b7-32b0-4e1c-a732-2ae37e03f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869436297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3869436297
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.528417671
Short name T37
Test name
Test status
Simulation time 30463792 ps
CPU time 1.01 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 217612 kb
Host smart-4315eb29-96fd-46b2-9a65-8ee746d05e01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528417671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.528417671
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2001186787
Short name T685
Test name
Test status
Simulation time 3226467496 ps
CPU time 5.9 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:32:53 PM PDT 24
Peak memory 233716 kb
Host smart-98c86937-da0d-4b27-bfae-5ce708650957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001186787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2001186787
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3660847850
Short name T800
Test name
Test status
Simulation time 2774323442 ps
CPU time 4.12 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:38 PM PDT 24
Peak memory 234140 kb
Host smart-61424498-8c45-4d03-ac2d-327eb20c5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660847850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3660847850
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.521721771
Short name T643
Test name
Test status
Simulation time 20716684667 ps
CPU time 15.51 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 221372 kb
Host smart-e8df7105-66fa-4fa9-b709-a7feba1593be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=521721771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.521721771
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1427779381
Short name T710
Test name
Test status
Simulation time 121043789 ps
CPU time 0.96 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:32:29 PM PDT 24
Peak memory 208476 kb
Host smart-b6792c5d-9fa1-41f0-ab55-2f45461a12e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427779381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1427779381
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.185937224
Short name T941
Test name
Test status
Simulation time 1179126337 ps
CPU time 12.01 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 217288 kb
Host smart-1f51f45e-ea1e-4dfb-93cf-31c194f534cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185937224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.185937224
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.965451455
Short name T711
Test name
Test status
Simulation time 3172809427 ps
CPU time 10.27 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 217488 kb
Host smart-78b514d6-f28f-481c-be5a-68bd54b4be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965451455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.965451455
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.34095670
Short name T326
Test name
Test status
Simulation time 132493646 ps
CPU time 1.77 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:33 PM PDT 24
Peak memory 217508 kb
Host smart-9c1d4f98-eac6-4ea1-85c4-ae61a2e979c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34095670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.34095670
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_upload.1096293103
Short name T823
Test name
Test status
Simulation time 9510389488 ps
CPU time 11.04 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:54 PM PDT 24
Peak memory 233912 kb
Host smart-316262ff-f026-48ff-8a0b-2a15c711e02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096293103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1096293103
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3779912624
Short name T734
Test name
Test status
Simulation time 10907739 ps
CPU time 0.67 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 206292 kb
Host smart-2800b8d5-c232-4916-bcaa-0f4d84b15846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779912624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3779912624
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.343090286
Short name T926
Test name
Test status
Simulation time 2151701156 ps
CPU time 5.79 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 233828 kb
Host smart-caa42bf2-4fd9-44cc-8847-67634cb405d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343090286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.343090286
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1100967798
Short name T609
Test name
Test status
Simulation time 27004079 ps
CPU time 0.75 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 206804 kb
Host smart-38630d33-7dec-4a9d-b57d-625cdf5f2373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100967798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1100967798
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2691641993
Short name T559
Test name
Test status
Simulation time 19834917902 ps
CPU time 123.96 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:35:02 PM PDT 24
Peak memory 257484 kb
Host smart-0e0c50cf-c0f6-4e7c-a9cf-4811fd8e62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691641993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2691641993
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.665768804
Short name T859
Test name
Test status
Simulation time 8145109638 ps
CPU time 96 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 250248 kb
Host smart-f6b0dc5a-b991-4411-b022-c95a77aa1f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665768804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.665768804
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.670610975
Short name T443
Test name
Test status
Simulation time 6672401082 ps
CPU time 21.92 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:33:04 PM PDT 24
Peak memory 235888 kb
Host smart-97a14302-694a-405c-98c8-60aba6998455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670610975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.670610975
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3471807057
Short name T197
Test name
Test status
Simulation time 17221871781 ps
CPU time 126.68 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 250284 kb
Host smart-2d92b3a0-9ee9-4ebb-9db7-60fe34feff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471807057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3471807057
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3815839186
Short name T424
Test name
Test status
Simulation time 795915226 ps
CPU time 3.23 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:32:31 PM PDT 24
Peak memory 225520 kb
Host smart-2467ff1a-23da-47d4-a935-184debcaf142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815839186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3815839186
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1894829822
Short name T88
Test name
Test status
Simulation time 2116294664 ps
CPU time 18 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 233616 kb
Host smart-f5739350-cd76-4468-86b1-19754bad0946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894829822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1894829822
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4047580110
Short name T836
Test name
Test status
Simulation time 17231881 ps
CPU time 1 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:41 PM PDT 24
Peak memory 217536 kb
Host smart-04f936e4-c02c-4173-bf7a-ab571a46a6fe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047580110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4047580110
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3401633461
Short name T909
Test name
Test status
Simulation time 2023558121 ps
CPU time 6.11 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 233764 kb
Host smart-41eef1b2-5525-43a6-b674-d086044c41df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401633461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3401633461
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1676210260
Short name T604
Test name
Test status
Simulation time 1212207660 ps
CPU time 10.67 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:36 PM PDT 24
Peak memory 250648 kb
Host smart-6557e335-e8fb-45ac-8edc-e2f9e418559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676210260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1676210260
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1441060392
Short name T889
Test name
Test status
Simulation time 310944272 ps
CPU time 5.72 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:45 PM PDT 24
Peak memory 221400 kb
Host smart-5774085a-f4e8-4b97-b137-f802c0ba1d02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1441060392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1441060392
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3620111054
Short name T691
Test name
Test status
Simulation time 3523653341 ps
CPU time 24.4 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 217492 kb
Host smart-4a420783-ec64-44ba-b710-bb5fe487affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620111054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3620111054
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3707749244
Short name T302
Test name
Test status
Simulation time 30240441300 ps
CPU time 22.19 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 217524 kb
Host smart-83438045-3a6c-4bc2-a30a-adde60f15908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707749244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3707749244
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1253218400
Short name T924
Test name
Test status
Simulation time 251505067 ps
CPU time 4.04 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 217208 kb
Host smart-4a067729-9d31-4c9f-ba8a-059a231b39f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253218400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1253218400
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3312784158
Short name T829
Test name
Test status
Simulation time 39601462 ps
CPU time 0.76 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 206896 kb
Host smart-e7286ba9-c5c4-4082-809e-1ea6e79c5e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312784158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3312784158
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1897903606
Short name T193
Test name
Test status
Simulation time 1325899303 ps
CPU time 7.15 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 235644 kb
Host smart-68d10a3a-c228-438f-b37c-1e5c0058daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897903606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1897903606
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2821733064
Short name T966
Test name
Test status
Simulation time 13178495 ps
CPU time 0.71 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:44 PM PDT 24
Peak memory 206608 kb
Host smart-3b937ccf-bbd7-4dea-bd0e-2a7188fbb373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821733064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2821733064
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2780433034
Short name T755
Test name
Test status
Simulation time 9183576438 ps
CPU time 19.97 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 233732 kb
Host smart-e6f094ed-2be2-4943-bf4b-7a76f2443332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780433034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2780433034
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3547616701
Short name T853
Test name
Test status
Simulation time 12926003 ps
CPU time 0.73 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:43 PM PDT 24
Peak memory 207804 kb
Host smart-bf2088da-2333-4295-b5cd-0f1194fc0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547616701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3547616701
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2961876805
Short name T572
Test name
Test status
Simulation time 16756181519 ps
CPU time 38.99 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 241936 kb
Host smart-2641d8d0-e875-4bf6-a78b-7589ceb18f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961876805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2961876805
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.513128958
Short name T915
Test name
Test status
Simulation time 1220170633 ps
CPU time 16.7 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 218836 kb
Host smart-c256135d-d99d-4389-8722-30726371af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513128958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.513128958
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4200893652
Short name T656
Test name
Test status
Simulation time 6219311190 ps
CPU time 61.28 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 242436 kb
Host smart-5c6b9dcb-d8d9-4964-b899-97f6aedb2384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200893652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4200893652
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2126499921
Short name T282
Test name
Test status
Simulation time 7124059318 ps
CPU time 30.57 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:33:19 PM PDT 24
Peak memory 250252 kb
Host smart-114c0b69-5ae2-4f3f-97a5-5a78aba8d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126499921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2126499921
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2842141756
Short name T213
Test name
Test status
Simulation time 36492332226 ps
CPU time 69.57 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 250732 kb
Host smart-6e62616b-c1cb-4084-823a-0e2735f3176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842141756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2842141756
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2334977597
Short name T174
Test name
Test status
Simulation time 4380429932 ps
CPU time 21.55 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 250232 kb
Host smart-5837311a-653b-4f56-8905-3679c806e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334977597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2334977597
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3666884919
Short name T723
Test name
Test status
Simulation time 24533438 ps
CPU time 1.02 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 218940 kb
Host smart-901274d0-6602-4543-b9da-329d42976951
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666884919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3666884919
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4132963204
Short name T876
Test name
Test status
Simulation time 7706841713 ps
CPU time 11.02 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:54 PM PDT 24
Peak memory 233744 kb
Host smart-1ce0da82-78f2-4ad2-afa7-a7c5c14e3006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132963204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4132963204
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.598097043
Short name T541
Test name
Test status
Simulation time 82199313 ps
CPU time 2.59 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:42 PM PDT 24
Peak memory 233696 kb
Host smart-a8c2b953-6688-4df6-b402-78076b377f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598097043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.598097043
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3139238721
Short name T364
Test name
Test status
Simulation time 244868973 ps
CPU time 4.51 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 223408 kb
Host smart-4c74eced-e81c-4260-8ac4-c75b6702a971
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3139238721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3139238721
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1812884230
Short name T944
Test name
Test status
Simulation time 46076591754 ps
CPU time 93.07 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 250420 kb
Host smart-44567ab0-d079-4db5-9e66-8a7fa990b87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812884230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1812884230
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4091630925
Short name T891
Test name
Test status
Simulation time 5727576070 ps
CPU time 18.03 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 217376 kb
Host smart-da1e7569-4d9c-4bd8-b973-408c252964b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091630925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4091630925
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3109492125
Short name T552
Test name
Test status
Simulation time 1214513362 ps
CPU time 8.2 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 217296 kb
Host smart-551a51db-bed9-4bae-8477-86a1c0fef430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109492125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3109492125
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2193470060
Short name T131
Test name
Test status
Simulation time 1028997649 ps
CPU time 6.77 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 217208 kb
Host smart-dffc9c5a-db7f-4ae2-b95d-19cf144d3812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193470060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2193470060
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1382097911
Short name T372
Test name
Test status
Simulation time 56363924 ps
CPU time 0.7 seconds
Started Jul 11 04:32:19 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 206856 kb
Host smart-8a41f17b-dc84-43fa-a554-3649927275a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382097911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1382097911
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2526217086
Short name T179
Test name
Test status
Simulation time 105589157 ps
CPU time 2.98 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:36 PM PDT 24
Peak memory 233760 kb
Host smart-96ba52ac-f558-4c3f-80e5-3d0405b1d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526217086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2526217086
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2721633094
Short name T709
Test name
Test status
Simulation time 195123278 ps
CPU time 0.71 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:45 PM PDT 24
Peak memory 206264 kb
Host smart-fff9f4b6-6ddb-4d00-b952-4836f752152e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721633094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2721633094
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2546889397
Short name T271
Test name
Test status
Simulation time 1708033903 ps
CPU time 13.83 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:53 PM PDT 24
Peak memory 225504 kb
Host smart-8da080af-c5c3-4736-b35f-b4b84cf5aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546889397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2546889397
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1306950362
Short name T544
Test name
Test status
Simulation time 68689202 ps
CPU time 0.74 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 207440 kb
Host smart-13ce1f22-f1de-4b6d-86fd-d8a34d419cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306950362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1306950362
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1025947916
Short name T617
Test name
Test status
Simulation time 2430116419 ps
CPU time 49.81 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:33:36 PM PDT 24
Peak memory 256040 kb
Host smart-cea3c4f8-c3c5-4359-a133-8e5fb72a849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025947916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1025947916
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2424505480
Short name T608
Test name
Test status
Simulation time 27557215725 ps
CPU time 45.14 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 251496 kb
Host smart-0abec58a-53c3-4771-90a5-d9d472a2102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424505480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2424505480
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1095272368
Short name T31
Test name
Test status
Simulation time 3545344569 ps
CPU time 32.49 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 222508 kb
Host smart-67df22ac-f90a-4c39-b613-cbf80322a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095272368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1095272368
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4090168183
Short name T695
Test name
Test status
Simulation time 252409759 ps
CPU time 3.45 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 225524 kb
Host smart-7e85e5f4-6d41-4299-999e-56ef38cd982b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090168183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4090168183
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1291969539
Short name T630
Test name
Test status
Simulation time 125789213067 ps
CPU time 128.3 seconds
Started Jul 11 04:32:13 PM PDT 24
Finished Jul 11 04:34:53 PM PDT 24
Peak memory 255080 kb
Host smart-ed046bf8-f5ba-41f4-93d2-c9295a751fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291969539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1291969539
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1624434945
Short name T959
Test name
Test status
Simulation time 1614128881 ps
CPU time 7.09 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 233648 kb
Host smart-25664042-7413-4b80-b4b2-5680dd076ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624434945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1624434945
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.856860383
Short name T586
Test name
Test status
Simulation time 971997180 ps
CPU time 4.91 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 225484 kb
Host smart-14983464-be8b-41b7-b237-3f89f0ab3362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856860383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.856860383
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.88003456
Short name T897
Test name
Test status
Simulation time 207794312 ps
CPU time 1.02 seconds
Started Jul 11 04:32:13 PM PDT 24
Finished Jul 11 04:32:45 PM PDT 24
Peak memory 217536 kb
Host smart-e894176f-ed04-42de-8a42-5424d2f9caca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88003456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.88003456
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2497758859
Short name T262
Test name
Test status
Simulation time 8673800956 ps
CPU time 9.61 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:54 PM PDT 24
Peak memory 233704 kb
Host smart-63d59120-842b-4bf0-b1fc-8612824cee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497758859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2497758859
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2584836606
Short name T821
Test name
Test status
Simulation time 5022229314 ps
CPU time 18.67 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 233768 kb
Host smart-0733ef98-247b-49d0-8cc6-324cc760fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584836606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2584836606
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3410458981
Short name T902
Test name
Test status
Simulation time 652243549 ps
CPU time 6.24 seconds
Started Jul 11 04:32:18 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 221336 kb
Host smart-9726b5d1-4d0f-4a92-ba88-bf9e02b31d8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410458981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3410458981
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2816217294
Short name T207
Test name
Test status
Simulation time 61785508106 ps
CPU time 193.31 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:36:00 PM PDT 24
Peak memory 255600 kb
Host smart-371f1f2d-3d0e-497e-a7c3-6bdd3a955d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816217294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2816217294
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1578573579
Short name T130
Test name
Test status
Simulation time 3518418420 ps
CPU time 11.55 seconds
Started Jul 11 04:32:19 PM PDT 24
Finished Jul 11 04:33:03 PM PDT 24
Peak memory 220888 kb
Host smart-80d1db61-e028-4db3-a0c9-ef972457685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578573579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1578573579
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.94470884
Short name T686
Test name
Test status
Simulation time 14573082 ps
CPU time 0.69 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:57 PM PDT 24
Peak memory 206488 kb
Host smart-88d279a7-3565-432b-95dd-822093dfc2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94470884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.94470884
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1601008956
Short name T642
Test name
Test status
Simulation time 38345167 ps
CPU time 0.78 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:40 PM PDT 24
Peak memory 207168 kb
Host smart-2c839abb-d5ba-4c92-b908-26ba2c2da7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601008956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1601008956
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3016767640
Short name T890
Test name
Test status
Simulation time 131724401 ps
CPU time 0.83 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:44 PM PDT 24
Peak memory 206844 kb
Host smart-3d87aade-4ad7-421d-a1ef-d82f6d143657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016767640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3016767640
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2213801916
Short name T511
Test name
Test status
Simulation time 4208290170 ps
CPU time 7.89 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 238976 kb
Host smart-058253ad-bf6f-4bbc-81ca-c28c67c0fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213801916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2213801916
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.226502211
Short name T486
Test name
Test status
Simulation time 26451492 ps
CPU time 0.72 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 205684 kb
Host smart-5f6d1a6f-4ae1-4d6e-b819-48ccdcf34bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226502211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.226502211
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4028059967
Short name T659
Test name
Test status
Simulation time 19168673 ps
CPU time 0.72 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:32:55 PM PDT 24
Peak memory 206780 kb
Host smart-cf63dde4-3553-4a3f-9b43-5d6e97f173fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028059967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4028059967
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2914432633
Short name T744
Test name
Test status
Simulation time 3664346482 ps
CPU time 47.12 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 257112 kb
Host smart-1ed14873-d0c2-4695-8c5f-7b8f94cf5759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914432633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2914432633
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1836832567
Short name T228
Test name
Test status
Simulation time 9574286795 ps
CPU time 83.92 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:34:07 PM PDT 24
Peak memory 233844 kb
Host smart-ff480be1-a3e0-4a15-8fe1-63287b318bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836832567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1836832567
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2685602319
Short name T50
Test name
Test status
Simulation time 9567577295 ps
CPU time 99.53 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:34:16 PM PDT 24
Peak memory 256884 kb
Host smart-f3af420e-1dff-4137-80d7-4f3d3508bcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685602319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2685602319
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1151425432
Short name T749
Test name
Test status
Simulation time 11966341306 ps
CPU time 31.83 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:33:18 PM PDT 24
Peak memory 225628 kb
Host smart-38c241fa-bc12-4e98-8179-010a75dd87b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151425432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1151425432
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1650987070
Short name T636
Test name
Test status
Simulation time 6813043055 ps
CPU time 88.84 seconds
Started Jul 11 04:32:17 PM PDT 24
Finished Jul 11 04:34:18 PM PDT 24
Peak memory 254832 kb
Host smart-080a8cee-b72d-46cd-b89e-3b84f9933d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650987070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1650987070
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1017661167
Short name T739
Test name
Test status
Simulation time 728792399 ps
CPU time 3.02 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 233668 kb
Host smart-ac83d33f-635f-4992-a49a-9d22a18ca54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017661167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1017661167
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4024445461
Short name T689
Test name
Test status
Simulation time 163702389 ps
CPU time 2.58 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:32:42 PM PDT 24
Peak memory 225548 kb
Host smart-d72d562b-7cdd-4e2a-8df8-08b1d74ff11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024445461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4024445461
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3469333198
Short name T521
Test name
Test status
Simulation time 28548050 ps
CPU time 1.04 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:46 PM PDT 24
Peak memory 217508 kb
Host smart-2fdee329-264a-4222-9c8c-e8b9aacb0302
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469333198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3469333198
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2710230017
Short name T323
Test name
Test status
Simulation time 2040394421 ps
CPU time 7.02 seconds
Started Jul 11 04:32:12 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 233792 kb
Host smart-8801d93d-cfcc-429d-9cca-bc89f435f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710230017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2710230017
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.464129908
Short name T699
Test name
Test status
Simulation time 333186504 ps
CPU time 4.79 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 233648 kb
Host smart-21b6cebe-c3fa-4754-ab83-a7c8ee951672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464129908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.464129908
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3527993466
Short name T929
Test name
Test status
Simulation time 4103686787 ps
CPU time 9.88 seconds
Started Jul 11 04:32:11 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 223072 kb
Host smart-a3f7e300-0e0a-428e-8323-f77337b30155
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527993466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3527993466
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1809060572
Short name T229
Test name
Test status
Simulation time 263207539899 ps
CPU time 1359.65 seconds
Started Jul 11 04:32:19 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 299548 kb
Host smart-24b65435-a190-4b5f-8b3c-8822c66f19dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809060572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1809060572
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2333173090
Short name T1018
Test name
Test status
Simulation time 2467234394 ps
CPU time 11.84 seconds
Started Jul 11 04:32:13 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 217392 kb
Host smart-650d6a2d-dbd0-47b2-8bfb-b01616ae014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333173090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2333173090
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.220377212
Short name T359
Test name
Test status
Simulation time 5130697067 ps
CPU time 4.94 seconds
Started Jul 11 04:32:10 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 217444 kb
Host smart-b376307f-3e3d-4cb8-9698-d56f6f95ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220377212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.220377212
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2663615063
Short name T311
Test name
Test status
Simulation time 44938703 ps
CPU time 1.2 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 217208 kb
Host smart-98e100cf-f1d3-4c6f-ae32-38700634cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663615063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2663615063
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3353923537
Short name T1013
Test name
Test status
Simulation time 15539773 ps
CPU time 0.7 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 206852 kb
Host smart-640ffa0f-b780-491a-a59f-55193ec1b8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353923537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3353923537
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.286525618
Short name T667
Test name
Test status
Simulation time 546403874 ps
CPU time 9.87 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 233580 kb
Host smart-73b9db67-ba0f-480b-9a86-caf8f139fa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286525618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.286525618
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2234058240
Short name T746
Test name
Test status
Simulation time 14941353 ps
CPU time 0.73 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 205652 kb
Host smart-99c35b7a-454d-43d8-830b-6e3e4be612cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234058240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2234058240
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2324772043
Short name T538
Test name
Test status
Simulation time 73718479 ps
CPU time 2.16 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:33:00 PM PDT 24
Peak memory 225080 kb
Host smart-59a6cb89-dd6b-46b3-a8c0-a62a84829627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324772043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2324772043
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1362900281
Short name T995
Test name
Test status
Simulation time 20351273 ps
CPU time 0.78 seconds
Started Jul 11 04:32:20 PM PDT 24
Finished Jul 11 04:32:53 PM PDT 24
Peak memory 207392 kb
Host smart-a91c4091-637b-408f-8616-1e81ff81692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362900281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1362900281
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2598017049
Short name T786
Test name
Test status
Simulation time 3147220436 ps
CPU time 33.14 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 253460 kb
Host smart-12b4db83-1981-40a0-b11f-e2d01f7c70f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598017049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2598017049
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2314720531
Short name T83
Test name
Test status
Simulation time 3856090001 ps
CPU time 19.29 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 218792 kb
Host smart-9e68cef4-25ed-456b-9b8c-62416ca71cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314720531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2314720531
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3317647494
Short name T901
Test name
Test status
Simulation time 26638596703 ps
CPU time 225.74 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:36:43 PM PDT 24
Peak memory 258552 kb
Host smart-8b6fc015-ee8d-40c9-b4ad-bb07553d97bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317647494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3317647494
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.897679993
Short name T286
Test name
Test status
Simulation time 205720114 ps
CPU time 3.65 seconds
Started Jul 11 04:32:23 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 233696 kb
Host smart-fd423bb8-acf6-4e9e-96f3-12e3aa87b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897679993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.897679993
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1475059023
Short name T243
Test name
Test status
Simulation time 37489290688 ps
CPU time 69.14 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 238748 kb
Host smart-39fee290-d526-45a3-bcfc-54253312bb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475059023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1475059023
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2451113794
Short name T766
Test name
Test status
Simulation time 1337700068 ps
CPU time 5.72 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 225464 kb
Host smart-34c65f8b-0bb3-44b1-aab3-572bc19468d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451113794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2451113794
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3130616328
Short name T579
Test name
Test status
Simulation time 2631029955 ps
CPU time 26.68 seconds
Started Jul 11 04:32:17 PM PDT 24
Finished Jul 11 04:33:16 PM PDT 24
Peak memory 249916 kb
Host smart-906b9e27-cc9b-4c73-938f-2203b8d42ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130616328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3130616328
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1755494396
Short name T673
Test name
Test status
Simulation time 336476451 ps
CPU time 1.13 seconds
Started Jul 11 04:32:31 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 217596 kb
Host smart-ebc841a1-967d-41c7-97b5-2562019bf1bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755494396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1755494396
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3666773073
Short name T969
Test name
Test status
Simulation time 1987613025 ps
CPU time 8.15 seconds
Started Jul 11 04:32:18 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 241932 kb
Host smart-c422caee-c0b6-4259-bef4-43e57c68247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666773073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3666773073
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.872741639
Short name T74
Test name
Test status
Simulation time 6664784525 ps
CPU time 10.67 seconds
Started Jul 11 04:32:24 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 233828 kb
Host smart-ec535964-42c0-4ee9-99e3-e392c856804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872741639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.872741639
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2353025252
Short name T780
Test name
Test status
Simulation time 2570176764 ps
CPU time 13.39 seconds
Started Jul 11 04:32:14 PM PDT 24
Finished Jul 11 04:33:00 PM PDT 24
Peak memory 224124 kb
Host smart-55483ae2-11ba-4e5a-a277-c4dfd87ee043
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2353025252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2353025252
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4202882796
Short name T1017
Test name
Test status
Simulation time 11322748123 ps
CPU time 143.51 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:35:21 PM PDT 24
Peak memory 274636 kb
Host smart-bda68024-7fd7-401a-9802-868066606048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202882796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4202882796
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.166839473
Short name T818
Test name
Test status
Simulation time 15083147 ps
CPU time 0.75 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 206960 kb
Host smart-6e4f2870-87d9-4083-aa60-53769650e5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166839473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.166839473
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3155225024
Short name T883
Test name
Test status
Simulation time 8314753622 ps
CPU time 6.82 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:07 PM PDT 24
Peak memory 217376 kb
Host smart-a53bca51-1527-4328-a05d-526ec643c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155225024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3155225024
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2428595147
Short name T475
Test name
Test status
Simulation time 479829521 ps
CPU time 1.69 seconds
Started Jul 11 04:32:13 PM PDT 24
Finished Jul 11 04:32:46 PM PDT 24
Peak memory 217312 kb
Host smart-d8ca78ae-e21f-48d0-9ca2-01756d18a9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428595147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2428595147
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1142551675
Short name T916
Test name
Test status
Simulation time 42313439 ps
CPU time 0.78 seconds
Started Jul 11 04:32:23 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 206936 kb
Host smart-33ecb3f5-0205-4994-9c83-1cb46d0adf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142551675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1142551675
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1297517323
Short name T663
Test name
Test status
Simulation time 2960411199 ps
CPU time 10.05 seconds
Started Jul 11 04:32:32 PM PDT 24
Finished Jul 11 04:33:11 PM PDT 24
Peak memory 241924 kb
Host smart-b44e8bfe-fbba-4719-8837-662e6f5a445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297517323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1297517323
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4164442378
Short name T981
Test name
Test status
Simulation time 24005692 ps
CPU time 0.74 seconds
Started Jul 11 04:32:32 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 206276 kb
Host smart-547e362e-8239-46e8-9c97-351b15beedaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164442378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4164442378
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3698595061
Short name T180
Test name
Test status
Simulation time 415918419 ps
CPU time 2.6 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 225336 kb
Host smart-42fbde6c-3c74-4d68-92de-12da8747dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698595061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3698595061
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2999188059
Short name T560
Test name
Test status
Simulation time 27953076 ps
CPU time 0.76 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 206348 kb
Host smart-a95e9dc6-d032-47b4-a571-bc1ee5f7f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999188059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2999188059
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.512010059
Short name T801
Test name
Test status
Simulation time 696440635 ps
CPU time 5.1 seconds
Started Jul 11 04:32:24 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 239628 kb
Host smart-427c0900-b6e4-40b8-b3e0-8f37af188854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512010059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.512010059
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.151105072
Short name T956
Test name
Test status
Simulation time 108700596705 ps
CPU time 256.67 seconds
Started Jul 11 04:32:32 PM PDT 24
Finished Jul 11 04:37:18 PM PDT 24
Peak memory 257452 kb
Host smart-2715d83b-4b28-4e3d-9573-9366419a2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151105072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.151105072
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2679153014
Short name T245
Test name
Test status
Simulation time 15695586229 ps
CPU time 144.5 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:35:22 PM PDT 24
Peak memory 250612 kb
Host smart-3c33dba0-6eed-4117-9dab-f90227efd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679153014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2679153014
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4290737042
Short name T447
Test name
Test status
Simulation time 528653481 ps
CPU time 5.75 seconds
Started Jul 11 04:32:32 PM PDT 24
Finished Jul 11 04:33:07 PM PDT 24
Peak memory 241848 kb
Host smart-63b6422c-4d1e-4ee6-9881-9fdf7e8912b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290737042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4290737042
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.158019821
Short name T465
Test name
Test status
Simulation time 5500887369 ps
CPU time 45.85 seconds
Started Jul 11 04:32:24 PM PDT 24
Finished Jul 11 04:33:41 PM PDT 24
Peak memory 233860 kb
Host smart-f6708609-7214-4a01-a698-1264b742fc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158019821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.158019821
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.713182498
Short name T832
Test name
Test status
Simulation time 1151766056 ps
CPU time 10.64 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 225460 kb
Host smart-64191924-6a9e-46d7-9150-04261fd7b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713182498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.713182498
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.299466683
Short name T733
Test name
Test status
Simulation time 3131124320 ps
CPU time 33.3 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 241512 kb
Host smart-3c908795-6dd8-450e-8578-d10a809be31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299466683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.299466683
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1840454109
Short name T484
Test name
Test status
Simulation time 106558301 ps
CPU time 1.04 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 218832 kb
Host smart-33f95ade-1cbe-43a1-815b-8c1329c7b769
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840454109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1840454109
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1313586052
Short name T263
Test name
Test status
Simulation time 9785843408 ps
CPU time 11.74 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 241704 kb
Host smart-9ad0a535-f2bd-4b6a-9d6f-858974af4d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313586052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1313586052
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2761512736
Short name T309
Test name
Test status
Simulation time 4589718685 ps
CPU time 8.02 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:57 PM PDT 24
Peak memory 233476 kb
Host smart-891c4ab4-3e3b-4391-8d7f-b83e7d92b64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761512736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2761512736
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3008428120
Short name T1020
Test name
Test status
Simulation time 2006822907 ps
CPU time 3.61 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 220932 kb
Host smart-57105b43-2c8b-4b90-a5af-753110c117fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008428120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3008428120
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.515205526
Short name T972
Test name
Test status
Simulation time 4690029186 ps
CPU time 50.35 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 252448 kb
Host smart-c389b13b-67eb-49e1-8410-dcfed5620eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515205526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.515205526
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1414818350
Short name T373
Test name
Test status
Simulation time 3934660648 ps
CPU time 10.11 seconds
Started Jul 11 04:32:15 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 217376 kb
Host smart-45164e52-c53c-4a56-a30c-c77d86c5ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414818350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1414818350
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4055217123
Short name T375
Test name
Test status
Simulation time 5908005420 ps
CPU time 7.54 seconds
Started Jul 11 04:32:30 PM PDT 24
Finished Jul 11 04:33:08 PM PDT 24
Peak memory 217332 kb
Host smart-2927e552-7393-4748-84fa-46db7e05e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055217123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4055217123
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.391624
Short name T366
Test name
Test status
Simulation time 223753669 ps
CPU time 1.45 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:00 PM PDT 24
Peak memory 217256 kb
Host smart-d740b6dd-7ea1-4af9-8ed0-b1f11fe81c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.391624
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2611213575
Short name T645
Test name
Test status
Simulation time 223532273 ps
CPU time 0.9 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:32:55 PM PDT 24
Peak memory 206884 kb
Host smart-3e34226c-8054-4028-9e9b-0923cc3cab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611213575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2611213575
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4180794926
Short name T25
Test name
Test status
Simulation time 9844854840 ps
CPU time 9.1 seconds
Started Jul 11 04:32:20 PM PDT 24
Finished Jul 11 04:33:00 PM PDT 24
Peak memory 233816 kb
Host smart-2642484c-a8a6-402b-9b35-00ee639384f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180794926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4180794926
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2763349975
Short name T56
Test name
Test status
Simulation time 516566741 ps
CPU time 2.26 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 225408 kb
Host smart-37516d76-b07a-43f3-bc2c-96e20583872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763349975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2763349975
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2033880708
Short name T657
Test name
Test status
Simulation time 113858811 ps
CPU time 0.76 seconds
Started Jul 11 04:32:22 PM PDT 24
Finished Jul 11 04:32:53 PM PDT 24
Peak memory 206476 kb
Host smart-ff60c597-bdc7-4871-8a44-5577e5720dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033880708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2033880708
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.163932845
Short name T127
Test name
Test status
Simulation time 8099774769 ps
CPU time 42.75 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 257488 kb
Host smart-e5bfcbec-40b3-43a9-b8b8-66c479cbac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163932845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.163932845
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1092232130
Short name T458
Test name
Test status
Simulation time 14649356200 ps
CPU time 45.44 seconds
Started Jul 11 04:32:31 PM PDT 24
Finished Jul 11 04:33:47 PM PDT 24
Peak memory 225744 kb
Host smart-e2e89a0b-5ef7-49b5-97d7-90888ef766ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092232130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1092232130
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3229034865
Short name T542
Test name
Test status
Simulation time 80575861 ps
CPU time 2.38 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 225436 kb
Host smart-9237a724-3db4-454e-a759-c42e20bdbd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229034865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3229034865
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.280791304
Short name T244
Test name
Test status
Simulation time 3826591822 ps
CPU time 27.64 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:27 PM PDT 24
Peak memory 255484 kb
Host smart-f4e04208-fad1-485e-a596-0a389a8482c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280791304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.280791304
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1493107904
Short name T474
Test name
Test status
Simulation time 31700441 ps
CPU time 2.25 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 233332 kb
Host smart-d0169f37-602d-445e-b10d-5dd46e296ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493107904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1493107904
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4075585165
Short name T731
Test name
Test status
Simulation time 24589825370 ps
CPU time 77.41 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 234116 kb
Host smart-ec631b6b-e942-407d-b244-43ae441c4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075585165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4075585165
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.991805162
Short name T39
Test name
Test status
Simulation time 148101933 ps
CPU time 1.04 seconds
Started Jul 11 04:32:31 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 217840 kb
Host smart-16e21596-06a8-47bd-b47f-4bc74f0f9794
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991805162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.991805162
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2667194764
Short name T480
Test name
Test status
Simulation time 149848953090 ps
CPU time 24.63 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 233836 kb
Host smart-0c613a58-41da-4155-8bcb-256ae8c54115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667194764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2667194764
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2886557856
Short name T365
Test name
Test status
Simulation time 522402021 ps
CPU time 5.21 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 233636 kb
Host smart-667282d3-a322-42f9-97c6-e896aa29d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886557856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2886557856
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3279487323
Short name T861
Test name
Test status
Simulation time 69008452 ps
CPU time 3.36 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:04 PM PDT 24
Peak memory 223840 kb
Host smart-ea61777b-c317-4a9e-8bc4-9c1c528b8caa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3279487323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3279487323
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.599940109
Short name T16
Test name
Test status
Simulation time 210342154 ps
CPU time 1.06 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 208080 kb
Host smart-c09fc637-1da6-4001-b102-3062a3280010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599940109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.599940109
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2310060517
Short name T567
Test name
Test status
Simulation time 3311448680 ps
CPU time 22.18 seconds
Started Jul 11 04:32:23 PM PDT 24
Finished Jul 11 04:33:17 PM PDT 24
Peak memory 217364 kb
Host smart-7866349d-3c44-477a-a0c3-cd62df246ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310060517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2310060517
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.965855658
Short name T922
Test name
Test status
Simulation time 5950606358 ps
CPU time 2.47 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 217188 kb
Host smart-ecebba0b-cee9-4a38-8ef8-4c6d0118e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965855658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.965855658
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.336339479
Short name T314
Test name
Test status
Simulation time 38817308 ps
CPU time 0.66 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:56 PM PDT 24
Peak memory 206520 kb
Host smart-674cad46-79c1-4f0b-844a-68fbfc44067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336339479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.336339479
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3112477723
Short name T439
Test name
Test status
Simulation time 26993626 ps
CPU time 0.78 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:57 PM PDT 24
Peak memory 207176 kb
Host smart-3726de69-45e8-4231-966c-4e627e81c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112477723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3112477723
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2835549652
Short name T728
Test name
Test status
Simulation time 350454309 ps
CPU time 6.94 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 250076 kb
Host smart-42003ae9-e018-446a-b1ae-ed810095f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835549652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2835549652
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3718101466
Short name T942
Test name
Test status
Simulation time 12261721 ps
CPU time 0.71 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 206256 kb
Host smart-1638a445-fe59-4de4-b267-d754251a95c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718101466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3718101466
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4099388302
Short name T878
Test name
Test status
Simulation time 4247505717 ps
CPU time 8.81 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:09 PM PDT 24
Peak memory 233860 kb
Host smart-347ccd08-443f-4f0e-81e2-1c882d606d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099388302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4099388302
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2706154233
Short name T337
Test name
Test status
Simulation time 55557495 ps
CPU time 0.79 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 207696 kb
Host smart-75b43f5c-ae93-4c70-aebe-0f4255747c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706154233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2706154233
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1582687601
Short name T466
Test name
Test status
Simulation time 28937079166 ps
CPU time 98.65 seconds
Started Jul 11 04:32:35 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 250148 kb
Host smart-ae251272-6ea5-4472-b979-44176ebc8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582687601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1582687601
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2834654813
Short name T716
Test name
Test status
Simulation time 6394527394 ps
CPU time 25.45 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 218760 kb
Host smart-130d576f-f3b2-44c0-8cd6-72791b148ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834654813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2834654813
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.829080711
Short name T628
Test name
Test status
Simulation time 5704048407 ps
CPU time 40.63 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 241464 kb
Host smart-c1270fc8-9e51-4aee-92ff-16315b04e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829080711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.829080711
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.963255083
Short name T597
Test name
Test status
Simulation time 192513967 ps
CPU time 3.9 seconds
Started Jul 11 04:32:31 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 233668 kb
Host smart-4a1820e5-77c4-48ce-82bd-e89e6f77d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963255083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.963255083
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3863446928
Short name T505
Test name
Test status
Simulation time 81154687927 ps
CPU time 175.9 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:35:54 PM PDT 24
Peak memory 258388 kb
Host smart-9403a231-93a9-4e2f-8fe2-9157cb679215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863446928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3863446928
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2084525331
Short name T1022
Test name
Test status
Simulation time 3771421835 ps
CPU time 22.83 seconds
Started Jul 11 04:32:25 PM PDT 24
Finished Jul 11 04:33:19 PM PDT 24
Peak memory 233840 kb
Host smart-26d8bb19-d818-485c-8ebe-e2cfb47dbd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084525331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2084525331
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1520193088
Short name T1009
Test name
Test status
Simulation time 4164782086 ps
CPU time 25.59 seconds
Started Jul 11 04:32:32 PM PDT 24
Finished Jul 11 04:33:27 PM PDT 24
Peak memory 233784 kb
Host smart-6a8327dc-9fab-44df-93ea-9d31377daec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520193088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1520193088
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2126510567
Short name T1000
Test name
Test status
Simulation time 29980158 ps
CPU time 0.99 seconds
Started Jul 11 04:32:30 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 218808 kb
Host smart-38633b25-3f81-4a0c-9547-a96c48c0e4d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126510567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2126510567
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3772155575
Short name T625
Test name
Test status
Simulation time 50680353 ps
CPU time 2.77 seconds
Started Jul 11 04:32:35 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 233644 kb
Host smart-8dbfe605-1153-4e4f-a765-7989e43c4fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772155575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3772155575
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3104266482
Short name T888
Test name
Test status
Simulation time 1074170371 ps
CPU time 5.02 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 233636 kb
Host smart-82592084-6c0b-4ed9-95df-0e70f2bb8330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104266482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3104266482
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2959842115
Short name T468
Test name
Test status
Simulation time 539072202 ps
CPU time 6.07 seconds
Started Jul 11 04:32:29 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 219740 kb
Host smart-805026d6-d799-4367-9fb3-065403977306
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2959842115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2959842115
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2281939958
Short name T858
Test name
Test status
Simulation time 57631307 ps
CPU time 0.96 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 208556 kb
Host smart-7585d0aa-4d62-4648-ad12-dc1f528b1c1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281939958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2281939958
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4000743261
Short name T992
Test name
Test status
Simulation time 2214411376 ps
CPU time 15.02 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:19 PM PDT 24
Peak memory 217456 kb
Host smart-07ca2a60-0152-4308-a15b-bf9d23f2ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000743261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4000743261
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1343527901
Short name T952
Test name
Test status
Simulation time 3049606560 ps
CPU time 5.55 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 217340 kb
Host smart-cfdc59e3-d8dc-408e-8b90-c3db2a61a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343527901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1343527901
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2630468830
Short name T934
Test name
Test status
Simulation time 12055576 ps
CPU time 0.68 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 206500 kb
Host smart-d51c0c1f-e0de-4073-a08e-e5e1e77a6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630468830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2630468830
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3839115676
Short name T847
Test name
Test status
Simulation time 191910188 ps
CPU time 0.81 seconds
Started Jul 11 04:32:27 PM PDT 24
Finished Jul 11 04:32:59 PM PDT 24
Peak memory 206844 kb
Host smart-0a4f290e-fed1-4abc-b4e1-17c8e0481888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839115676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3839115676
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2059169111
Short name T340
Test name
Test status
Simulation time 124539912 ps
CPU time 3.29 seconds
Started Jul 11 04:32:26 PM PDT 24
Finished Jul 11 04:33:01 PM PDT 24
Peak memory 233724 kb
Host smart-e82111a0-ec2e-4742-8f1e-8f9b2a6902d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059169111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2059169111
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3515568853
Short name T371
Test name
Test status
Simulation time 14035660 ps
CPU time 0.7 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:13 PM PDT 24
Peak memory 206192 kb
Host smart-b827b41c-78ff-4dad-ba3c-40f4ed3f7642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515568853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
515568853
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3040528983
Short name T912
Test name
Test status
Simulation time 364442357 ps
CPU time 3.2 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 233648 kb
Host smart-ac74f740-9e9d-4d81-8823-81f4702e2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040528983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3040528983
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2760869665
Short name T975
Test name
Test status
Simulation time 16344293 ps
CPU time 0.78 seconds
Started Jul 11 04:31:24 PM PDT 24
Finished Jul 11 04:31:44 PM PDT 24
Peak memory 207812 kb
Host smart-2505fcfa-8ca9-4ee4-bb99-b6802dfe0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760869665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2760869665
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1492458288
Short name T618
Test name
Test status
Simulation time 62386624106 ps
CPU time 25.3 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 242048 kb
Host smart-3ba9f960-c1dd-4625-bf76-332ec0b582e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492458288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1492458288
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.684977853
Short name T295
Test name
Test status
Simulation time 11702519136 ps
CPU time 103.47 seconds
Started Jul 11 04:31:40 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 249864 kb
Host smart-61e16c38-f15f-44cb-a227-2e951380f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684977853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.684977853
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2388125883
Short name T301
Test name
Test status
Simulation time 6639534821 ps
CPU time 95.2 seconds
Started Jul 11 04:31:40 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 255032 kb
Host smart-1b1d5b82-38b7-4ab9-9357-b5df389ab567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388125883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2388125883
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2995978973
Short name T498
Test name
Test status
Simulation time 1859317333 ps
CPU time 16.76 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:32:21 PM PDT 24
Peak memory 225416 kb
Host smart-756921da-fbcd-479b-a835-d21931ccaa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995978973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2995978973
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3978485453
Short name T968
Test name
Test status
Simulation time 8867547044 ps
CPU time 58.27 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:33:02 PM PDT 24
Peak memory 251188 kb
Host smart-973aa46b-44d2-4906-bd3b-520ec0dce092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978485453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3978485453
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3439812173
Short name T254
Test name
Test status
Simulation time 14104094386 ps
CPU time 11.89 seconds
Started Jul 11 04:31:28 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 233708 kb
Host smart-60bbc342-f7bf-4677-b30c-82ce13583ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439812173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3439812173
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3454333166
Short name T58
Test name
Test status
Simulation time 638868731 ps
CPU time 9.6 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:25 PM PDT 24
Peak memory 225440 kb
Host smart-1c0e506e-2a26-4509-b9ef-ff2c671bb531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454333166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3454333166
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.14141529
Short name T38
Test name
Test status
Simulation time 150626532 ps
CPU time 1.03 seconds
Started Jul 11 04:31:36 PM PDT 24
Finished Jul 11 04:31:56 PM PDT 24
Peak memory 217644 kb
Host smart-f5ba208c-8c28-481a-9139-9ce2f7345627
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.14141529
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.698465690
Short name T275
Test name
Test status
Simulation time 1529732997 ps
CPU time 8.22 seconds
Started Jul 11 04:31:32 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 233640 kb
Host smart-0e100028-79d1-4f18-aa8b-3adc7467770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698465690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
698465690
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2020101066
Short name T184
Test name
Test status
Simulation time 4964134542 ps
CPU time 10.19 seconds
Started Jul 11 04:31:36 PM PDT 24
Finished Jul 11 04:32:05 PM PDT 24
Peak memory 233808 kb
Host smart-4ba4007c-97fe-467b-8abd-3cfa0ae56e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020101066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2020101066
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.422856990
Short name T524
Test name
Test status
Simulation time 1161888153 ps
CPU time 3.35 seconds
Started Jul 11 04:31:31 PM PDT 24
Finished Jul 11 04:31:52 PM PDT 24
Peak memory 221616 kb
Host smart-8bc8228f-f4c1-49c8-8000-8edee7795fbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=422856990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.422856990
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2477132781
Short name T65
Test name
Test status
Simulation time 335325110 ps
CPU time 1.13 seconds
Started Jul 11 04:31:46 PM PDT 24
Finished Jul 11 04:32:09 PM PDT 24
Peak memory 236740 kb
Host smart-b8831edf-f483-4b98-bf21-86af5b158cab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477132781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2477132781
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3377544084
Short name T297
Test name
Test status
Simulation time 1263689619 ps
CPU time 8.89 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:11 PM PDT 24
Peak memory 217236 kb
Host smart-d8220fc7-2ab0-4141-b50f-6f4a28fb9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377544084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3377544084
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1005723720
Short name T549
Test name
Test status
Simulation time 1813416496 ps
CPU time 5.18 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:32:09 PM PDT 24
Peak memory 217188 kb
Host smart-dafac797-8ac8-401b-b1dc-c3be5e034989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005723720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1005723720
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2021809098
Short name T320
Test name
Test status
Simulation time 43775488 ps
CPU time 0.75 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:32:04 PM PDT 24
Peak memory 206856 kb
Host smart-05977e87-f94b-465d-ae3c-bc1a01d427c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021809098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2021809098
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3273915212
Short name T330
Test name
Test status
Simulation time 28342448 ps
CPU time 0.7 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 206904 kb
Host smart-88b9a629-8add-428a-a20d-7eb76f1e263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273915212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3273915212
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1744207606
Short name T533
Test name
Test status
Simulation time 7883573289 ps
CPU time 7.85 seconds
Started Jul 11 04:31:35 PM PDT 24
Finished Jul 11 04:32:01 PM PDT 24
Peak memory 233724 kb
Host smart-3f2de4de-5166-4b31-9d5e-7037947898bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744207606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1744207606
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.993121845
Short name T545
Test name
Test status
Simulation time 43853536 ps
CPU time 0.7 seconds
Started Jul 11 04:32:36 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 205772 kb
Host smart-1ac00ad1-91b2-48ef-b3d5-23c266f11460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993121845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.993121845
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2618627826
Short name T479
Test name
Test status
Simulation time 500150674 ps
CPU time 2.3 seconds
Started Jul 11 04:32:37 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 233684 kb
Host smart-9dfa4354-923b-4196-a78d-afd98b58ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618627826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2618627826
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2569023608
Short name T765
Test name
Test status
Simulation time 63187175 ps
CPU time 0.8 seconds
Started Jul 11 04:32:28 PM PDT 24
Finished Jul 11 04:33:00 PM PDT 24
Peak memory 207720 kb
Host smart-a4fbdcf8-e49b-44e5-81ad-5adb7f256825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569023608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2569023608
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4173274903
Short name T682
Test name
Test status
Simulation time 23882154 ps
CPU time 0.75 seconds
Started Jul 11 04:32:37 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 216876 kb
Host smart-b62e39b1-5a8d-42b4-9454-e857eadea712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173274903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4173274903
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2706358843
Short name T226
Test name
Test status
Simulation time 25417167610 ps
CPU time 44.7 seconds
Started Jul 11 04:32:31 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 240740 kb
Host smart-63788de6-4a81-4c48-b327-96d4117587ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706358843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2706358843
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3642182159
Short name T264
Test name
Test status
Simulation time 25445266633 ps
CPU time 54.72 seconds
Started Jul 11 04:32:33 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 251356 kb
Host smart-810b880d-67b1-4b97-92b2-cbdd01b4aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642182159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3642182159
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2337377596
Short name T578
Test name
Test status
Simulation time 279279841 ps
CPU time 6.22 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 233632 kb
Host smart-b9927692-77bb-4ab7-8b4f-038843728954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337377596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2337377596
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1068978004
Short name T631
Test name
Test status
Simulation time 20111894220 ps
CPU time 144.19 seconds
Started Jul 11 04:32:40 PM PDT 24
Finished Jul 11 04:35:31 PM PDT 24
Peak memory 251696 kb
Host smart-2088220e-a8d5-4f22-8e4f-7e4504196f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068978004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1068978004
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1388648881
Short name T255
Test name
Test status
Simulation time 235204130 ps
CPU time 3.43 seconds
Started Jul 11 04:32:37 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 229420 kb
Host smart-86ed3ff3-a2a9-42ba-b6b4-cc2dda0d69ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388648881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1388648881
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3490367196
Short name T342
Test name
Test status
Simulation time 16237881889 ps
CPU time 26.55 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:30 PM PDT 24
Peak memory 233692 kb
Host smart-67bd0b9a-1c5f-4b2b-9651-b8db2bb9eaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490367196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3490367196
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1599293373
Short name T650
Test name
Test status
Simulation time 161996851 ps
CPU time 2.84 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:11 PM PDT 24
Peak memory 233668 kb
Host smart-504b3592-8fd7-48f3-8835-08c15a691daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599293373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1599293373
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2164110298
Short name T778
Test name
Test status
Simulation time 12583623354 ps
CPU time 7.19 seconds
Started Jul 11 04:32:36 PM PDT 24
Finished Jul 11 04:33:11 PM PDT 24
Peak memory 237372 kb
Host smart-cb6c94b5-e344-4f40-90f1-6df8101e2072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164110298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2164110298
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3334785360
Short name T595
Test name
Test status
Simulation time 612292688 ps
CPU time 8.71 seconds
Started Jul 11 04:32:39 PM PDT 24
Finished Jul 11 04:33:15 PM PDT 24
Peak memory 220424 kb
Host smart-9c12a1d1-04b7-441a-9b3c-f1a466feb1f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3334785360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3334785360
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2596703002
Short name T232
Test name
Test status
Simulation time 15866888642 ps
CPU time 48.48 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:56 PM PDT 24
Peak memory 258356 kb
Host smart-39f2e4d3-4a4f-4c52-8f5e-04ce4a73fd59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596703002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2596703002
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2094934980
Short name T993
Test name
Test status
Simulation time 13139949 ps
CPU time 0.74 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:08 PM PDT 24
Peak memory 206516 kb
Host smart-8191f11e-5a11-42ee-9575-ff774a54522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094934980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2094934980
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4276382972
Short name T167
Test name
Test status
Simulation time 43009421 ps
CPU time 0.67 seconds
Started Jul 11 04:32:37 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 206524 kb
Host smart-5821ffe4-44fb-4b05-b0f5-d448748842e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276382972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4276382972
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1093991038
Short name T590
Test name
Test status
Simulation time 500143291 ps
CPU time 7.85 seconds
Started Jul 11 04:32:33 PM PDT 24
Finished Jul 11 04:33:11 PM PDT 24
Peak memory 217576 kb
Host smart-dc132d78-6df7-4c84-b17c-db7ccf3a1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093991038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1093991038
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2592150765
Short name T517
Test name
Test status
Simulation time 86789947 ps
CPU time 0.96 seconds
Started Jul 11 04:32:35 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 207920 kb
Host smart-09849e8e-4712-46bf-9d41-431162b13bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592150765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2592150765
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2402115869
Short name T725
Test name
Test status
Simulation time 20900147995 ps
CPU time 17.84 seconds
Started Jul 11 04:32:47 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 233848 kb
Host smart-c6eaa919-22fc-4749-9e0a-e9379628b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402115869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2402115869
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3164035307
Short name T581
Test name
Test status
Simulation time 27084800 ps
CPU time 0.72 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:08 PM PDT 24
Peak memory 206252 kb
Host smart-554d1acb-e99e-4c2b-9f00-8bb9675e162e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164035307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3164035307
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1521847763
Short name T90
Test name
Test status
Simulation time 461798958 ps
CPU time 6.37 seconds
Started Jul 11 04:32:38 PM PDT 24
Finished Jul 11 04:33:13 PM PDT 24
Peak memory 233676 kb
Host smart-889582c1-c3cf-4bc0-bed7-9512503d73ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521847763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1521847763
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.217597676
Short name T894
Test name
Test status
Simulation time 21563892 ps
CPU time 0.78 seconds
Started Jul 11 04:32:38 PM PDT 24
Finished Jul 11 04:33:08 PM PDT 24
Peak memory 207468 kb
Host smart-5a6ec6b2-96b4-48c9-948b-7673f07ddc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217597676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.217597676
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2306218475
Short name T233
Test name
Test status
Simulation time 19933550393 ps
CPU time 201.89 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:36:32 PM PDT 24
Peak memory 257212 kb
Host smart-5de1f3a0-a417-4a62-9f09-fb7374608a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306218475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2306218475
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1436819933
Short name T603
Test name
Test status
Simulation time 725633083 ps
CPU time 15.01 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:22 PM PDT 24
Peak memory 241968 kb
Host smart-ae688b97-9010-4186-8e3a-78d787ab5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436819933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1436819933
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3118992009
Short name T461
Test name
Test status
Simulation time 1728050362 ps
CPU time 5.34 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:13 PM PDT 24
Peak memory 225444 kb
Host smart-b3305bf5-69ed-4130-935a-25eb0fc7bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118992009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3118992009
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2676466972
Short name T529
Test name
Test status
Simulation time 32906927 ps
CPU time 0.75 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:09 PM PDT 24
Peak memory 217116 kb
Host smart-457fc23f-9342-43a4-a83c-36f2dab51ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676466972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2676466972
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.924291055
Short name T258
Test name
Test status
Simulation time 569905393 ps
CPU time 4.57 seconds
Started Jul 11 04:32:36 PM PDT 24
Finished Jul 11 04:33:09 PM PDT 24
Peak memory 225484 kb
Host smart-4138d545-3f6f-48c4-ae2f-72baddd3d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924291055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.924291055
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3410693057
Short name T385
Test name
Test status
Simulation time 358598785 ps
CPU time 3.06 seconds
Started Jul 11 04:32:35 PM PDT 24
Finished Jul 11 04:33:07 PM PDT 24
Peak memory 233732 kb
Host smart-c9e91cdc-fc1c-4439-a2ba-8e7ce352d52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410693057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3410693057
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1420838395
Short name T273
Test name
Test status
Simulation time 95836609 ps
CPU time 2.47 seconds
Started Jul 11 04:32:38 PM PDT 24
Finished Jul 11 04:33:07 PM PDT 24
Peak memory 225372 kb
Host smart-eaf242e1-011f-4190-9349-4526042c6a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420838395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1420838395
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2258268239
Short name T967
Test name
Test status
Simulation time 402140529 ps
CPU time 4.7 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:33:15 PM PDT 24
Peak memory 233620 kb
Host smart-196d3969-f65d-42bb-acd2-1169a3cfdb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258268239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2258268239
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3722672397
Short name T426
Test name
Test status
Simulation time 70989819 ps
CPU time 3.37 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 224064 kb
Host smart-11c78d27-d422-4364-b172-9695aa0e8e33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722672397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3722672397
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2314785449
Short name T157
Test name
Test status
Simulation time 244935157 ps
CPU time 1.07 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 208508 kb
Host smart-c35838e3-c25e-49e2-b330-10a7e8958188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314785449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2314785449
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3503512607
Short name T830
Test name
Test status
Simulation time 28968146716 ps
CPU time 26.81 seconds
Started Jul 11 04:32:43 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 217492 kb
Host smart-eab669b4-a714-4ba8-b7f6-f42661aa8df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503512607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3503512607
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2678831
Short name T957
Test name
Test status
Simulation time 6891595847 ps
CPU time 20.79 seconds
Started Jul 11 04:32:36 PM PDT 24
Finished Jul 11 04:33:25 PM PDT 24
Peak memory 217404 kb
Host smart-35486c27-3c25-454b-9064-eb4df773a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2678831
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2781491342
Short name T945
Test name
Test status
Simulation time 113685916 ps
CPU time 0.95 seconds
Started Jul 11 04:32:47 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 207980 kb
Host smart-b91d2252-3418-4c07-b8b7-6f1d7f7a1a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781491342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2781491342
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3161372908
Short name T555
Test name
Test status
Simulation time 18692205 ps
CPU time 0.71 seconds
Started Jul 11 04:32:47 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 206948 kb
Host smart-45df9efc-8e14-4c8f-ae92-9a53e3c4383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161372908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3161372908
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3373874747
Short name T256
Test name
Test status
Simulation time 9241423834 ps
CPU time 6.81 seconds
Started Jul 11 04:32:34 PM PDT 24
Finished Jul 11 04:33:10 PM PDT 24
Peak memory 225484 kb
Host smart-b8fd6d7f-81e3-4b51-ab1f-8b8765650467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373874747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3373874747
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2496151787
Short name T393
Test name
Test status
Simulation time 82563415 ps
CPU time 0.72 seconds
Started Jul 11 04:32:47 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 205772 kb
Host smart-b9dc235f-49e5-4d8c-8275-3e7525983638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496151787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2496151787
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3207909519
Short name T587
Test name
Test status
Simulation time 300874349 ps
CPU time 2.69 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:11 PM PDT 24
Peak memory 225748 kb
Host smart-78ae000d-ed6d-408f-afa4-b5e075091b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207909519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3207909519
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2916824197
Short name T867
Test name
Test status
Simulation time 23259949 ps
CPU time 0.83 seconds
Started Jul 11 04:32:50 PM PDT 24
Finished Jul 11 04:33:15 PM PDT 24
Peak memory 207480 kb
Host smart-360438ec-d30e-4b97-9026-9eb891ac33fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916824197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2916824197
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1462264183
Short name T996
Test name
Test status
Simulation time 23262603895 ps
CPU time 157.05 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:35:50 PM PDT 24
Peak memory 250296 kb
Host smart-2a833028-8ee4-42c8-8103-399a055e0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462264183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1462264183
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.161776517
Short name T54
Test name
Test status
Simulation time 33016649617 ps
CPU time 290.63 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:38:03 PM PDT 24
Peak memory 251412 kb
Host smart-6847b055-25ec-405a-997e-589b3e3d62d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161776517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.161776517
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3062858954
Short name T989
Test name
Test status
Simulation time 6924617330 ps
CPU time 40.98 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 250760 kb
Host smart-e3547427-eae9-487e-bc70-1ef2c8f86d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062858954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3062858954
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.296398169
Short name T510
Test name
Test status
Simulation time 326528232 ps
CPU time 4.58 seconds
Started Jul 11 04:32:47 PM PDT 24
Finished Jul 11 04:33:16 PM PDT 24
Peak memory 225552 kb
Host smart-0224d90d-0c46-4b4b-b721-00e76666295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296398169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.296398169
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1591401547
Short name T268
Test name
Test status
Simulation time 418652701 ps
CPU time 4.9 seconds
Started Jul 11 04:32:42 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 233696 kb
Host smart-6b3b5bc9-23d5-44a5-89ab-d2020eaf1b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591401547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1591401547
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3273973273
Short name T842
Test name
Test status
Simulation time 3817841324 ps
CPU time 15.12 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:22 PM PDT 24
Peak memory 233720 kb
Host smart-81bb82ab-a930-427f-a381-cd0e0cb246c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273973273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3273973273
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.574608672
Short name T520
Test name
Test status
Simulation time 1500595847 ps
CPU time 10.61 seconds
Started Jul 11 04:32:42 PM PDT 24
Finished Jul 11 04:33:18 PM PDT 24
Peak memory 239168 kb
Host smart-0ce38ecc-7856-4ddf-bea3-f89ca9b77dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574608672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.574608672
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2081119652
Short name T3
Test name
Test status
Simulation time 713652673 ps
CPU time 5.89 seconds
Started Jul 11 04:32:45 PM PDT 24
Finished Jul 11 04:33:16 PM PDT 24
Peak memory 233628 kb
Host smart-67dc3033-1032-4a8b-8bb7-73c0516abc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081119652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2081119652
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.660569078
Short name T68
Test name
Test status
Simulation time 1824994870 ps
CPU time 15.78 seconds
Started Jul 11 04:32:40 PM PDT 24
Finished Jul 11 04:33:22 PM PDT 24
Peak memory 220892 kb
Host smart-6a145797-d69e-4d72-a946-613853ad513a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=660569078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.660569078
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4104757544
Short name T442
Test name
Test status
Simulation time 180391436 ps
CPU time 0.91 seconds
Started Jul 11 04:32:49 PM PDT 24
Finished Jul 11 04:33:15 PM PDT 24
Peak memory 207380 kb
Host smart-969fcacd-5262-4c48-b714-2836ebb28381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104757544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4104757544
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1103726258
Short name T412
Test name
Test status
Simulation time 1337130363 ps
CPU time 7.33 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:33:17 PM PDT 24
Peak memory 217220 kb
Host smart-b291807d-b888-411f-a0b7-0d30a341b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103726258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1103726258
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.552311417
Short name T835
Test name
Test status
Simulation time 15063184695 ps
CPU time 18.44 seconds
Started Jul 11 04:32:49 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 217252 kb
Host smart-9509872b-535a-443a-bbd1-424d4968c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552311417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.552311417
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4136062150
Short name T539
Test name
Test status
Simulation time 160991638 ps
CPU time 0.88 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 206668 kb
Host smart-b48e14ed-21ac-4dbe-9553-a0e51dcdb69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136062150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4136062150
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.189283136
Short name T900
Test name
Test status
Simulation time 192972516 ps
CPU time 0.86 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 207384 kb
Host smart-5dab6db8-cde5-407c-9610-6f496af4279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189283136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.189283136
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2590650042
Short name T531
Test name
Test status
Simulation time 458604919 ps
CPU time 3.71 seconds
Started Jul 11 04:32:44 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 225440 kb
Host smart-7ca39a6f-e8c6-4727-85d9-cda9cebe4fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590650042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2590650042
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2810268339
Short name T353
Test name
Test status
Simulation time 25950209 ps
CPU time 0.74 seconds
Started Jul 11 04:32:55 PM PDT 24
Finished Jul 11 04:33:19 PM PDT 24
Peak memory 206364 kb
Host smart-e730b591-1226-4792-a367-c216d0f59dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810268339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2810268339
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2679961913
Short name T851
Test name
Test status
Simulation time 2165713635 ps
CPU time 6.12 seconds
Started Jul 11 04:32:55 PM PDT 24
Finished Jul 11 04:33:24 PM PDT 24
Peak memory 225668 kb
Host smart-3170c476-831e-43dc-88a3-ac0acf07154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679961913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2679961913
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2338939623
Short name T72
Test name
Test status
Simulation time 15476728 ps
CPU time 0.84 seconds
Started Jul 11 04:32:50 PM PDT 24
Finished Jul 11 04:33:15 PM PDT 24
Peak memory 207472 kb
Host smart-49ff6d51-2265-4892-b63c-e2402258ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338939623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2338939623
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1886030373
Short name T234
Test name
Test status
Simulation time 12067720787 ps
CPU time 38.12 seconds
Started Jul 11 04:32:46 PM PDT 24
Finished Jul 11 04:33:49 PM PDT 24
Peak memory 235924 kb
Host smart-011cbb6e-e60e-468f-a833-aebf13419722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886030373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1886030373
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2165207504
Short name T123
Test name
Test status
Simulation time 28928599301 ps
CPU time 313.2 seconds
Started Jul 11 04:32:46 PM PDT 24
Finished Jul 11 04:38:24 PM PDT 24
Peak memory 258424 kb
Host smart-af8d8807-09f5-4148-9012-70113d6a9eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165207504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2165207504
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3539942064
Short name T43
Test name
Test status
Simulation time 116019419739 ps
CPU time 564.22 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:42:39 PM PDT 24
Peak memory 267056 kb
Host smart-45a9f688-d462-40d3-976f-843529879e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539942064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3539942064
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.813879003
Short name T409
Test name
Test status
Simulation time 469848042 ps
CPU time 4.1 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 225424 kb
Host smart-5e25e103-b376-4622-999f-9d7016ae658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813879003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.813879003
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1876724081
Short name T92
Test name
Test status
Simulation time 2458007058 ps
CPU time 48.84 seconds
Started Jul 11 04:32:49 PM PDT 24
Finished Jul 11 04:34:02 PM PDT 24
Peak memory 251272 kb
Host smart-2787f632-be0d-4ae2-a848-684892133617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876724081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1876724081
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2833659360
Short name T460
Test name
Test status
Simulation time 974187399 ps
CPU time 2.99 seconds
Started Jul 11 04:32:46 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 225748 kb
Host smart-832f4261-17c1-434f-b315-687a75d9c33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833659360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2833659360
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3009951118
Short name T276
Test name
Test status
Simulation time 14655543903 ps
CPU time 26.77 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 225560 kb
Host smart-553ce57a-494a-45b9-93fc-3d34942590d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009951118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3009951118
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3495577779
Short name T543
Test name
Test status
Simulation time 2522562343 ps
CPU time 6.2 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 225640 kb
Host smart-cc18972c-df17-435d-9a8b-3de593107624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495577779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3495577779
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.995037193
Short name T817
Test name
Test status
Simulation time 1110521589 ps
CPU time 4.92 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 233728 kb
Host smart-f6683e33-a008-4774-b7ef-290e70578f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995037193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.995037193
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.393575535
Short name T45
Test name
Test status
Simulation time 4951346270 ps
CPU time 9.97 seconds
Started Jul 11 04:32:50 PM PDT 24
Finished Jul 11 04:33:24 PM PDT 24
Peak memory 221060 kb
Host smart-3ea0c722-d9af-4087-a902-1fd3d36547c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=393575535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.393575535
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.681851063
Short name T463
Test name
Test status
Simulation time 36051843 ps
CPU time 0.9 seconds
Started Jul 11 04:32:50 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 208560 kb
Host smart-c770319c-3180-44c8-894d-317b57836499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681851063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.681851063
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3046855302
Short name T747
Test name
Test status
Simulation time 5115134763 ps
CPU time 25.72 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 221096 kb
Host smart-42330f71-d9f6-420b-8fe3-a16b6834cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046855302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3046855302
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1815981275
Short name T335
Test name
Test status
Simulation time 3696247777 ps
CPU time 7.32 seconds
Started Jul 11 04:32:41 PM PDT 24
Finished Jul 11 04:33:16 PM PDT 24
Peak memory 217260 kb
Host smart-ce1a6c09-c6c0-452e-9054-cbaf2e8a8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815981275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1815981275
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3376803664
Short name T427
Test name
Test status
Simulation time 477736544 ps
CPU time 2.16 seconds
Started Jul 11 04:32:50 PM PDT 24
Finished Jul 11 04:33:17 PM PDT 24
Peak memory 217372 kb
Host smart-c0a044bf-703b-46a7-9fcd-b42ec8a21bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376803664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3376803664
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3501247659
Short name T414
Test name
Test status
Simulation time 30642204 ps
CPU time 0.78 seconds
Started Jul 11 04:32:46 PM PDT 24
Finished Jul 11 04:33:12 PM PDT 24
Peak memory 206808 kb
Host smart-ca93e18a-7b37-4550-aa25-ae2999fad055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501247659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3501247659
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1379105754
Short name T438
Test name
Test status
Simulation time 9836982163 ps
CPU time 8.13 seconds
Started Jul 11 04:32:55 PM PDT 24
Finished Jul 11 04:33:26 PM PDT 24
Peak memory 225680 kb
Host smart-9406123f-5742-4ae2-b2c4-e1c06cb3e093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379105754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1379105754
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.352682870
Short name T576
Test name
Test status
Simulation time 12671531 ps
CPU time 0.69 seconds
Started Jul 11 04:32:56 PM PDT 24
Finished Jul 11 04:33:20 PM PDT 24
Peak memory 206680 kb
Host smart-c79e1238-3558-44b2-9976-e014baf93c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352682870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.352682870
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1563386134
Short name T905
Test name
Test status
Simulation time 534010432 ps
CPU time 3.28 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:20 PM PDT 24
Peak memory 225456 kb
Host smart-1dcb87cf-15a3-424a-bec7-a76f05f553aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563386134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1563386134
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3026825350
Short name T806
Test name
Test status
Simulation time 16021965 ps
CPU time 0.8 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:16 PM PDT 24
Peak memory 207476 kb
Host smart-9ba30f19-de4e-42bd-af24-c433fd3247ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026825350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3026825350
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.899395171
Short name T713
Test name
Test status
Simulation time 5108595180 ps
CPU time 63.15 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:34:41 PM PDT 24
Peak memory 267116 kb
Host smart-65e587cd-4d86-413b-b83c-471ec22aa40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899395171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.899395171
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3407295463
Short name T704
Test name
Test status
Simulation time 16829526627 ps
CPU time 20.2 seconds
Started Jul 11 04:33:03 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 242064 kb
Host smart-a2f02bba-2aa0-436d-a369-4d4a6f2a79e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407295463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3407295463
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.505936021
Short name T884
Test name
Test status
Simulation time 2710362799 ps
CPU time 3.17 seconds
Started Jul 11 04:33:00 PM PDT 24
Finished Jul 11 04:33:24 PM PDT 24
Peak memory 225544 kb
Host smart-34889a96-f363-4a2f-a12c-47ed4d6fbe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505936021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.505936021
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3184985585
Short name T170
Test name
Test status
Simulation time 77316291070 ps
CPU time 486.85 seconds
Started Jul 11 04:32:55 PM PDT 24
Finished Jul 11 04:41:25 PM PDT 24
Peak memory 266204 kb
Host smart-ef774844-2116-4714-b31a-efaaa1010b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184985585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3184985585
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3274030598
Short name T249
Test name
Test status
Simulation time 4609054841 ps
CPU time 14.12 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 225660 kb
Host smart-0d6d58ba-caea-413c-854d-dd5114a78365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274030598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3274030598
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1149156315
Short name T998
Test name
Test status
Simulation time 9753498855 ps
CPU time 27.38 seconds
Started Jul 11 04:33:02 PM PDT 24
Finished Jul 11 04:33:50 PM PDT 24
Peak memory 237716 kb
Host smart-1494ced3-1358-431e-b834-8b21ae90f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149156315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1149156315
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3871038264
Short name T844
Test name
Test status
Simulation time 57718546 ps
CPU time 2.23 seconds
Started Jul 11 04:32:57 PM PDT 24
Finished Jul 11 04:33:22 PM PDT 24
Peak memory 233428 kb
Host smart-ca6d651f-5a2c-46b5-859a-ccd457b8bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871038264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3871038264
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.420387404
Short name T775
Test name
Test status
Simulation time 576885842 ps
CPU time 5.89 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 233700 kb
Host smart-6d5ac638-db4c-450c-8523-3aa7ec7ac1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420387404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.420387404
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3106937023
Short name T661
Test name
Test status
Simulation time 320744911 ps
CPU time 3.22 seconds
Started Jul 11 04:32:57 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 221184 kb
Host smart-b4e422c6-927d-4280-b7f9-7fbc7c940c24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106937023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3106937023
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1418237834
Short name T230
Test name
Test status
Simulation time 31248541590 ps
CPU time 356.48 seconds
Started Jul 11 04:32:58 PM PDT 24
Finished Jul 11 04:39:16 PM PDT 24
Peak memory 274708 kb
Host smart-69825675-d468-487b-b837-5ed0e40bb912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418237834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1418237834
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2826192201
Short name T528
Test name
Test status
Simulation time 2447903176 ps
CPU time 13.46 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:28 PM PDT 24
Peak memory 217448 kb
Host smart-45cd2805-df26-4bba-bffb-365dcc6809a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826192201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2826192201
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2647950830
Short name T348
Test name
Test status
Simulation time 25549093378 ps
CPU time 13.06 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:33:28 PM PDT 24
Peak memory 217416 kb
Host smart-4772635c-8485-4249-9c27-3ce7ce58b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647950830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2647950830
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.471171390
Short name T864
Test name
Test status
Simulation time 253764414 ps
CPU time 2.44 seconds
Started Jul 11 04:32:49 PM PDT 24
Finished Jul 11 04:33:17 PM PDT 24
Peak memory 217356 kb
Host smart-aa12535c-1b78-4645-b720-e0fbe7549af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471171390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.471171390
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2410446084
Short name T26
Test name
Test status
Simulation time 15517535 ps
CPU time 0.77 seconds
Started Jul 11 04:32:48 PM PDT 24
Finished Jul 11 04:33:14 PM PDT 24
Peak memory 206848 kb
Host smart-96f417a9-067e-4e13-a7a4-54b610b7233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410446084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2410446084
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3316523366
Short name T777
Test name
Test status
Simulation time 43243966 ps
CPU time 2.38 seconds
Started Jul 11 04:32:59 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 225184 kb
Host smart-03a08e70-5791-4adc-9ae6-869ef24e4a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316523366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3316523366
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4051161225
Short name T459
Test name
Test status
Simulation time 13522772 ps
CPU time 0.71 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 205700 kb
Host smart-4965c7ea-35c3-4b1d-afeb-dcc967746328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051161225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4051161225
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.215333317
Short name T979
Test name
Test status
Simulation time 33829086 ps
CPU time 2.32 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:41 PM PDT 24
Peak memory 233488 kb
Host smart-5f217200-cf4e-456f-897e-c692e084ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215333317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.215333317
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1337952235
Short name T849
Test name
Test status
Simulation time 25864688 ps
CPU time 0.73 seconds
Started Jul 11 04:33:02 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 207732 kb
Host smart-461ec780-d1ee-4db3-a9cc-0d224ad6f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337952235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1337952235
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1395950373
Short name T7
Test name
Test status
Simulation time 29119830609 ps
CPU time 204.29 seconds
Started Jul 11 04:32:56 PM PDT 24
Finished Jul 11 04:36:43 PM PDT 24
Peak memory 259488 kb
Host smart-6461e192-3b50-4f76-842e-f26a8a1494f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395950373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1395950373
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1838537744
Short name T165
Test name
Test status
Simulation time 6074585398 ps
CPU time 39.07 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:34:11 PM PDT 24
Peak memory 250152 kb
Host smart-5ccc5258-58e5-40d1-9a74-b9e55145f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838537744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1838537744
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.874696679
Short name T546
Test name
Test status
Simulation time 29981572383 ps
CPU time 220.55 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:37:05 PM PDT 24
Peak memory 239468 kb
Host smart-36de2f6b-b154-412a-8ded-166e2ffe9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874696679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.874696679
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1030129165
Short name T287
Test name
Test status
Simulation time 297904015 ps
CPU time 5.12 seconds
Started Jul 11 04:32:52 PM PDT 24
Finished Jul 11 04:33:21 PM PDT 24
Peak memory 238188 kb
Host smart-30868860-45a8-4bda-8879-7210f64af69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030129165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1030129165
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.64220072
Short name T210
Test name
Test status
Simulation time 39380148025 ps
CPU time 183.33 seconds
Started Jul 11 04:32:51 PM PDT 24
Finished Jul 11 04:36:18 PM PDT 24
Peak memory 263016 kb
Host smart-7c6fe7d0-5772-4a75-8f28-8bc634af2fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64220072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.64220072
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.956180237
Short name T824
Test name
Test status
Simulation time 104593271 ps
CPU time 2 seconds
Started Jul 11 04:33:03 PM PDT 24
Finished Jul 11 04:33:26 PM PDT 24
Peak memory 225452 kb
Host smart-8dad4da2-45da-4125-9bc8-0511bbaaa93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956180237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.956180237
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.102274166
Short name T1021
Test name
Test status
Simulation time 95778447 ps
CPU time 2.1 seconds
Started Jul 11 04:32:53 PM PDT 24
Finished Jul 11 04:33:19 PM PDT 24
Peak memory 224804 kb
Host smart-8706d41b-3618-4e28-b89e-d2b2edf0fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102274166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.102274166
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4274682389
Short name T822
Test name
Test status
Simulation time 4806846787 ps
CPU time 16.54 seconds
Started Jul 11 04:32:56 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 241572 kb
Host smart-9f05f87f-31f0-4d5f-bc92-81c89f102127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274682389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4274682389
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1464444666
Short name T569
Test name
Test status
Simulation time 6116697874 ps
CPU time 13.92 seconds
Started Jul 11 04:32:54 PM PDT 24
Finished Jul 11 04:33:32 PM PDT 24
Peak memory 225588 kb
Host smart-b252936b-5697-430c-a64a-9f23a567704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464444666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1464444666
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.584816552
Short name T508
Test name
Test status
Simulation time 77525947 ps
CPU time 3.43 seconds
Started Jul 11 04:33:00 PM PDT 24
Finished Jul 11 04:33:24 PM PDT 24
Peak memory 222936 kb
Host smart-05d69d3f-e48a-421c-9293-59d10cf8b669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=584816552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.584816552
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2707846726
Short name T732
Test name
Test status
Simulation time 53001252105 ps
CPU time 476.48 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:41:19 PM PDT 24
Peak memory 264436 kb
Host smart-c6868372-66bd-4ed6-8fff-7e784afe0a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707846726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2707846726
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4111825
Short name T903
Test name
Test status
Simulation time 1705095941 ps
CPU time 15.19 seconds
Started Jul 11 04:32:55 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 217316 kb
Host smart-04872e5b-1c9c-4984-9fd1-ee4fb68dfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4111825
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1276845443
Short name T386
Test name
Test status
Simulation time 728851367 ps
CPU time 5.04 seconds
Started Jul 11 04:32:59 PM PDT 24
Finished Jul 11 04:33:26 PM PDT 24
Peak memory 217224 kb
Host smart-e83a4e15-2196-48ca-927c-b6f844f98e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276845443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1276845443
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2975096159
Short name T607
Test name
Test status
Simulation time 72850905 ps
CPU time 1.28 seconds
Started Jul 11 04:32:57 PM PDT 24
Finished Jul 11 04:33:20 PM PDT 24
Peak memory 217308 kb
Host smart-11a534e3-7377-474e-b351-ceb399cdaee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975096159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2975096159
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3747707200
Short name T376
Test name
Test status
Simulation time 97857813 ps
CPU time 0.87 seconds
Started Jul 11 04:32:59 PM PDT 24
Finished Jul 11 04:33:22 PM PDT 24
Peak memory 206848 kb
Host smart-dfc85761-99fe-4ecd-a6d1-6377513efd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747707200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3747707200
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2256092092
Short name T913
Test name
Test status
Simulation time 181098821 ps
CPU time 2.39 seconds
Started Jul 11 04:32:59 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 225504 kb
Host smart-c65b1a8c-6f09-44a9-a987-aee9dd3000f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256092092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2256092092
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.168680647
Short name T761
Test name
Test status
Simulation time 30422725 ps
CPU time 0.74 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:33:25 PM PDT 24
Peak memory 206348 kb
Host smart-fcd5792d-60a8-4b3a-9b1d-9fee223aadd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168680647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.168680647
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2669329647
Short name T612
Test name
Test status
Simulation time 959435126 ps
CPU time 3.77 seconds
Started Jul 11 04:32:59 PM PDT 24
Finished Jul 11 04:33:24 PM PDT 24
Peak memory 225352 kb
Host smart-97916ac9-d4ed-4b02-94c2-7186031378ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669329647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2669329647
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3094169407
Short name T640
Test name
Test status
Simulation time 49457721 ps
CPU time 0.79 seconds
Started Jul 11 04:33:05 PM PDT 24
Finished Jul 11 04:33:27 PM PDT 24
Peak memory 207472 kb
Host smart-7a39fafb-7a24-42e9-b945-6413b13892d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094169407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3094169407
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3568993791
Short name T872
Test name
Test status
Simulation time 1410078308 ps
CPU time 29.91 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 250056 kb
Host smart-f4cf2f7f-df1f-4aae-9072-7e0967882ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568993791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3568993791
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3593983451
Short name T527
Test name
Test status
Simulation time 3885747136 ps
CPU time 10.64 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 225624 kb
Host smart-cafbe83d-707b-4180-8915-5a28594dcad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593983451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3593983451
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3937534955
Short name T899
Test name
Test status
Simulation time 143306133993 ps
CPU time 235.48 seconds
Started Jul 11 04:33:00 PM PDT 24
Finished Jul 11 04:37:18 PM PDT 24
Peak memory 250164 kb
Host smart-6102fb0d-b383-439e-b39d-894ff1571eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937534955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3937534955
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.211291527
Short name T270
Test name
Test status
Simulation time 987337374 ps
CPU time 3.29 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 233708 kb
Host smart-2ad279da-cc74-4ea6-9714-c53468d35d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211291527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.211291527
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.487115874
Short name T504
Test name
Test status
Simulation time 31406024428 ps
CPU time 46.75 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 241660 kb
Host smart-5b456bac-ef2b-4f0a-888b-41bf6487d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487115874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.487115874
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4255679685
Short name T363
Test name
Test status
Simulation time 8349115828 ps
CPU time 10.95 seconds
Started Jul 11 04:33:03 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 233688 kb
Host smart-c7cbdb12-8e10-40b1-8baf-f37cd44ffed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255679685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4255679685
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3815851951
Short name T585
Test name
Test status
Simulation time 6961745477 ps
CPU time 16.41 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 225600 kb
Host smart-6e41f916-7802-4e43-ad06-5613497d00cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815851951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3815851951
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1990871517
Short name T561
Test name
Test status
Simulation time 5775383527 ps
CPU time 10.54 seconds
Started Jul 11 04:33:09 PM PDT 24
Finished Jul 11 04:33:40 PM PDT 24
Peak memory 221472 kb
Host smart-009dd397-3524-48b2-963e-cb39011e71d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990871517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1990871517
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.784583304
Short name T1003
Test name
Test status
Simulation time 49860574 ps
CPU time 1.01 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 207768 kb
Host smart-e88244a6-ef7e-44da-afe8-827ba6c2941d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784583304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.784583304
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3560390817
Short name T32
Test name
Test status
Simulation time 356460307 ps
CPU time 2.26 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:33:25 PM PDT 24
Peak memory 219416 kb
Host smart-792b7a33-40c8-48bc-900c-1c18558d7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560390817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3560390817
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3050173724
Short name T324
Test name
Test status
Simulation time 3428573872 ps
CPU time 8.26 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 217472 kb
Host smart-e06d5a7f-7d23-40e9-9860-f564393fa023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050173724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3050173724
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.514741829
Short name T670
Test name
Test status
Simulation time 44547207 ps
CPU time 1.18 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 217128 kb
Host smart-2946a099-411f-448a-a186-16d1a80eb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514741829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.514741829
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.29968242
Short name T487
Test name
Test status
Simulation time 167102093 ps
CPU time 0.85 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 206944 kb
Host smart-05307f82-7a24-477f-af4a-9762599feac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29968242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.29968242
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.277322850
Short name T344
Test name
Test status
Simulation time 1057847228 ps
CPU time 7.8 seconds
Started Jul 11 04:33:06 PM PDT 24
Finished Jul 11 04:33:34 PM PDT 24
Peak memory 233524 kb
Host smart-506a3085-ea79-4e18-8b53-8ec67b2be817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277322850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.277322850
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1925397896
Short name T953
Test name
Test status
Simulation time 11885452 ps
CPU time 0.7 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 206600 kb
Host smart-b2f43bb2-1032-4995-a688-0b9069129f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925397896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1925397896
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3707280832
Short name T161
Test name
Test status
Simulation time 424398307 ps
CPU time 3.24 seconds
Started Jul 11 04:33:06 PM PDT 24
Finished Jul 11 04:33:30 PM PDT 24
Peak memory 233676 kb
Host smart-d993838c-be04-4169-9d34-0163d2ffb7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707280832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3707280832
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2967531870
Short name T446
Test name
Test status
Simulation time 83855942 ps
CPU time 0.87 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:33:23 PM PDT 24
Peak memory 207444 kb
Host smart-1f69c125-9f4a-4434-87c2-7279ebf0f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967531870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2967531870
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1858723198
Short name T831
Test name
Test status
Simulation time 6103192587 ps
CPU time 42.72 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:34:08 PM PDT 24
Peak memory 242000 kb
Host smart-0328a601-2cce-4b34-b022-4dc9ed291f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858723198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1858723198
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.985787501
Short name T444
Test name
Test status
Simulation time 15906508445 ps
CPU time 85.55 seconds
Started Jul 11 04:33:05 PM PDT 24
Finished Jul 11 04:34:51 PM PDT 24
Peak memory 258444 kb
Host smart-ed7ce742-0b1c-4f90-bc85-bd504114a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985787501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.985787501
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1386298986
Short name T293
Test name
Test status
Simulation time 5293271943 ps
CPU time 23.23 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:55 PM PDT 24
Peak memory 218644 kb
Host smart-d80d8a9b-e456-44c3-aacf-4ad29d029478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386298986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1386298986
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3883144246
Short name T284
Test name
Test status
Simulation time 602749791 ps
CPU time 6.87 seconds
Started Jul 11 04:33:01 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 225560 kb
Host smart-18046ee3-82c5-4498-b617-8153671753e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883144246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3883144246
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.63018511
Short name T223
Test name
Test status
Simulation time 9854235092 ps
CPU time 130.46 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:35:36 PM PDT 24
Peak memory 266620 kb
Host smart-4c44b65f-4190-4a77-b67d-cb9db8d1dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63018511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.63018511
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3642199939
Short name T451
Test name
Test status
Simulation time 1868468206 ps
CPU time 14.05 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 225472 kb
Host smart-88439574-b8d7-4a8f-80ae-41731c845e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642199939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3642199939
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3843520102
Short name T199
Test name
Test status
Simulation time 6052436200 ps
CPU time 23.44 seconds
Started Jul 11 04:33:00 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 241716 kb
Host smart-4677d5a8-6035-4026-8892-46f259445974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843520102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3843520102
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3597516365
Short name T1006
Test name
Test status
Simulation time 769666702 ps
CPU time 7.18 seconds
Started Jul 11 04:33:05 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 240684 kb
Host smart-14d331b6-ced3-4e54-b212-5c28c7584411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597516365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3597516365
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3908624596
Short name T266
Test name
Test status
Simulation time 1263692517 ps
CPU time 6.2 seconds
Started Jul 11 04:33:04 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 225528 kb
Host smart-6bca7429-835b-4945-a328-badb68f9ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908624596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3908624596
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1480137032
Short name T841
Test name
Test status
Simulation time 139072016 ps
CPU time 5.1 seconds
Started Jul 11 04:33:05 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 224020 kb
Host smart-7fbe70b8-ac3c-4b83-aa0a-c7411c91bde9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1480137032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1480137032
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3674065322
Short name T596
Test name
Test status
Simulation time 315427837 ps
CPU time 1 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 207936 kb
Host smart-0fb6e919-d143-4722-9f71-c26d598686cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674065322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3674065322
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2560079505
Short name T445
Test name
Test status
Simulation time 923743581 ps
CPU time 3.53 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 219932 kb
Host smart-5ec7954f-4aef-4b2d-897f-6b71aa279c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560079505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2560079505
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2954841129
Short name T954
Test name
Test status
Simulation time 1202452390 ps
CPU time 4.93 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 217312 kb
Host smart-fe078809-fe89-4e4a-85c2-64ddc642dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954841129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2954841129
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1056862352
Short name T563
Test name
Test status
Simulation time 61888130 ps
CPU time 0.77 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 206764 kb
Host smart-5f6c8d16-49cd-4ab9-baca-d318fe1a25e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056862352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1056862352
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4095206907
Short name T978
Test name
Test status
Simulation time 120009140 ps
CPU time 0.86 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 206860 kb
Host smart-73c3e685-9911-4b7b-bbba-680f7a4326ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095206907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4095206907
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1085748539
Short name T253
Test name
Test status
Simulation time 1334803538 ps
CPU time 6.26 seconds
Started Jul 11 04:33:02 PM PDT 24
Finished Jul 11 04:33:29 PM PDT 24
Peak memory 233652 kb
Host smart-b1eb58e9-753f-4595-a2a4-a5f968c306b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085748539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1085748539
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.696098789
Short name T464
Test name
Test status
Simulation time 11315633 ps
CPU time 0.72 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 205760 kb
Host smart-480e2224-3007-4f2e-a3eb-31f3aeee30d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696098789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.696098789
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1010036999
Short name T379
Test name
Test status
Simulation time 127971024 ps
CPU time 2.33 seconds
Started Jul 11 04:33:13 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 225440 kb
Host smart-d859f0ab-4346-4584-9c35-073196faf34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010036999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1010036999
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1636224216
Short name T492
Test name
Test status
Simulation time 27562835 ps
CPU time 0.72 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 206408 kb
Host smart-b817f39b-a552-4ecc-b785-2369b142f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636224216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1636224216
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3978627288
Short name T614
Test name
Test status
Simulation time 3989567514 ps
CPU time 39.18 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:34:11 PM PDT 24
Peak memory 250160 kb
Host smart-3f34b54b-6e27-4afd-83db-6a8d456008e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978627288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3978627288
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3919761834
Short name T357
Test name
Test status
Simulation time 23914314415 ps
CPU time 216.64 seconds
Started Jul 11 04:33:13 PM PDT 24
Finished Jul 11 04:37:10 PM PDT 24
Peak memory 250268 kb
Host smart-08331e60-77b8-4e53-8251-b53e70e65dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919761834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3919761834
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2735200551
Short name T135
Test name
Test status
Simulation time 5380202341 ps
CPU time 48.11 seconds
Started Jul 11 04:33:20 PM PDT 24
Finished Jul 11 04:34:28 PM PDT 24
Peak memory 225792 kb
Host smart-55d38eb3-f4f3-42af-81a2-7f542fe080c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735200551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2735200551
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.95123643
Short name T380
Test name
Test status
Simulation time 83451533 ps
CPU time 3.62 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:36 PM PDT 24
Peak memory 219832 kb
Host smart-5d0cae1b-bb8a-4ec7-a45f-5e44dbd41a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95123643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.95123643
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4288838019
Short name T665
Test name
Test status
Simulation time 12797001388 ps
CPU time 69.67 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 252392 kb
Host smart-b0000c6a-de38-40c3-ae0e-e764a0e4e679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288838019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4288838019
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2752154278
Short name T666
Test name
Test status
Simulation time 190155878 ps
CPU time 2.69 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 233680 kb
Host smart-d9c83544-a99a-468b-b6a9-0f3927049d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752154278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2752154278
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1543902935
Short name T387
Test name
Test status
Simulation time 3486342374 ps
CPU time 13.92 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 233824 kb
Host smart-abf4b7b1-024e-4ff9-af1d-115186449c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543902935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1543902935
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2709103853
Short name T396
Test name
Test status
Simulation time 3427467790 ps
CPU time 9.68 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 225508 kb
Host smart-35209af1-4e6c-4792-b4c3-f82abedb9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709103853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2709103853
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3665049055
Short name T331
Test name
Test status
Simulation time 9937637604 ps
CPU time 6.2 seconds
Started Jul 11 04:33:09 PM PDT 24
Finished Jul 11 04:33:34 PM PDT 24
Peak memory 234068 kb
Host smart-59efe5c1-49bf-43f5-b76d-c8c0baf04d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665049055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3665049055
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.120804337
Short name T675
Test name
Test status
Simulation time 71936302 ps
CPU time 3.39 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 219656 kb
Host smart-6488a86d-2592-4f9f-bf22-8046e3ffcc66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120804337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.120804337
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.901483305
Short name T499
Test name
Test status
Simulation time 3732341678 ps
CPU time 28.08 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:34:10 PM PDT 24
Peak memory 225756 kb
Host smart-12a69a1a-50b0-4ac9-b259-b39242225c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901483305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.901483305
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1550055264
Short name T690
Test name
Test status
Simulation time 27726173601 ps
CPU time 35.52 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:34:10 PM PDT 24
Peak memory 217348 kb
Host smart-0a548f13-35f4-4357-a142-63da71c43eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550055264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1550055264
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2467476250
Short name T588
Test name
Test status
Simulation time 3731021502 ps
CPU time 8.31 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 217432 kb
Host smart-cfdcee58-6778-4614-be84-8310be74e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467476250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2467476250
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1882619546
Short name T932
Test name
Test status
Simulation time 163020004 ps
CPU time 1.57 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:32 PM PDT 24
Peak memory 217248 kb
Host smart-e8d39bcb-be8e-4a88-bcfd-3e8f597136dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882619546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1882619546
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4103837991
Short name T898
Test name
Test status
Simulation time 267400801 ps
CPU time 0.94 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 207252 kb
Host smart-4cb5998a-eef9-40dd-99ee-a1ac80def7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103837991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4103837991
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3043642092
Short name T896
Test name
Test status
Simulation time 1028788151 ps
CPU time 4.26 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 233704 kb
Host smart-42f751c8-3542-46f7-9755-af53700b1b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043642092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3043642092
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1904755694
Short name T361
Test name
Test status
Simulation time 51348872 ps
CPU time 0.72 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:40 PM PDT 24
Peak memory 206168 kb
Host smart-1095ca5d-1b5d-4cbf-b283-39fdb2df5411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904755694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1904755694
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2965410680
Short name T575
Test name
Test status
Simulation time 97867574 ps
CPU time 3.59 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:55 PM PDT 24
Peak memory 233660 kb
Host smart-4c8359d5-8e7d-4a92-8d96-2e2a0e70d698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965410680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2965410680
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1102813534
Short name T355
Test name
Test status
Simulation time 19964332 ps
CPU time 0.78 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 207720 kb
Host smart-41e36032-80ff-4ee8-b6a0-9bd16c969aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102813534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1102813534
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3147823176
Short name T708
Test name
Test status
Simulation time 22836605887 ps
CPU time 97.1 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:35:09 PM PDT 24
Peak memory 250376 kb
Host smart-bc4922c3-a970-4781-af8f-20bc2f7c90fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147823176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3147823176
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2985729835
Short name T767
Test name
Test status
Simulation time 10916788250 ps
CPU time 59.33 seconds
Started Jul 11 04:33:20 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 233876 kb
Host smart-e26bbcf6-31a8-4e08-9113-630ae75aec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985729835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2985729835
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.478241564
Short name T413
Test name
Test status
Simulation time 264126704227 ps
CPU time 349.73 seconds
Started Jul 11 04:33:20 PM PDT 24
Finished Jul 11 04:39:30 PM PDT 24
Peak memory 255008 kb
Host smart-33d15df5-cd5e-4715-bd2d-60367b76559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478241564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.478241564
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2503205589
Short name T146
Test name
Test status
Simulation time 195533612 ps
CPU time 9.43 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:41 PM PDT 24
Peak memory 241852 kb
Host smart-02ff8fd8-7acb-46fe-be2e-7b41d3f7644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503205589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2503205589
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3418486988
Short name T40
Test name
Test status
Simulation time 9742837470 ps
CPU time 99.93 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:35:32 PM PDT 24
Peak memory 258356 kb
Host smart-8c1c91e7-e94a-4953-b53e-13daee0ca9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418486988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3418486988
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1427666619
Short name T852
Test name
Test status
Simulation time 6155617837 ps
CPU time 30.19 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:34:10 PM PDT 24
Peak memory 233748 kb
Host smart-7f875fd9-eeab-4544-8f1b-4d182aeb73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427666619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1427666619
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.594697590
Short name T637
Test name
Test status
Simulation time 1072429149 ps
CPU time 2.1 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:33:36 PM PDT 24
Peak memory 224092 kb
Host smart-e324dd3c-a43e-467e-aa92-3d186847c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594697590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.594697590
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2824892213
Short name T938
Test name
Test status
Simulation time 2689588304 ps
CPU time 9.26 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:01 PM PDT 24
Peak memory 233404 kb
Host smart-caa39d37-ebdf-418d-85f7-723a90d7863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824892213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2824892213
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3325316727
Short name T318
Test name
Test status
Simulation time 534791971 ps
CPU time 3.25 seconds
Started Jul 11 04:33:09 PM PDT 24
Finished Jul 11 04:33:31 PM PDT 24
Peak memory 225520 kb
Host smart-3d6680c4-082f-4052-98ff-610200d6b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325316727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3325316727
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3997939432
Short name T752
Test name
Test status
Simulation time 160609127 ps
CPU time 3.58 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 221232 kb
Host smart-f0a98236-1c9f-46d7-8b34-ee4f7f406b39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3997939432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3997939432
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.239396242
Short name T407
Test name
Test status
Simulation time 2457886384 ps
CPU time 10.79 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:50 PM PDT 24
Peak memory 217272 kb
Host smart-12942a53-ec58-4dbf-ba65-a26587012d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239396242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.239396242
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2203636279
Short name T469
Test name
Test status
Simulation time 1243704490 ps
CPU time 4.65 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:36 PM PDT 24
Peak memory 217300 kb
Host smart-2969d296-ef41-4318-986b-c3e4e8ea23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203636279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2203636279
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.824443150
Short name T491
Test name
Test status
Simulation time 13789549 ps
CPU time 0.7 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 206508 kb
Host smart-94954fdd-5e64-4194-931f-180f518d8851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824443150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.824443150
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3973149600
Short name T727
Test name
Test status
Simulation time 63540794 ps
CPU time 0.81 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 206584 kb
Host smart-86402453-6cf1-4229-a2d1-c6e64183b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973149600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3973149600
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.350360701
Short name T856
Test name
Test status
Simulation time 3005772728 ps
CPU time 11.34 seconds
Started Jul 11 04:33:10 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 233828 kb
Host smart-2f0a6ca1-87f1-4361-9367-c4b9a0f16b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350360701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.350360701
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.395426361
Short name T532
Test name
Test status
Simulation time 11625794 ps
CPU time 0.72 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 206836 kb
Host smart-d99ef40d-072c-405e-af27-7047430aaab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395426361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.395426361
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3311226547
Short name T694
Test name
Test status
Simulation time 701412660 ps
CPU time 5.07 seconds
Started Jul 11 04:31:25 PM PDT 24
Finished Jul 11 04:31:49 PM PDT 24
Peak memory 225452 kb
Host smart-733a9d1b-36c3-4967-87c5-3d192b80a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311226547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3311226547
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3162882661
Short name T866
Test name
Test status
Simulation time 13404896 ps
CPU time 0.77 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:13 PM PDT 24
Peak memory 207376 kb
Host smart-eea12a54-4a08-4ac7-baa6-4bc8ec0ce0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162882661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3162882661
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.16441522
Short name T840
Test name
Test status
Simulation time 5255665791 ps
CPU time 28.81 seconds
Started Jul 11 04:31:33 PM PDT 24
Finished Jul 11 04:32:20 PM PDT 24
Peak memory 250328 kb
Host smart-c35b274a-9fd6-4e13-a396-43c3f73cf1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16441522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.16441522
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1441490574
Short name T754
Test name
Test status
Simulation time 4043384012 ps
CPU time 47.11 seconds
Started Jul 11 04:31:41 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 250232 kb
Host smart-031d566f-5351-45f9-8be3-4d8794b4e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441490574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1441490574
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1746142289
Short name T803
Test name
Test status
Simulation time 87503911632 ps
CPU time 107.24 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 257652 kb
Host smart-e22260e7-89e0-4105-8233-0e014d80f018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746142289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1746142289
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.584102791
Short name T940
Test name
Test status
Simulation time 1898476799 ps
CPU time 10.78 seconds
Started Jul 11 04:31:53 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 233580 kb
Host smart-2b186e9e-3d32-4ab0-bcf5-69260d90a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584102791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.584102791
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2731262895
Short name T91
Test name
Test status
Simulation time 7668202794 ps
CPU time 46.32 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:33:08 PM PDT 24
Peak memory 251356 kb
Host smart-0ea8dd67-6677-4d00-b5da-bd667ea81556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731262895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2731262895
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.977651103
Short name T388
Test name
Test status
Simulation time 140815558 ps
CPU time 2.47 seconds
Started Jul 11 04:31:39 PM PDT 24
Finished Jul 11 04:32:00 PM PDT 24
Peak memory 227832 kb
Host smart-2506c913-7ded-41a4-9121-a5229f95201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977651103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.977651103
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.805089333
Short name T914
Test name
Test status
Simulation time 8273774978 ps
CPU time 40.56 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:32:45 PM PDT 24
Peak memory 242084 kb
Host smart-0519da52-543d-4a40-8707-fba930f33b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805089333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.805089333
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2785542455
Short name T696
Test name
Test status
Simulation time 33424753 ps
CPU time 1.13 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:09 PM PDT 24
Peak memory 217588 kb
Host smart-fd5745de-b519-4b20-8159-de9a4ab22b1e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785542455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2785542455
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4163024970
Short name T741
Test name
Test status
Simulation time 489733033 ps
CPU time 6.25 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 233624 kb
Host smart-487a517d-7357-44ad-bd08-ac0348cfa5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163024970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4163024970
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3650750201
Short name T622
Test name
Test status
Simulation time 363745525 ps
CPU time 3.12 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:19 PM PDT 24
Peak memory 233636 kb
Host smart-074a9c18-04d1-4fd7-a61f-5b90fb571b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650750201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3650750201
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3638014806
Short name T606
Test name
Test status
Simulation time 545444418 ps
CPU time 4.17 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:30 PM PDT 24
Peak memory 224140 kb
Host smart-f8d11e55-5060-4ede-a4da-51e56748c7e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638014806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3638014806
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4242818909
Short name T66
Test name
Test status
Simulation time 81186811 ps
CPU time 1.14 seconds
Started Jul 11 04:31:31 PM PDT 24
Finished Jul 11 04:31:51 PM PDT 24
Peak memory 236212 kb
Host smart-bbeb53de-85e0-41a6-82d5-c28e7d3251f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242818909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4242818909
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4190084100
Short name T138
Test name
Test status
Simulation time 266879762246 ps
CPU time 544.79 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:41:36 PM PDT 24
Peak memory 270540 kb
Host smart-d9df8db8-c152-4802-a276-77bb19c3c475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190084100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4190084100
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2506455568
Short name T321
Test name
Test status
Simulation time 2812249798 ps
CPU time 8.09 seconds
Started Jul 11 04:31:31 PM PDT 24
Finished Jul 11 04:31:58 PM PDT 24
Peak memory 217520 kb
Host smart-e3a6691a-9ed1-4ed1-91e3-42a5f1661d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506455568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2506455568
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3629912498
Short name T507
Test name
Test status
Simulation time 123789377 ps
CPU time 1.28 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 208852 kb
Host smart-74f4e33d-ce81-428c-b4b4-e2e31018e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629912498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3629912498
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2259155855
Short name T481
Test name
Test status
Simulation time 134703585 ps
CPU time 5.73 seconds
Started Jul 11 04:31:40 PM PDT 24
Finished Jul 11 04:32:04 PM PDT 24
Peak memory 217336 kb
Host smart-b8f2d4d4-08f5-4c82-837d-809df0bd6da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259155855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2259155855
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.787647571
Short name T1015
Test name
Test status
Simulation time 38526129 ps
CPU time 0.78 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:32:05 PM PDT 24
Peak memory 206848 kb
Host smart-c043510c-faea-4f6a-b2f2-b6b33a04df08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787647571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.787647571
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2171629600
Short name T782
Test name
Test status
Simulation time 149077333 ps
CPU time 2.71 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:31:58 PM PDT 24
Peak memory 225444 kb
Host smart-2c1214d6-c9f6-453b-b5e4-9538f99f5bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171629600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2171629600
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3773758904
Short name T454
Test name
Test status
Simulation time 173750761 ps
CPU time 0.72 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 206600 kb
Host smart-8c739465-e180-479c-8c8b-1ca4fb372abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773758904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3773758904
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3908252104
Short name T346
Test name
Test status
Simulation time 440595033 ps
CPU time 7.41 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 225524 kb
Host smart-f4d700a9-57f4-4837-814e-a6d25b317cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908252104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3908252104
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2537361207
Short name T931
Test name
Test status
Simulation time 34321892 ps
CPU time 0.74 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 207760 kb
Host smart-a1eb1f51-d3a8-414f-9bce-602bfa910c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537361207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2537361207
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2508682224
Short name T204
Test name
Test status
Simulation time 87409103926 ps
CPU time 217.72 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:37:14 PM PDT 24
Peak memory 263340 kb
Host smart-960bd44a-673f-420a-b0c4-855a501cbc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508682224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2508682224
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.271747899
Short name T904
Test name
Test status
Simulation time 1913595559 ps
CPU time 30.8 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:34:09 PM PDT 24
Peak memory 242064 kb
Host smart-f982e99b-e6b8-4733-acda-80fc64f12cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271747899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.271747899
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.528434214
Short name T629
Test name
Test status
Simulation time 2025279573 ps
CPU time 12.52 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:33:44 PM PDT 24
Peak memory 225480 kb
Host smart-6722c627-3525-4bd1-86d1-d5a762958eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528434214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.528434214
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1967623934
Short name T963
Test name
Test status
Simulation time 8658836640 ps
CPU time 55.18 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 250184 kb
Host smart-d4b6a762-3576-4159-abcc-bf29d2e2fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967623934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1967623934
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3772247499
Short name T354
Test name
Test status
Simulation time 329969121 ps
CPU time 5.6 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 233740 kb
Host smart-289d7ae4-9ed1-4b62-9dad-497a9c547a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772247499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3772247499
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2587079571
Short name T473
Test name
Test status
Simulation time 52241838518 ps
CPU time 107.72 seconds
Started Jul 11 04:33:11 PM PDT 24
Finished Jul 11 04:35:19 PM PDT 24
Peak memory 250588 kb
Host smart-a3dc868d-0a16-4157-b187-44e301cdf2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587079571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2587079571
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.370708430
Short name T635
Test name
Test status
Simulation time 3318925555 ps
CPU time 11.32 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 233760 kb
Host smart-46ee6f31-b076-4c30-b2e2-e540242b7334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370708430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.370708430
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1644901877
Short name T743
Test name
Test status
Simulation time 7915248996 ps
CPU time 8.5 seconds
Started Jul 11 04:33:08 PM PDT 24
Finished Jul 11 04:33:36 PM PDT 24
Peak memory 233800 kb
Host smart-51fdad93-e732-4f53-9c7d-c03529c4cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644901877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1644901877
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3824150603
Short name T660
Test name
Test status
Simulation time 469089806 ps
CPU time 3.9 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:33:40 PM PDT 24
Peak memory 220664 kb
Host smart-297cc358-7338-4050-bd09-3b9d658cd2cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824150603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3824150603
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3599249253
Short name T298
Test name
Test status
Simulation time 5225736965 ps
CPU time 7.61 seconds
Started Jul 11 04:33:07 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 217364 kb
Host smart-01f5fc5e-599b-4d20-81fc-40db321ced1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599249253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3599249253
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3210550676
Short name T863
Test name
Test status
Simulation time 400896848 ps
CPU time 1.26 seconds
Started Jul 11 04:33:12 PM PDT 24
Finished Jul 11 04:33:33 PM PDT 24
Peak memory 208660 kb
Host smart-e024cf1e-a610-4d64-8cf0-04e1cdd05b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210550676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3210550676
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3526417904
Short name T681
Test name
Test status
Simulation time 73487801 ps
CPU time 1.52 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:53 PM PDT 24
Peak memory 217292 kb
Host smart-5eda6f46-0bb4-4076-a2f9-46e4f4f85664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526417904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3526417904
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.738731721
Short name T707
Test name
Test status
Simulation time 196458120 ps
CPU time 0.73 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 206896 kb
Host smart-f9fda93a-cec0-45fa-a594-68fe26aa25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738731721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.738731721
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3022683956
Short name T360
Test name
Test status
Simulation time 22807888042 ps
CPU time 18.28 seconds
Started Jul 11 04:33:20 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 233844 kb
Host smart-856f6b36-d754-454d-a6e3-ec7a1be4b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022683956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3022683956
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4244337538
Short name T793
Test name
Test status
Simulation time 12681477 ps
CPU time 0.75 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 205788 kb
Host smart-33abe3b3-ffcd-4ff9-bdc1-25cd5d407963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244337538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4244337538
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4266851522
Short name T771
Test name
Test status
Simulation time 111488490 ps
CPU time 3.49 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:53 PM PDT 24
Peak memory 233580 kb
Host smart-f80f892e-0287-4f39-a5f4-d17a230a6e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266851522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4266851522
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2766468821
Short name T722
Test name
Test status
Simulation time 22415134 ps
CPU time 0.75 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 206708 kb
Host smart-cb4937d6-8eea-4ccc-af60-ac0dc08a028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766468821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2766468821
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2550973962
Short name T218
Test name
Test status
Simulation time 276516322050 ps
CPU time 351.94 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:39:26 PM PDT 24
Peak memory 258400 kb
Host smart-4c966e5e-9c71-4193-862c-b577084ad90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550973962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2550973962
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2783655893
Short name T419
Test name
Test status
Simulation time 27553062769 ps
CPU time 273.22 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:38:15 PM PDT 24
Peak memory 250372 kb
Host smart-8f639425-950a-417e-8e8f-332fe2eb2a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783655893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2783655893
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.947308096
Short name T202
Test name
Test status
Simulation time 21676102724 ps
CPU time 139.88 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 236300 kb
Host smart-bcf736f6-7685-4971-a960-da2c1c72c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947308096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.947308096
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3466247795
Short name T450
Test name
Test status
Simulation time 4106995532 ps
CPU time 7.15 seconds
Started Jul 11 04:33:15 PM PDT 24
Finished Jul 11 04:33:41 PM PDT 24
Peak memory 233708 kb
Host smart-8cbd4b38-72a4-4608-bdba-39646a6d12dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466247795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3466247795
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1048683114
Short name T814
Test name
Test status
Simulation time 3222749920 ps
CPU time 64.5 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 252112 kb
Host smart-76b200ee-f660-4141-adb6-1831251e00f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048683114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1048683114
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4049380204
Short name T394
Test name
Test status
Simulation time 4277073787 ps
CPU time 17.69 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:09 PM PDT 24
Peak memory 225364 kb
Host smart-e1063247-6b4d-4408-991f-c4cc9f95b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049380204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4049380204
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3664348633
Short name T440
Test name
Test status
Simulation time 10423002395 ps
CPU time 50.6 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 233828 kb
Host smart-95cb854d-75bd-45c8-bb17-8c6ae6a6f1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664348633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3664348633
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.917885180
Short name T75
Test name
Test status
Simulation time 41377756413 ps
CPU time 13.82 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:33:57 PM PDT 24
Peak memory 225564 kb
Host smart-1d59d048-42fe-4d75-9da4-ba4aedd36b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917885180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.917885180
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.216362067
Short name T198
Test name
Test status
Simulation time 774424610 ps
CPU time 5.54 seconds
Started Jul 11 04:33:28 PM PDT 24
Finished Jul 11 04:33:55 PM PDT 24
Peak memory 233656 kb
Host smart-77989521-5b11-4907-9a30-c7a82c9ce536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216362067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.216362067
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3535074060
Short name T970
Test name
Test status
Simulation time 301083709 ps
CPU time 5.26 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 223104 kb
Host smart-9e6cad1a-dcc3-476c-a2cf-dcfe48cfa7b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535074060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3535074060
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3916585742
Short name T750
Test name
Test status
Simulation time 126928176539 ps
CPU time 604.02 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:43:44 PM PDT 24
Peak memory 257084 kb
Host smart-78c0c667-5513-4464-8038-8b4acd357a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916585742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3916585742
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.521148531
Short name T27
Test name
Test status
Simulation time 4010938480 ps
CPU time 17.78 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:20 PM PDT 24
Peak memory 217452 kb
Host smart-4e58b3b8-d65f-48ac-8672-1b15df1fc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521148531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.521148531
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3165674867
Short name T955
Test name
Test status
Simulation time 14278610 ps
CPU time 0.68 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:40 PM PDT 24
Peak memory 206576 kb
Host smart-f406b268-5155-45a5-bbf9-c9132074b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165674867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3165674867
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.851425621
Short name T855
Test name
Test status
Simulation time 191851653 ps
CPU time 4.91 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 217260 kb
Host smart-c95ea652-4f63-45ae-aae6-72468a0f7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851425621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.851425621
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.973597243
Short name T476
Test name
Test status
Simulation time 66437631 ps
CPU time 0.85 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 206860 kb
Host smart-a9f2d1db-23e1-4067-aa50-5fdad04b7e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973597243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.973597243
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4011749855
Short name T649
Test name
Test status
Simulation time 855897451 ps
CPU time 8.13 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:33:50 PM PDT 24
Peak memory 233620 kb
Host smart-5333e310-9327-4306-bca1-832a13720803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011749855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4011749855
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.27565322
Short name T391
Test name
Test status
Simulation time 14355513 ps
CPU time 0.73 seconds
Started Jul 11 04:33:25 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 206676 kb
Host smart-537c952a-f5e6-485d-9c8a-2cd0e2b60767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27565322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.27565322
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2353268842
Short name T693
Test name
Test status
Simulation time 844451067 ps
CPU time 7.2 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:09 PM PDT 24
Peak memory 233632 kb
Host smart-25bcc356-11e6-4d92-9c52-96f3e02de341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353268842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2353268842
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3115918037
Short name T951
Test name
Test status
Simulation time 248859886 ps
CPU time 0.77 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 206364 kb
Host smart-2b1310c0-ff2b-4637-b019-d1160f7b4d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115918037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3115918037
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.258882894
Short name T536
Test name
Test status
Simulation time 5744807265 ps
CPU time 47.12 seconds
Started Jul 11 04:33:23 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 239924 kb
Host smart-a3f17940-4d3f-4c8e-8366-304c3bd7c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258882894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.258882894
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.780836792
Short name T24
Test name
Test status
Simulation time 9042073740 ps
CPU time 94.32 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:35:16 PM PDT 24
Peak memory 250300 kb
Host smart-e8000227-1d38-422e-802e-d30670a983c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780836792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.780836792
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2490828658
Short name T895
Test name
Test status
Simulation time 53944021059 ps
CPU time 121.85 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:35:48 PM PDT 24
Peak memory 250456 kb
Host smart-6f11d59d-556f-4791-955e-8638b96e5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490828658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2490828658
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.289606185
Short name T947
Test name
Test status
Simulation time 845846376 ps
CPU time 4.97 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:07 PM PDT 24
Peak memory 225456 kb
Host smart-6f497672-7f66-4a49-993e-027e57a96343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289606185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.289606185
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1134508115
Short name T870
Test name
Test status
Simulation time 1900845633 ps
CPU time 6.51 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:33:45 PM PDT 24
Peak memory 235016 kb
Host smart-26493c84-7b92-477f-81e3-34c541814519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134508115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1134508115
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3725842290
Short name T278
Test name
Test status
Simulation time 361665080 ps
CPU time 2.93 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:39 PM PDT 24
Peak memory 225684 kb
Host smart-a1f774c8-54b0-496b-bfdd-6cdb970cb108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725842290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3725842290
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2907082801
Short name T937
Test name
Test status
Simulation time 3706181414 ps
CPU time 16.18 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:08 PM PDT 24
Peak memory 225436 kb
Host smart-7b26f131-4672-48b8-80d9-bf8a24ed6aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907082801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2907082801
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3590425083
Short name T132
Test name
Test status
Simulation time 1993624037 ps
CPU time 5.06 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:33:47 PM PDT 24
Peak memory 225548 kb
Host smart-70a637ef-0f2d-4c04-a9c9-cdf2fcbcfc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590425083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3590425083
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3035867318
Short name T973
Test name
Test status
Simulation time 548074490 ps
CPU time 3.86 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 225460 kb
Host smart-87a8e8d4-cc35-48d1-b212-a2eb2f2eb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035867318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3035867318
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.198253624
Short name T816
Test name
Test status
Simulation time 802027855 ps
CPU time 10.52 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:49 PM PDT 24
Peak memory 223048 kb
Host smart-c3b46962-2801-4036-afd5-47f19bfee78a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=198253624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.198253624
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2632111222
Short name T168
Test name
Test status
Simulation time 14073878 ps
CPU time 0.72 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 206960 kb
Host smart-5196b81e-d3d1-45a3-9cf4-bd3c3fa4a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632111222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2632111222
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2005554606
Short name T930
Test name
Test status
Simulation time 5076669393 ps
CPU time 3.67 seconds
Started Jul 11 04:33:41 PM PDT 24
Finished Jul 11 04:34:04 PM PDT 24
Peak memory 217360 kb
Host smart-61093387-f5bc-4d2a-ac91-213d09c8e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005554606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2005554606
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.868452676
Short name T305
Test name
Test status
Simulation time 103950373 ps
CPU time 0.68 seconds
Started Jul 11 04:33:16 PM PDT 24
Finished Jul 11 04:33:35 PM PDT 24
Peak memory 206560 kb
Host smart-9dd0bc0d-cec9-4693-99f3-6c8a58fcf355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868452676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.868452676
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.14083314
Short name T948
Test name
Test status
Simulation time 25552115 ps
CPU time 0.77 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 207128 kb
Host smart-fe8d32f5-1d84-45c8-abde-6c0ceb6a94ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14083314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.14083314
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4135468664
Short name T783
Test name
Test status
Simulation time 864492498 ps
CPU time 8.11 seconds
Started Jul 11 04:33:19 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 241736 kb
Host smart-1d466463-cf21-400a-b20f-36b4ac4d7493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135468664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4135468664
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1772063950
Short name T815
Test name
Test status
Simulation time 39067366 ps
CPU time 0.69 seconds
Started Jul 11 04:33:21 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 206692 kb
Host smart-6b17cc79-700f-40ed-9250-aa1cb694166a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772063950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1772063950
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2874860141
Short name T87
Test name
Test status
Simulation time 65478022 ps
CPU time 2.79 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:33:45 PM PDT 24
Peak memory 225716 kb
Host smart-4def07b7-643d-4542-9284-b0df0f6f67b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874860141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2874860141
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.551811444
Short name T892
Test name
Test status
Simulation time 26112354 ps
CPU time 0.77 seconds
Started Jul 11 04:33:23 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 207708 kb
Host smart-5c49db73-3def-47ae-9f90-5af3538d3243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551811444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.551811444
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.340520963
Short name T261
Test name
Test status
Simulation time 66393650135 ps
CPU time 146.83 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:36:13 PM PDT 24
Peak memory 262968 kb
Host smart-3a4da069-589f-43e9-9d9b-018e626e65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340520963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.340520963
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2426366075
Short name T52
Test name
Test status
Simulation time 268092982853 ps
CPU time 348.67 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:39:48 PM PDT 24
Peak memory 255504 kb
Host smart-3391bb22-9ccf-4de3-ad44-d452ae07f1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426366075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2426366075
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1417556653
Short name T299
Test name
Test status
Simulation time 47770414893 ps
CPU time 451.36 seconds
Started Jul 11 04:33:28 PM PDT 24
Finished Jul 11 04:41:20 PM PDT 24
Peak memory 266692 kb
Host smart-0c98c423-dc78-4873-b6b5-c1221782f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417556653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1417556653
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2665860891
Short name T562
Test name
Test status
Simulation time 44480580 ps
CPU time 2.8 seconds
Started Jul 11 04:33:43 PM PDT 24
Finished Jul 11 04:34:07 PM PDT 24
Peak memory 233732 kb
Host smart-efa562bc-7ffb-4547-8cae-aa702a840838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665860891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2665860891
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2716612952
Short name T950
Test name
Test status
Simulation time 1670444756 ps
CPU time 23.5 seconds
Started Jul 11 04:33:27 PM PDT 24
Finished Jul 11 04:34:10 PM PDT 24
Peak memory 238004 kb
Host smart-bd3bcca7-b865-4830-90c0-bbe49fac3b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716612952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2716612952
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1122902053
Short name T714
Test name
Test status
Simulation time 189580207 ps
CPU time 3.72 seconds
Started Jul 11 04:33:23 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 225512 kb
Host smart-ad8cd2d2-9bf0-4044-8d00-cb24133064fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122902053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1122902053
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4109803170
Short name T374
Test name
Test status
Simulation time 634362514 ps
CPU time 3.37 seconds
Started Jul 11 04:33:22 PM PDT 24
Finished Jul 11 04:33:45 PM PDT 24
Peak memory 233596 kb
Host smart-fc63c2d4-a681-475d-9148-29482ec0e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109803170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4109803170
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2648442742
Short name T401
Test name
Test status
Simulation time 33920813 ps
CPU time 2.36 seconds
Started Jul 11 04:33:43 PM PDT 24
Finished Jul 11 04:34:07 PM PDT 24
Peak memory 233440 kb
Host smart-b1e2f8aa-0eed-4e7a-abf2-1890faeed8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648442742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2648442742
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1736278930
Short name T400
Test name
Test status
Simulation time 6532385328 ps
CPU time 18.31 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 225500 kb
Host smart-7056f20a-7224-42ae-b9b5-6ea9b9c16b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736278930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1736278930
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1489863248
Short name T367
Test name
Test status
Simulation time 85692329 ps
CPU time 3.4 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 223692 kb
Host smart-ee0869e4-b93a-45f3-8ef7-c7e48740d0c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1489863248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1489863248
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3013545422
Short name T605
Test name
Test status
Simulation time 3048108187 ps
CPU time 27.58 seconds
Started Jul 11 04:33:18 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 217452 kb
Host smart-9e041cb8-f61a-47d3-90a4-ab58e5a70823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013545422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3013545422
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.826302742
Short name T303
Test name
Test status
Simulation time 741300934 ps
CPU time 3.63 seconds
Started Jul 11 04:34:12 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 217372 kb
Host smart-6748f97f-e42e-460e-8a25-c35ff154d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826302742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.826302742
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2385901476
Short name T358
Test name
Test status
Simulation time 41114280 ps
CPU time 0.71 seconds
Started Jul 11 04:33:17 PM PDT 24
Finished Jul 11 04:33:37 PM PDT 24
Peak memory 206536 kb
Host smart-fab50c84-b0ad-4102-b182-eaa7b23f318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385901476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2385901476
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.97323118
Short name T405
Test name
Test status
Simulation time 124132993 ps
CPU time 0.84 seconds
Started Jul 11 04:33:41 PM PDT 24
Finished Jul 11 04:34:01 PM PDT 24
Peak memory 206796 kb
Host smart-f9f27078-1dd9-47b3-8de6-b6b3ecc3b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97323118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.97323118
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2644968925
Short name T381
Test name
Test status
Simulation time 180506192 ps
CPU time 2 seconds
Started Jul 11 04:33:20 PM PDT 24
Finished Jul 11 04:33:42 PM PDT 24
Peak memory 225056 kb
Host smart-11c21a3c-5219-4598-b14c-f1158835b6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644968925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2644968925
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1952358233
Short name T958
Test name
Test status
Simulation time 47671590 ps
CPU time 0.71 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 206248 kb
Host smart-11d18d26-4945-4216-b546-4a79d5fffa76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952358233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1952358233
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.13638521
Short name T986
Test name
Test status
Simulation time 46078007 ps
CPU time 2.35 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 233764 kb
Host smart-0556bcda-92af-48b6-afa9-12f4d761b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13638521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.13638521
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1812561003
Short name T1016
Test name
Test status
Simulation time 18856644 ps
CPU time 0.84 seconds
Started Jul 11 04:33:45 PM PDT 24
Finished Jul 11 04:34:05 PM PDT 24
Peak memory 207788 kb
Host smart-9ba357ff-5a7a-498e-abaf-8ad2b672d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812561003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1812561003
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1400647625
Short name T196
Test name
Test status
Simulation time 42580885877 ps
CPU time 318.64 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:39:05 PM PDT 24
Peak memory 266600 kb
Host smart-238e6e62-94e9-4fea-a3dd-345e41bba4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400647625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1400647625
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2107959701
Short name T124
Test name
Test status
Simulation time 2306746842 ps
CPU time 43.02 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:34:28 PM PDT 24
Peak memory 239536 kb
Host smart-7f9d24d5-7327-4146-aae3-06d265eed2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107959701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2107959701
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2902290555
Short name T565
Test name
Test status
Simulation time 8147405941 ps
CPU time 38.01 seconds
Started Jul 11 04:33:35 PM PDT 24
Finished Jul 11 04:34:32 PM PDT 24
Peak memory 250132 kb
Host smart-74dd2070-622b-44b1-b1ba-e8fd8589c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902290555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2902290555
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.796250268
Short name T564
Test name
Test status
Simulation time 464237355 ps
CPU time 6.47 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:33:51 PM PDT 24
Peak memory 225448 kb
Host smart-7b6adf89-279c-44af-bd54-f14a3964d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796250268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.796250268
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1163367569
Short name T41
Test name
Test status
Simulation time 52607376379 ps
CPU time 207.51 seconds
Started Jul 11 04:33:27 PM PDT 24
Finished Jul 11 04:37:15 PM PDT 24
Peak memory 243196 kb
Host smart-b036780f-dd4b-41ac-ba72-db89ebb4f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163367569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1163367569
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3182442039
Short name T737
Test name
Test status
Simulation time 165872269 ps
CPU time 1.91 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 224092 kb
Host smart-0e87512f-0879-43e8-9037-d6da8547deba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182442039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3182442039
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.417523358
Short name T265
Test name
Test status
Simulation time 11423642749 ps
CPU time 87 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:35:16 PM PDT 24
Peak memory 236660 kb
Host smart-646eb9c7-d4f5-4bfd-8518-b0c724e0cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417523358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.417523358
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3982079775
Short name T887
Test name
Test status
Simulation time 4328222806 ps
CPU time 5.41 seconds
Started Jul 11 04:33:41 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 233652 kb
Host smart-e41b34d0-86e3-4717-93f5-defc6c65bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982079775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3982079775
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.878929757
Short name T594
Test name
Test status
Simulation time 3274478798 ps
CPU time 12.28 seconds
Started Jul 11 04:33:27 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 233788 kb
Host smart-a7f774f9-dfd3-424a-b694-2a771817fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878929757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.878929757
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.664132549
Short name T392
Test name
Test status
Simulation time 524633450 ps
CPU time 4.4 seconds
Started Jul 11 04:33:35 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 223456 kb
Host smart-fd76f28f-405b-43c8-84af-7481db32dca4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=664132549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.664132549
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2896459566
Short name T988
Test name
Test status
Simulation time 15537201240 ps
CPU time 63.81 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:55 PM PDT 24
Peak memory 253524 kb
Host smart-93ea736f-b0ad-464d-a6c1-5ea374ea9473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896459566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2896459566
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.18020587
Short name T705
Test name
Test status
Simulation time 13007523427 ps
CPU time 8.74 seconds
Started Jul 11 04:33:41 PM PDT 24
Finished Jul 11 04:34:09 PM PDT 24
Peak memory 217336 kb
Host smart-3db14f3b-29a8-42ef-ad0a-b8722484d34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18020587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.18020587
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3913329981
Short name T493
Test name
Test status
Simulation time 816780530 ps
CPU time 1.81 seconds
Started Jul 11 04:33:35 PM PDT 24
Finished Jul 11 04:33:56 PM PDT 24
Peak memory 217196 kb
Host smart-891fe816-b94e-41e9-8c4f-d949653d7704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913329981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3913329981
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1878731215
Short name T857
Test name
Test status
Simulation time 51991403 ps
CPU time 0.84 seconds
Started Jul 11 04:33:25 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 206896 kb
Host smart-e958c41d-7dc4-4423-9be5-42094963983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878731215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1878731215
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1842439957
Short name T195
Test name
Test status
Simulation time 101467938 ps
CPU time 2.5 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:54 PM PDT 24
Peak memory 241852 kb
Host smart-3383ffd4-5d5e-4b1f-b75b-b47382a492e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842439957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1842439957
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.565998763
Short name T760
Test name
Test status
Simulation time 23542269 ps
CPU time 0.68 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 206272 kb
Host smart-25adb062-5f18-43e5-9345-bdbb3d5187d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565998763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.565998763
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3454427241
Short name T515
Test name
Test status
Simulation time 32017543 ps
CPU time 2.17 seconds
Started Jul 11 04:33:25 PM PDT 24
Finished Jul 11 04:33:47 PM PDT 24
Peak memory 233380 kb
Host smart-8f7b1fad-1f71-4d76-ba2c-2ea8be5d05ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454427241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3454427241
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3075329438
Short name T757
Test name
Test status
Simulation time 17968718 ps
CPU time 0.91 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 206444 kb
Host smart-50be9a6a-9283-439d-8429-0b77a889b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075329438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3075329438
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4286756210
Short name T441
Test name
Test status
Simulation time 7108762648 ps
CPU time 33.42 seconds
Started Jul 11 04:33:39 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 241252 kb
Host smart-053fdb1a-2a24-441f-8162-6597bb94b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286756210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4286756210
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3681654880
Short name T250
Test name
Test status
Simulation time 4167060889 ps
CPU time 28.32 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 251504 kb
Host smart-6cffb216-6261-4fec-a783-2da0a16eeb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681654880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3681654880
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3147699694
Short name T411
Test name
Test status
Simulation time 62647624453 ps
CPU time 118.79 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:35:56 PM PDT 24
Peak memory 258244 kb
Host smart-440c642a-1b76-4c96-bedc-9df8b8c93e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147699694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3147699694
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2542486176
Short name T280
Test name
Test status
Simulation time 2367102618 ps
CPU time 10.81 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:34:02 PM PDT 24
Peak memory 233856 kb
Host smart-a7ae5162-8083-405a-9d2b-cbcdf7d97772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542486176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2542486176
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4280883553
Short name T920
Test name
Test status
Simulation time 21323164435 ps
CPU time 157.94 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:36:29 PM PDT 24
Peak memory 250284 kb
Host smart-4183a7a8-8635-4dfc-ab9f-fdab346018f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280883553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4280883553
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1423492794
Short name T248
Test name
Test status
Simulation time 2648537071 ps
CPU time 26.47 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 225432 kb
Host smart-bd5c73ab-a824-4e51-a5fd-ed63e16749d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423492794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1423492794
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4072522190
Short name T854
Test name
Test status
Simulation time 355504841 ps
CPU time 8.26 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 241424 kb
Host smart-e5435cd8-34bf-49a3-9126-e7e93491ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072522190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4072522190
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2065540025
Short name T449
Test name
Test status
Simulation time 820476658 ps
CPU time 8.5 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 233704 kb
Host smart-a362ecfa-9917-4d7c-9295-91eb0801bab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065540025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2065540025
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2548145042
Short name T997
Test name
Test status
Simulation time 381127348 ps
CPU time 3.22 seconds
Started Jul 11 04:33:23 PM PDT 24
Finished Jul 11 04:33:46 PM PDT 24
Peak memory 233720 kb
Host smart-354e3eb2-d39a-44c6-9864-dfd3b62a01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548145042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2548145042
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4205472713
Short name T813
Test name
Test status
Simulation time 906803836 ps
CPU time 8.66 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 224120 kb
Host smart-0bef2d0e-8f7e-4a10-b348-32f2ab28676e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205472713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4205472713
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.61876804
Short name T21
Test name
Test status
Simulation time 12595022973 ps
CPU time 90.27 seconds
Started Jul 11 04:33:33 PM PDT 24
Finished Jul 11 04:35:23 PM PDT 24
Peak memory 249808 kb
Host smart-cf0781e2-b005-4d9e-9b6d-005e5ff5ac42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61876804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.61876804
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1791212582
Short name T551
Test name
Test status
Simulation time 1852148699 ps
CPU time 16.93 seconds
Started Jul 11 04:33:26 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 217440 kb
Host smart-f582c052-baa2-4e8a-9942-fbb3381f4f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791212582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1791212582
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4076722038
Short name T470
Test name
Test status
Simulation time 1361233508 ps
CPU time 2.12 seconds
Started Jul 11 04:33:24 PM PDT 24
Finished Jul 11 04:33:45 PM PDT 24
Peak memory 208348 kb
Host smart-07eab59d-c618-4b41-ad4a-5b3c1309cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076722038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4076722038
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3025720785
Short name T456
Test name
Test status
Simulation time 497773780 ps
CPU time 2.14 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 217248 kb
Host smart-5241e680-8413-45ac-8b76-05fa38dd7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025720785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3025720785
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.500824886
Short name T436
Test name
Test status
Simulation time 126103523 ps
CPU time 0.97 seconds
Started Jul 11 04:33:27 PM PDT 24
Finished Jul 11 04:33:48 PM PDT 24
Peak memory 207872 kb
Host smart-9d2d4f3b-aa55-4212-aae2-472870031481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500824886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.500824886
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.945109965
Short name T188
Test name
Test status
Simulation time 1163163828 ps
CPU time 3.38 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 225432 kb
Host smart-a55a255a-722d-4f71-9362-3b1d9cc4ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945109965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.945109965
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1446382439
Short name T23
Test name
Test status
Simulation time 52915245 ps
CPU time 0.73 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:50 PM PDT 24
Peak memory 206228 kb
Host smart-b521c7fb-ce2b-40ef-afea-22429c265157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446382439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1446382439
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2007543214
Short name T653
Test name
Test status
Simulation time 34498705 ps
CPU time 2.53 seconds
Started Jul 11 04:33:35 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 233328 kb
Host smart-637ff32b-1a4d-4fd7-a36f-c159c624db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007543214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2007543214
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3613851715
Short name T917
Test name
Test status
Simulation time 20855354 ps
CPU time 0.73 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 206288 kb
Host smart-e27cbc4e-7b14-4bfb-bdc2-523dae8c14e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613851715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3613851715
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2140606309
Short name T176
Test name
Test status
Simulation time 227209874404 ps
CPU time 440.38 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:41:10 PM PDT 24
Peak memory 257080 kb
Host smart-96366536-f7cf-44a5-b255-c495ef76a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140606309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2140606309
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2175675949
Short name T215
Test name
Test status
Simulation time 17083311244 ps
CPU time 128.58 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 251192 kb
Host smart-7afbb10d-4867-482d-a7c4-8fd0bd924097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175675949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2175675949
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2484474325
Short name T621
Test name
Test status
Simulation time 224078611705 ps
CPU time 395.79 seconds
Started Jul 11 04:33:33 PM PDT 24
Finished Jul 11 04:40:28 PM PDT 24
Peak memory 254556 kb
Host smart-cd4720ec-f1d1-4d67-b14c-13c592b42d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484474325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2484474325
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2717558728
Short name T935
Test name
Test status
Simulation time 331332459 ps
CPU time 3.03 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:33:54 PM PDT 24
Peak memory 225384 kb
Host smart-917f5255-b7f0-4717-bb37-022fd705624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717558728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2717558728
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1521361516
Short name T260
Test name
Test status
Simulation time 167202456 ps
CPU time 5.08 seconds
Started Jul 11 04:33:33 PM PDT 24
Finished Jul 11 04:33:57 PM PDT 24
Peak memory 225368 kb
Host smart-0ecedead-4af0-4d6f-9283-2869ac0d2af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521361516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1521361516
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1875927306
Short name T736
Test name
Test status
Simulation time 1070600905 ps
CPU time 13.47 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 250532 kb
Host smart-94043058-1d09-4a1a-acb9-9d8716a54355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875927306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1875927306
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3494858985
Short name T540
Test name
Test status
Simulation time 2640330091 ps
CPU time 6.73 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 225612 kb
Host smart-b6e721eb-f939-463b-ab10-624981b27308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494858985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3494858985
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2394402570
Short name T267
Test name
Test status
Simulation time 3695536799 ps
CPU time 8.73 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 233864 kb
Host smart-fc5c4719-62d2-4b31-9fe1-caeaaa18f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394402570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2394402570
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.563464005
Short name T325
Test name
Test status
Simulation time 1872722250 ps
CPU time 5.89 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 220604 kb
Host smart-2daeda8c-7838-4450-a348-c9be9dc8efb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563464005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.563464005
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.260566887
Short name T70
Test name
Test status
Simulation time 88601797 ps
CPU time 1.09 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 207836 kb
Host smart-f924613a-0483-489c-a341-1104e0df6328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260566887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.260566887
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1849551765
Short name T583
Test name
Test status
Simulation time 1128636044 ps
CPU time 12.51 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:25 PM PDT 24
Peak memory 217300 kb
Host smart-d98cac68-aab9-4a38-9792-82a1c66355b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849551765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1849551765
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3101019581
Short name T877
Test name
Test status
Simulation time 1430635866 ps
CPU time 3.42 seconds
Started Jul 11 04:33:33 PM PDT 24
Finished Jul 11 04:33:56 PM PDT 24
Peak memory 217260 kb
Host smart-f98c5120-d32d-431e-8c20-8c073e85985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101019581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3101019581
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.505845996
Short name T296
Test name
Test status
Simulation time 124123929 ps
CPU time 1.53 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 217168 kb
Host smart-d25fc554-385b-4e20-8970-3ed576e665c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505845996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.505845996
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1809967446
Short name T919
Test name
Test status
Simulation time 46270366 ps
CPU time 0.76 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 206800 kb
Host smart-2a1dcc22-887e-4540-b995-8760c800f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809967446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1809967446
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2197833881
Short name T169
Test name
Test status
Simulation time 4094987382 ps
CPU time 18.47 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:16 PM PDT 24
Peak memory 249868 kb
Host smart-e8528a5d-9047-4ae8-9439-4e5a1e0f72eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197833881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2197833881
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1505057607
Short name T61
Test name
Test status
Simulation time 61030133 ps
CPU time 0.71 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 205768 kb
Host smart-889c375a-238e-49f5-99d2-e9cd6701d643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505057607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1505057607
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.142176633
Short name T826
Test name
Test status
Simulation time 107502139 ps
CPU time 2.29 seconds
Started Jul 11 04:33:29 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 225520 kb
Host smart-e63f8e0c-c263-4dd2-bcd5-7df8d5376856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142176633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.142176633
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1893218101
Short name T352
Test name
Test status
Simulation time 15444189 ps
CPU time 0.77 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:33:50 PM PDT 24
Peak memory 207472 kb
Host smart-3c8a0e1c-9846-4f9d-8fdf-07841eccb695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893218101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1893218101
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3071630760
Short name T512
Test name
Test status
Simulation time 235060431657 ps
CPU time 179.63 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:37:12 PM PDT 24
Peak memory 255092 kb
Host smart-126c834d-4ad6-46c2-93a0-976f122edce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071630760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3071630760
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.766201817
Short name T472
Test name
Test status
Simulation time 11060351039 ps
CPU time 105.62 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:35:43 PM PDT 24
Peak memory 250604 kb
Host smart-0f7757e9-ab34-4079-847d-b65868c9225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766201817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.766201817
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3400125682
Short name T220
Test name
Test status
Simulation time 220283198739 ps
CPU time 456.15 seconds
Started Jul 11 04:33:40 PM PDT 24
Finished Jul 11 04:41:37 PM PDT 24
Peak memory 265468 kb
Host smart-4f6ba899-d8ff-42bc-9784-c32aa602ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400125682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3400125682
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.988710990
Short name T639
Test name
Test status
Simulation time 1005699160 ps
CPU time 9.71 seconds
Started Jul 11 04:33:32 PM PDT 24
Finished Jul 11 04:34:01 PM PDT 24
Peak memory 241860 kb
Host smart-8f92b35e-93c5-459a-bcca-3ca82cbff8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988710990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.988710990
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4201742755
Short name T423
Test name
Test status
Simulation time 46199460497 ps
CPU time 81.78 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:35:19 PM PDT 24
Peak memory 242348 kb
Host smart-f43c551e-e922-4e6e-a13a-cb33cc37df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201742755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4201742755
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1035212303
Short name T433
Test name
Test status
Simulation time 125901617 ps
CPU time 2.34 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 233352 kb
Host smart-63ebc6ff-7fa5-43cb-a36f-7301cd0aef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035212303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1035212303
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.575372470
Short name T12
Test name
Test status
Simulation time 8700789202 ps
CPU time 22.89 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 233760 kb
Host smart-44e0db1e-71df-4bf0-9c79-f85c52fddd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575372470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.575372470
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2750771646
Short name T798
Test name
Test status
Simulation time 1105421517 ps
CPU time 7.19 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 236792 kb
Host smart-e827680a-4ba5-4dba-97e0-b15f8a830c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750771646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2750771646
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2456706783
Short name T272
Test name
Test status
Simulation time 3981085582 ps
CPU time 6.62 seconds
Started Jul 11 04:33:31 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 241156 kb
Host smart-d768b1dc-bbfa-49c3-8798-7b2c173bf8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456706783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2456706783
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1958968949
Short name T44
Test name
Test status
Simulation time 128321659 ps
CPU time 3.4 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:33:53 PM PDT 24
Peak memory 221672 kb
Host smart-118972c4-185d-4ddd-bfeb-5986ec7db14f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1958968949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1958968949
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.953068486
Short name T397
Test name
Test status
Simulation time 222405713 ps
CPU time 1.06 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:33:58 PM PDT 24
Peak memory 207712 kb
Host smart-f8da51eb-4719-4b94-9758-a5df377410d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953068486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.953068486
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3354200428
Short name T600
Test name
Test status
Simulation time 8909793258 ps
CPU time 52.16 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:35:05 PM PDT 24
Peak memory 217440 kb
Host smart-8a57c106-80b5-4bc8-85f0-be572e514976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354200428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3354200428
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3897767412
Short name T518
Test name
Test status
Simulation time 7536732254 ps
CPU time 11.61 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:08 PM PDT 24
Peak memory 217296 kb
Host smart-61a69241-6706-4f81-993d-fd65b56d479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897767412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3897767412
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1573049206
Short name T638
Test name
Test status
Simulation time 119321256 ps
CPU time 1.27 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 208980 kb
Host smart-1cb7c8bb-861c-4f9f-923d-519f949e560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573049206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1573049206
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3274601865
Short name T163
Test name
Test status
Simulation time 146116794 ps
CPU time 0.91 seconds
Started Jul 11 04:33:33 PM PDT 24
Finished Jul 11 04:33:53 PM PDT 24
Peak memory 207320 kb
Host smart-be250e21-e754-4e9b-b918-97a2f8a0f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274601865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3274601865
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.895857230
Short name T702
Test name
Test status
Simulation time 132597845 ps
CPU time 2.7 seconds
Started Jul 11 04:33:30 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 233680 kb
Host smart-96869acf-5a24-4402-ae73-d0732c53a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895857230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.895857230
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1741367286
Short name T347
Test name
Test status
Simulation time 23171225 ps
CPU time 0.74 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 206308 kb
Host smart-f2bc96d4-077a-4b64-911d-5bc5c3c1ff27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741367286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1741367286
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3318602270
Short name T306
Test name
Test status
Simulation time 3802909983 ps
CPU time 9.9 seconds
Started Jul 11 04:33:39 PM PDT 24
Finished Jul 11 04:34:09 PM PDT 24
Peak memory 233864 kb
Host smart-9ffb2433-4b16-435f-97b3-2fac0cf0a323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318602270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3318602270
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2509932548
Short name T310
Test name
Test status
Simulation time 13667634 ps
CPU time 0.74 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 207308 kb
Host smart-67659a99-08a6-4400-a262-c0d5f3a4ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509932548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2509932548
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.602942789
Short name T668
Test name
Test status
Simulation time 280552100382 ps
CPU time 187.03 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:37:06 PM PDT 24
Peak memory 258128 kb
Host smart-2666ad20-261e-4994-9d15-6aea7eefb958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602942789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.602942789
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2125256274
Short name T797
Test name
Test status
Simulation time 2948276202 ps
CPU time 45.12 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 252640 kb
Host smart-f037564c-8727-4693-9bf7-40ce8ca34010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125256274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2125256274
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1160611381
Short name T547
Test name
Test status
Simulation time 456042978 ps
CPU time 3.15 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:34:01 PM PDT 24
Peak memory 233736 kb
Host smart-dcfe97bf-8e87-4f25-8e40-1b73194b0d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160611381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1160611381
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2335000587
Short name T984
Test name
Test status
Simulation time 38204037226 ps
CPU time 121.31 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 258124 kb
Host smart-c1c12574-651a-494a-a028-dfa03091a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335000587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2335000587
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.465605102
Short name T828
Test name
Test status
Simulation time 2925864857 ps
CPU time 27.6 seconds
Started Jul 11 04:33:43 PM PDT 24
Finished Jul 11 04:34:32 PM PDT 24
Peak memory 225624 kb
Host smart-8bc20258-54e2-4174-9417-dfbc0ec32297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465605102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.465605102
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1099940850
Short name T483
Test name
Test status
Simulation time 1144620630 ps
CPU time 13.8 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:28 PM PDT 24
Peak memory 234644 kb
Host smart-236973e5-3347-40cb-8acc-c501b85f5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099940850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1099940850
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3268242758
Short name T1001
Test name
Test status
Simulation time 632926201 ps
CPU time 2.57 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 225548 kb
Host smart-3994b638-cdc3-49bf-a273-ac884c14956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268242758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3268242758
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.397125139
Short name T6
Test name
Test status
Simulation time 198074041 ps
CPU time 2.79 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:00 PM PDT 24
Peak memory 233752 kb
Host smart-37d32db4-2e9d-46fe-986a-a1c80ad68a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397125139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.397125139
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1767948336
Short name T735
Test name
Test status
Simulation time 74518068 ps
CPU time 3.81 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:20 PM PDT 24
Peak memory 219888 kb
Host smart-8d988d89-88da-4e6c-9ea6-6e9bb5f2dcbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767948336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1767948336
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1877694788
Short name T619
Test name
Test status
Simulation time 81083910073 ps
CPU time 163.35 seconds
Started Jul 11 04:33:41 PM PDT 24
Finished Jul 11 04:36:45 PM PDT 24
Peak memory 251000 kb
Host smart-ee501f51-0b69-4594-a298-b439a006fa78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877694788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1877694788
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3455611644
Short name T885
Test name
Test status
Simulation time 3194998533 ps
CPU time 18.91 seconds
Started Jul 11 04:33:39 PM PDT 24
Finished Jul 11 04:34:18 PM PDT 24
Peak memory 217448 kb
Host smart-f335ca86-32f9-4d09-ae84-da945446e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455611644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3455611644
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3942793515
Short name T664
Test name
Test status
Simulation time 253584422 ps
CPU time 1.52 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:33:59 PM PDT 24
Peak memory 208908 kb
Host smart-cb3a42f0-dd07-4a1c-9f1e-17b064a6af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942793515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3942793515
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.982272730
Short name T717
Test name
Test status
Simulation time 1107348860 ps
CPU time 8.01 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:04 PM PDT 24
Peak memory 217260 kb
Host smart-e3aa12c8-62af-4c13-9308-c01e39eab3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982272730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.982272730
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.33239187
Short name T762
Test name
Test status
Simulation time 288241414 ps
CPU time 0.96 seconds
Started Jul 11 04:33:47 PM PDT 24
Finished Jul 11 04:34:11 PM PDT 24
Peak memory 206892 kb
Host smart-51fd446d-18b8-447a-9f66-2431ce80b9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33239187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.33239187
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.32483070
Short name T172
Test name
Test status
Simulation time 5603311454 ps
CPU time 7.86 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 233732 kb
Host smart-7c2c0d51-34b6-4c95-b091-bd4dc024eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32483070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.32483070
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3990760034
Short name T763
Test name
Test status
Simulation time 20663154 ps
CPU time 0.66 seconds
Started Jul 11 04:34:16 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 206164 kb
Host smart-adf28c55-98c4-4b7a-a410-5ffa241e59f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990760034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3990760034
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.611560109
Short name T482
Test name
Test status
Simulation time 108180530 ps
CPU time 2.46 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:22 PM PDT 24
Peak memory 233480 kb
Host smart-8399298e-117d-4d21-8a50-ce4cd9cccbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611560109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.611560109
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.603490787
Short name T582
Test name
Test status
Simulation time 52724061 ps
CPU time 0.76 seconds
Started Jul 11 04:33:40 PM PDT 24
Finished Jul 11 04:34:01 PM PDT 24
Peak memory 206676 kb
Host smart-6a9168fb-87e5-43e8-8e8d-12b4b5cd4ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603490787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.603490787
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.277779945
Short name T1019
Test name
Test status
Simulation time 23523219892 ps
CPU time 178.55 seconds
Started Jul 11 04:33:37 PM PDT 24
Finished Jul 11 04:36:56 PM PDT 24
Peak memory 255752 kb
Host smart-5ccdc39e-2ad5-4de0-b8d2-0209a7feaedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277779945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.277779945
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.315097446
Short name T35
Test name
Test status
Simulation time 30126021071 ps
CPU time 300.39 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:39:26 PM PDT 24
Peak memory 253664 kb
Host smart-66863dd9-3cd6-411c-af0c-db8ea3e44228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315097446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.315097446
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.713626251
Short name T422
Test name
Test status
Simulation time 9664295371 ps
CPU time 16.96 seconds
Started Jul 11 04:33:44 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 218704 kb
Host smart-645e65ab-a74c-4d43-8018-8120351d8ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713626251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.713626251
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1681036986
Short name T4
Test name
Test status
Simulation time 33286052 ps
CPU time 2.54 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 233704 kb
Host smart-1147fe01-8b4c-41f6-a251-bb5dc98975f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681036986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1681036986
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1530027039
Short name T214
Test name
Test status
Simulation time 47683623705 ps
CPU time 114.39 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 251220 kb
Host smart-2335f1d9-13f6-4543-a1df-36f31afd06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530027039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1530027039
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.895934221
Short name T402
Test name
Test status
Simulation time 2669115493 ps
CPU time 7.27 seconds
Started Jul 11 04:33:45 PM PDT 24
Finished Jul 11 04:34:12 PM PDT 24
Peak memory 233792 kb
Host smart-3a518f7d-7d32-479a-8658-9d5859e3ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895934221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.895934221
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1681295195
Short name T201
Test name
Test status
Simulation time 2489121853 ps
CPU time 33.07 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:49 PM PDT 24
Peak memory 242016 kb
Host smart-56064012-12fc-46f4-86a8-5870ca9530be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681295195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1681295195
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4191747434
Short name T399
Test name
Test status
Simulation time 49163809916 ps
CPU time 31.91 seconds
Started Jul 11 04:33:36 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 233744 kb
Host smart-92102b79-6d16-40e7-b473-2ce06911950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191747434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4191747434
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1268440305
Short name T599
Test name
Test status
Simulation time 834420881 ps
CPU time 6.16 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:08 PM PDT 24
Peak memory 225404 kb
Host smart-fc88f954-665e-4755-98f9-f9bbcc3ffa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268440305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1268440305
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3558296419
Short name T1023
Test name
Test status
Simulation time 8315862408 ps
CPU time 7.05 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 221728 kb
Host smart-31edface-1c52-4f10-90e5-8b3823cf7c9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558296419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3558296419
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1589398790
Short name T678
Test name
Test status
Simulation time 5187496376 ps
CPU time 14.97 seconds
Started Jul 11 04:33:40 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 217372 kb
Host smart-f9241ba1-d6d0-4fd9-8d17-662a13b1864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589398790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1589398790
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3104073289
Short name T671
Test name
Test status
Simulation time 3845340542 ps
CPU time 8 seconds
Started Jul 11 04:33:38 PM PDT 24
Finished Jul 11 04:34:06 PM PDT 24
Peak memory 217500 kb
Host smart-f1d7ffb6-8395-442d-8c31-7b57d510a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104073289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3104073289
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.890181798
Short name T680
Test name
Test status
Simulation time 175413590 ps
CPU time 2.48 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:05 PM PDT 24
Peak memory 217228 kb
Host smart-2ac6bd7a-dd13-4066-ae0d-9b0937bad8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890181798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.890181798
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3594734236
Short name T698
Test name
Test status
Simulation time 54964131 ps
CPU time 0.72 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 206944 kb
Host smart-27d383b1-5345-4da5-8941-4e2418a59bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594734236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3594734236
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4270999019
Short name T684
Test name
Test status
Simulation time 3191613706 ps
CPU time 6.48 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 233852 kb
Host smart-fa564c0e-8dd1-4118-8359-945cab82e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270999019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4270999019
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4023262825
Short name T715
Test name
Test status
Simulation time 21294432 ps
CPU time 0.74 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 205744 kb
Host smart-a4573514-32eb-43e2-b323-8d635888b189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023262825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
023262825
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3900314715
Short name T432
Test name
Test status
Simulation time 4224994524 ps
CPU time 12.08 seconds
Started Jul 11 04:31:48 PM PDT 24
Finished Jul 11 04:32:22 PM PDT 24
Peak memory 233828 kb
Host smart-8b534391-9bc4-49a0-b0e0-c5a8cea2627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900314715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3900314715
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1547061597
Short name T827
Test name
Test status
Simulation time 47064335 ps
CPU time 0.77 seconds
Started Jul 11 04:31:40 PM PDT 24
Finished Jul 11 04:31:59 PM PDT 24
Peak memory 207340 kb
Host smart-c21cdf9c-bb43-4393-b141-1fb804c8bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547061597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1547061597
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2691491393
Short name T57
Test name
Test status
Simulation time 151933680983 ps
CPU time 106.22 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:34:05 PM PDT 24
Peak memory 250140 kb
Host smart-8485c7d1-c77d-4167-8b79-40e672568d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691491393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2691491393
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2341416594
Short name T291
Test name
Test status
Simulation time 50213409368 ps
CPU time 72.81 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:34:02 PM PDT 24
Peak memory 255008 kb
Host smart-7137d9f9-eb6a-4b28-bd01-4b870aeab965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341416594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2341416594
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1435688935
Short name T141
Test name
Test status
Simulation time 1027249717 ps
CPU time 15.15 seconds
Started Jul 11 04:31:46 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 225540 kb
Host smart-9ddd8158-4d44-4246-b0ee-3f81180c5a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435688935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1435688935
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.260730447
Short name T980
Test name
Test status
Simulation time 14490378317 ps
CPU time 125.9 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:34:55 PM PDT 24
Peak memory 267292 kb
Host smart-da824276-1720-4357-b53f-ab0575698ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260730447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
260730447
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3601715436
Short name T724
Test name
Test status
Simulation time 1822561971 ps
CPU time 20.39 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 233792 kb
Host smart-02ebe003-c44f-4a1b-a5c6-fa9a8269f69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601715436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3601715436
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.852090821
Short name T703
Test name
Test status
Simulation time 64048229 ps
CPU time 1.07 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 217436 kb
Host smart-1df667a1-191a-4c29-8147-4553b8a6a770
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852090821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.852090821
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1276695762
Short name T488
Test name
Test status
Simulation time 7403558406 ps
CPU time 16.23 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:29 PM PDT 24
Peak memory 233796 kb
Host smart-ac384d1b-cc76-4593-9691-fc05a1b7b1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276695762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1276695762
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3993726720
Short name T1005
Test name
Test status
Simulation time 4303008689 ps
CPU time 12.74 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 225668 kb
Host smart-83dea87d-8803-45d8-8e38-e26ade7286d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993726720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3993726720
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3300379679
Short name T497
Test name
Test status
Simulation time 4813165331 ps
CPU time 12.62 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:22 PM PDT 24
Peak memory 223184 kb
Host smart-c59a7c29-f335-4ecf-a0f9-6426eeee775d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3300379679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3300379679
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.637339031
Short name T64
Test name
Test status
Simulation time 112558030 ps
CPU time 1.04 seconds
Started Jul 11 04:32:19 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 236672 kb
Host smart-c0f7bd8d-922e-4777-896c-868272e7afb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637339031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.637339031
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2911751476
Short name T494
Test name
Test status
Simulation time 1459235426 ps
CPU time 9.67 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 217324 kb
Host smart-d67ad3d8-5d77-40e3-b8cb-14a8c5ce96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911751476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2911751476
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4087821488
Short name T457
Test name
Test status
Simulation time 4849836348 ps
CPU time 5.1 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:18 PM PDT 24
Peak memory 217404 kb
Host smart-6a913a16-a451-47be-9bf1-bb700273f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087821488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4087821488
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3975037814
Short name T758
Test name
Test status
Simulation time 15616515 ps
CPU time 0.84 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 207452 kb
Host smart-508c7ba0-b405-4930-8580-e60f803ae0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975037814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3975037814
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3022554482
Short name T1014
Test name
Test status
Simulation time 145227088 ps
CPU time 0.85 seconds
Started Jul 11 04:31:45 PM PDT 24
Finished Jul 11 04:32:07 PM PDT 24
Peak memory 206844 kb
Host smart-bca2c41e-e4f5-4d7e-ab33-8e8082560e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022554482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3022554482
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3106938967
Short name T471
Test name
Test status
Simulation time 564560947 ps
CPU time 4.13 seconds
Started Jul 11 04:31:54 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 233572 kb
Host smart-2adaea15-cae3-4666-9fc8-b5476b63d86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106938967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3106938967
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3209193593
Short name T500
Test name
Test status
Simulation time 27734451 ps
CPU time 0.67 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 206316 kb
Host smart-a1715893-17fb-4d66-9233-db3d31afadf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209193593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3209193593
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2550066353
Short name T247
Test name
Test status
Simulation time 34810809 ps
CPU time 2.33 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 233664 kb
Host smart-d317bc6d-84b1-4e84-beb1-bacc205af294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550066353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2550066353
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1326862544
Short name T339
Test name
Test status
Simulation time 227294732 ps
CPU time 0.73 seconds
Started Jul 11 04:33:43 PM PDT 24
Finished Jul 11 04:34:05 PM PDT 24
Peak memory 207356 kb
Host smart-50e4e327-e49e-4af5-b5be-10be18d97327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326862544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1326862544
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2885144203
Short name T408
Test name
Test status
Simulation time 29714026619 ps
CPU time 61.75 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:35:12 PM PDT 24
Peak memory 250184 kb
Host smart-0af078f6-91c4-4bfb-a44b-90ae266fd440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885144203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2885144203
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3652670250
Short name T81
Test name
Test status
Simulation time 24316868207 ps
CPU time 18.44 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:35 PM PDT 24
Peak memory 242032 kb
Host smart-3b60b872-baf4-4dcc-8ae6-d748a6b53020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652670250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3652670250
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3912620428
Short name T881
Test name
Test status
Simulation time 38326791118 ps
CPU time 132.36 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:36:25 PM PDT 24
Peak memory 255420 kb
Host smart-e08e43f4-e355-4919-a155-793e3e4cb227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912620428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3912620428
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2287552808
Short name T751
Test name
Test status
Simulation time 1971439001 ps
CPU time 28.72 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:45 PM PDT 24
Peak memory 235000 kb
Host smart-f3ef456e-6f2d-4374-83e5-f314b3edac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287552808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2287552808
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1556495970
Short name T225
Test name
Test status
Simulation time 18080656415 ps
CPU time 177.82 seconds
Started Jul 11 04:33:47 PM PDT 24
Finished Jul 11 04:37:07 PM PDT 24
Peak memory 250180 kb
Host smart-c8dc3d0e-e24e-4feb-803d-b6da357e1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556495970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1556495970
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3094944460
Short name T378
Test name
Test status
Simulation time 653719069 ps
CPU time 8.51 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 228732 kb
Host smart-f2d3c65a-8985-4df3-a862-44cb37598bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094944460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3094944460
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2883020361
Short name T257
Test name
Test status
Simulation time 21579076474 ps
CPU time 28.47 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:45 PM PDT 24
Peak memory 233796 kb
Host smart-8f57295b-440c-4e45-a4c6-8da7673d8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883020361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2883020361
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2789960687
Short name T216
Test name
Test status
Simulation time 793410218 ps
CPU time 6.89 seconds
Started Jul 11 04:34:19 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 241308 kb
Host smart-4733ee70-c071-40f6-a17d-601a2b953adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789960687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2789960687
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3127920981
Short name T779
Test name
Test status
Simulation time 1061816391 ps
CPU time 8.47 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 225464 kb
Host smart-3a677c60-3775-4c31-9ab9-082dffea9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127920981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3127920981
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3657210880
Short name T148
Test name
Test status
Simulation time 127542221 ps
CPU time 3.77 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 223320 kb
Host smart-5fbec405-a720-44bc-8e9a-93eca621f1bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3657210880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3657210880
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3249769929
Short name T159
Test name
Test status
Simulation time 81211364413 ps
CPU time 283.69 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:38:54 PM PDT 24
Peak memory 274332 kb
Host smart-5cfe0084-5c28-4fc1-b289-3445b9f2dc46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249769929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3249769929
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4255902741
Short name T738
Test name
Test status
Simulation time 766875159 ps
CPU time 7.06 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:20 PM PDT 24
Peak memory 217288 kb
Host smart-926cb6a4-207f-4b78-a6ae-488af7e17d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255902741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4255902741
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2654286507
Short name T962
Test name
Test status
Simulation time 13947538 ps
CPU time 0.73 seconds
Started Jul 11 04:33:42 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 206508 kb
Host smart-f81ddce6-bf0d-43b0-90e5-f81e8ffe2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654286507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2654286507
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3242344804
Short name T632
Test name
Test status
Simulation time 105264990 ps
CPU time 1.13 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:14 PM PDT 24
Peak memory 217136 kb
Host smart-b04e2913-6654-445c-803c-a00aac4aa146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242344804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3242344804
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2337987303
Short name T683
Test name
Test status
Simulation time 30679271 ps
CPU time 0.73 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 206760 kb
Host smart-3665bc4c-6083-4fc2-bf4a-a5ad08a378d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337987303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2337987303
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.382111975
Short name T173
Test name
Test status
Simulation time 165589184247 ps
CPU time 24.15 seconds
Started Jul 11 04:34:16 PM PDT 24
Finished Jul 11 04:35:03 PM PDT 24
Peak memory 239908 kb
Host smart-e4555795-82f3-4923-8ee6-65b2ca7f138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382111975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.382111975
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.799664261
Short name T514
Test name
Test status
Simulation time 35330727 ps
CPU time 0.7 seconds
Started Jul 11 04:33:46 PM PDT 24
Finished Jul 11 04:34:08 PM PDT 24
Peak memory 206328 kb
Host smart-c4c0e7c8-a031-4686-9524-956dd75de4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799664261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.799664261
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.466988468
Short name T129
Test name
Test status
Simulation time 545770696 ps
CPU time 3.12 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:23 PM PDT 24
Peak memory 225448 kb
Host smart-ef7e0353-9af9-4f42-86fc-31f5ac30ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466988468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.466988468
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2281107238
Short name T308
Test name
Test status
Simulation time 38617537 ps
CPU time 0.8 seconds
Started Jul 11 04:33:44 PM PDT 24
Finished Jul 11 04:34:05 PM PDT 24
Peak memory 207704 kb
Host smart-f83f93a9-2fba-4fac-9e18-7ecbc139c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281107238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2281107238
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3843086536
Short name T939
Test name
Test status
Simulation time 36914071092 ps
CPU time 89.11 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 250180 kb
Host smart-517322f6-009b-4f4c-b58c-7a9e18e363d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843086536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3843086536
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4222267604
Short name T692
Test name
Test status
Simulation time 31130202774 ps
CPU time 85.37 seconds
Started Jul 11 04:34:16 PM PDT 24
Finished Jul 11 04:36:04 PM PDT 24
Peak memory 252768 kb
Host smart-cebb2303-1866-43d3-9e4f-5d23d0f2f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222267604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4222267604
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3775626883
Short name T34
Test name
Test status
Simulation time 18797388980 ps
CPU time 179.1 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:37:24 PM PDT 24
Peak memory 250388 kb
Host smart-774b9e75-308d-40db-ae7d-f33de89fe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775626883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3775626883
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.105319918
Short name T332
Test name
Test status
Simulation time 220931977 ps
CPU time 4.92 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 241672 kb
Host smart-30ec84ea-0469-4fe2-8761-092cb88c1200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105319918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.105319918
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3111269006
Short name T805
Test name
Test status
Simulation time 9645388412 ps
CPU time 42.19 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:53 PM PDT 24
Peak memory 225568 kb
Host smart-8e6c452c-9bb2-4656-8e8b-68cb56688d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111269006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3111269006
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1253428667
Short name T415
Test name
Test status
Simulation time 411758571 ps
CPU time 4.85 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 233552 kb
Host smart-52e750d9-5ac8-455d-87a1-b2ac1179e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253428667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1253428667
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1723657468
Short name T601
Test name
Test status
Simulation time 6480886433 ps
CPU time 72.08 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:35:25 PM PDT 24
Peak memory 235592 kb
Host smart-b7b9143f-3a97-49d6-ba90-ef977b85f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723657468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1723657468
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3936242579
Short name T453
Test name
Test status
Simulation time 234470840 ps
CPU time 5.5 seconds
Started Jul 11 04:33:46 PM PDT 24
Finished Jul 11 04:34:11 PM PDT 24
Peak memory 241024 kb
Host smart-aa465673-c878-4551-ba1c-02ab92ea09ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936242579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3936242579
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.814887024
Short name T93
Test name
Test status
Simulation time 1766741202 ps
CPU time 5.73 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:18 PM PDT 24
Peak memory 225460 kb
Host smart-85f97897-b29b-46c1-9982-909712ad5597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814887024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.814887024
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1660322188
Short name T964
Test name
Test status
Simulation time 546532609 ps
CPU time 6.29 seconds
Started Jul 11 04:34:20 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 221652 kb
Host smart-27038133-1f32-43c0-93b5-8595580b7e2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660322188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1660322188
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1602356739
Short name T219
Test name
Test status
Simulation time 127870207476 ps
CPU time 545.33 seconds
Started Jul 11 04:33:54 PM PDT 24
Finished Jul 11 04:43:24 PM PDT 24
Peak memory 283636 kb
Host smart-7115ebf2-5e31-49c2-bcdb-7cb1a36f583e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602356739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1602356739
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1285044471
Short name T290
Test name
Test status
Simulation time 17105554465 ps
CPU time 27.02 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 221332 kb
Host smart-0be1c6f4-2239-44fb-9812-9348f0586984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285044471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1285044471
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1175625490
Short name T333
Test name
Test status
Simulation time 698770946 ps
CPU time 1.98 seconds
Started Jul 11 04:33:45 PM PDT 24
Finished Jul 11 04:34:07 PM PDT 24
Peak memory 217096 kb
Host smart-ba328e55-0c8e-4743-9c20-a44ea58c26db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175625490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1175625490
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.648246858
Short name T300
Test name
Test status
Simulation time 79014750 ps
CPU time 1.09 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:12 PM PDT 24
Peak memory 208836 kb
Host smart-b567570a-236e-4512-aa84-9993346647ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648246858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.648246858
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1999838928
Short name T812
Test name
Test status
Simulation time 76440260 ps
CPU time 0.84 seconds
Started Jul 11 04:33:43 PM PDT 24
Finished Jul 11 04:34:03 PM PDT 24
Peak memory 206956 kb
Host smart-0cbd26e1-e930-4288-a36b-097b3b54031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999838928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1999838928
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.423002210
Short name T351
Test name
Test status
Simulation time 691856677 ps
CPU time 2.91 seconds
Started Jul 11 04:33:47 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 233744 kb
Host smart-3f2f4808-3d13-4cab-b229-b94f439ea032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423002210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.423002210
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1359443699
Short name T343
Test name
Test status
Simulation time 25032076 ps
CPU time 0.7 seconds
Started Jul 11 04:33:54 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 206696 kb
Host smart-2b682d31-611a-429d-bc92-0e3c557033fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359443699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1359443699
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1582601739
Short name T319
Test name
Test status
Simulation time 439671015 ps
CPU time 4.78 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 233668 kb
Host smart-69814f17-ada4-43db-8ab4-c5d68a657972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582601739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1582601739
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2425884625
Short name T602
Test name
Test status
Simulation time 17967187 ps
CPU time 0.76 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 207640 kb
Host smart-75a2ed0d-59c2-4815-ba9d-1b80d2024e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425884625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2425884625
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3596065864
Short name T946
Test name
Test status
Simulation time 263912392 ps
CPU time 7.54 seconds
Started Jul 11 04:34:01 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 234672 kb
Host smart-8ebaedbd-0da7-4c72-9d20-9329d6f7a5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596065864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3596065864
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2730455699
Short name T1010
Test name
Test status
Simulation time 27534434057 ps
CPU time 72.58 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:35:26 PM PDT 24
Peak memory 250908 kb
Host smart-8211a5eb-2fb7-44a3-a650-207cf00651fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730455699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2730455699
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.255434888
Short name T753
Test name
Test status
Simulation time 2583881499 ps
CPU time 33.23 seconds
Started Jul 11 04:35:30 PM PDT 24
Finished Jul 11 04:36:04 PM PDT 24
Peak memory 233780 kb
Host smart-20d0c5ec-a4ae-45e2-8392-5041824432c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255434888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.255434888
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2445340072
Short name T880
Test name
Test status
Simulation time 341010933 ps
CPU time 7.63 seconds
Started Jul 11 04:35:11 PM PDT 24
Finished Jul 11 04:35:21 PM PDT 24
Peak memory 231880 kb
Host smart-01cac15f-2c71-4425-8532-2f94a554cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445340072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2445340072
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3868575543
Short name T259
Test name
Test status
Simulation time 89871024898 ps
CPU time 148.58 seconds
Started Jul 11 04:33:52 PM PDT 24
Finished Jul 11 04:36:45 PM PDT 24
Peak memory 256584 kb
Host smart-d82e4b70-dc83-4082-a45a-c9b346a2ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868575543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3868575543
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4184804620
Short name T553
Test name
Test status
Simulation time 204803739 ps
CPU time 2.81 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 233680 kb
Host smart-93daa68f-f7a3-4c9c-8f19-c75339fe12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184804620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4184804620
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.580601597
Short name T776
Test name
Test status
Simulation time 30989671857 ps
CPU time 58.26 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:35:11 PM PDT 24
Peak memory 230120 kb
Host smart-a205524c-3469-4a35-a113-fc7548391538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580601597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.580601597
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.878971854
Short name T718
Test name
Test status
Simulation time 1540927739 ps
CPU time 6.11 seconds
Started Jul 11 04:34:01 PM PDT 24
Finished Jul 11 04:34:31 PM PDT 24
Peak memory 225524 kb
Host smart-3fb9b8ad-f81e-46db-9313-63318567b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878971854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.878971854
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2333500916
Short name T398
Test name
Test status
Simulation time 63151914 ps
CPU time 2.78 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 233348 kb
Host smart-e52e83d5-1b13-4b76-80d7-b37566f068e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333500916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2333500916
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3214655389
Short name T838
Test name
Test status
Simulation time 411639815 ps
CPU time 5.33 seconds
Started Jul 11 04:33:52 PM PDT 24
Finished Jul 11 04:34:20 PM PDT 24
Peak memory 221232 kb
Host smart-b6faca32-d534-4222-bd07-affa51959efc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3214655389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3214655389
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1093886701
Short name T158
Test name
Test status
Simulation time 4356528947 ps
CPU time 27.47 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 252368 kb
Host smart-788f2b35-6ccc-4f12-b6f0-d38eb5e4d829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093886701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1093886701
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3797416796
Short name T843
Test name
Test status
Simulation time 2858236797 ps
CPU time 32.33 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 221388 kb
Host smart-ee183717-0715-4bd9-b37f-0e5bef4f8a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797416796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3797416796
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2285234022
Short name T740
Test name
Test status
Simulation time 617757925 ps
CPU time 2.4 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 208660 kb
Host smart-baa6a0be-5564-4575-8a1f-1a9cfd302fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285234022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2285234022
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.458067084
Short name T697
Test name
Test status
Simulation time 23160394 ps
CPU time 0.74 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:14 PM PDT 24
Peak memory 206852 kb
Host smart-daf9ea3f-7d66-4e40-aa04-083be0325dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458067084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.458067084
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.815081652
Short name T369
Test name
Test status
Simulation time 479847252 ps
CPU time 0.89 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 206832 kb
Host smart-b2fb843d-8ea7-454c-baf1-19409538341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815081652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.815081652
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3098038546
Short name T719
Test name
Test status
Simulation time 1690323109 ps
CPU time 3.65 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 225400 kb
Host smart-95deda8b-ed41-4d13-a927-ce8de5d7cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098038546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3098038546
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.7913001
Short name T434
Test name
Test status
Simulation time 33119280 ps
CPU time 0.7 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 205728 kb
Host smart-86dbb150-e180-4e4c-9946-ae0bcf13c2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7913001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.7913001
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.839257900
Short name T819
Test name
Test status
Simulation time 628778382 ps
CPU time 3.69 seconds
Started Jul 11 04:35:53 PM PDT 24
Finished Jul 11 04:35:59 PM PDT 24
Peak memory 225380 kb
Host smart-f35214eb-33fb-4d78-bc50-f8c02e14abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839257900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.839257900
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.849813409
Short name T574
Test name
Test status
Simulation time 33659127 ps
CPU time 0.75 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:13 PM PDT 24
Peak memory 206620 kb
Host smart-0b93ce9f-a5ba-450d-ba60-bef063e17420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849813409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.849813409
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.310168471
Short name T862
Test name
Test status
Simulation time 42511074547 ps
CPU time 176.87 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:37:13 PM PDT 24
Peak memory 267536 kb
Host smart-be942042-b58d-4f02-9585-bb20426046a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310168471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.310168471
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3891126254
Short name T799
Test name
Test status
Simulation time 18173147500 ps
CPU time 67.15 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:35:20 PM PDT 24
Peak memory 250592 kb
Host smart-2b68b49a-4242-4e89-8838-697584f106b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891126254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3891126254
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1356278277
Short name T477
Test name
Test status
Simulation time 85455989287 ps
CPU time 205.03 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:37:37 PM PDT 24
Peak memory 250612 kb
Host smart-8dee4a10-506c-447e-93b5-ee624cbd0ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356278277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1356278277
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.457913556
Short name T729
Test name
Test status
Simulation time 178367439 ps
CPU time 4.36 seconds
Started Jul 11 04:33:51 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 225552 kb
Host smart-1b69d565-ec0c-4513-848b-f92121fca3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457913556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.457913556
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4070801864
Short name T217
Test name
Test status
Simulation time 1845177507 ps
CPU time 51.9 seconds
Started Jul 11 04:33:52 PM PDT 24
Finished Jul 11 04:35:08 PM PDT 24
Peak memory 254684 kb
Host smart-7d9f2fd7-aaf9-4654-bcac-5b5e4d0b3bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070801864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4070801864
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.842686426
Short name T190
Test name
Test status
Simulation time 4055686589 ps
CPU time 22.65 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 225628 kb
Host smart-f1bce499-545d-4746-b2bf-63ec29d6ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842686426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.842686426
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1440292207
Short name T166
Test name
Test status
Simulation time 546788143 ps
CPU time 4.81 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 225528 kb
Host smart-33d6c934-40c0-4cfb-b0a9-c607779d9afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440292207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1440292207
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1266226131
Short name T802
Test name
Test status
Simulation time 1354286060 ps
CPU time 4.8 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 225384 kb
Host smart-bbffd386-c859-400d-82b4-9c5bce6886da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266226131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1266226131
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.512370841
Short name T869
Test name
Test status
Simulation time 33626242 ps
CPU time 2.47 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 233496 kb
Host smart-513193b3-b9a0-4d21-82c6-b78c055f4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512370841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.512370841
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2174957968
Short name T437
Test name
Test status
Simulation time 581377345 ps
CPU time 5.45 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:18 PM PDT 24
Peak memory 223188 kb
Host smart-d4076c58-506b-40c8-bafc-9de373b67274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2174957968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2174957968
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2032651615
Short name T501
Test name
Test status
Simulation time 8675856450 ps
CPU time 32.06 seconds
Started Jul 11 04:33:49 PM PDT 24
Finished Jul 11 04:34:44 PM PDT 24
Peak memory 217576 kb
Host smart-caa51915-0f65-4b20-a04d-7ae6815afba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032651615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2032651615
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1306473387
Short name T506
Test name
Test status
Simulation time 160740715 ps
CPU time 1.07 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 207948 kb
Host smart-a20fcaf9-f493-4909-b16f-220f631b5dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306473387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1306473387
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3366062610
Short name T860
Test name
Test status
Simulation time 63656401 ps
CPU time 0.91 seconds
Started Jul 11 04:35:11 PM PDT 24
Finished Jul 11 04:35:14 PM PDT 24
Peak memory 205168 kb
Host smart-40ed29d5-65fa-43d0-bc1c-e6d18443a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366062610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3366062610
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.128150064
Short name T646
Test name
Test status
Simulation time 22803180 ps
CPU time 0.71 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 206872 kb
Host smart-5b3dfdda-62b3-4e6c-81bd-d57705a848a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128150064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.128150064
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3326737504
Short name T651
Test name
Test status
Simulation time 6761515591 ps
CPU time 4.8 seconds
Started Jul 11 04:35:11 PM PDT 24
Finished Jul 11 04:35:18 PM PDT 24
Peak memory 223296 kb
Host smart-8375d82d-3e33-4dc2-8b10-7329558b64be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326737504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3326737504
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3855064557
Short name T848
Test name
Test status
Simulation time 13496679 ps
CPU time 0.7 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 206328 kb
Host smart-f51aa7ff-4a90-4fca-a39d-41348bb88c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855064557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3855064557
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2282365358
Short name T977
Test name
Test status
Simulation time 372544804 ps
CPU time 2.1 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:15 PM PDT 24
Peak memory 225048 kb
Host smart-8c00de6a-671e-4016-9059-6fd110b288f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282365358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2282365358
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1028102123
Short name T315
Test name
Test status
Simulation time 79494987 ps
CPU time 0.77 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 207652 kb
Host smart-223e2abe-6713-4df8-a31e-216e172e7f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028102123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1028102123
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1616552817
Short name T428
Test name
Test status
Simulation time 425885404 ps
CPU time 4.55 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:34:23 PM PDT 24
Peak memory 225500 kb
Host smart-2987046d-e620-46c0-a1b8-70fb2be69d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616552817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1616552817
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4289331730
Short name T55
Test name
Test status
Simulation time 318658003428 ps
CPU time 241.15 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:38:14 PM PDT 24
Peak memory 267668 kb
Host smart-f053c430-a458-47d8-979e-5c2de7cf58b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289331730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4289331730
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3992594798
Short name T416
Test name
Test status
Simulation time 77388648357 ps
CPU time 247.01 seconds
Started Jul 11 04:33:53 PM PDT 24
Finished Jul 11 04:38:23 PM PDT 24
Peak memory 253052 kb
Host smart-3852b323-88d1-45ad-ac9a-fe429d83ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992594798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3992594798
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2235589761
Short name T467
Test name
Test status
Simulation time 1675825759 ps
CPU time 7.17 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 233744 kb
Host smart-50e38240-705d-47b7-9367-5e35b496a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235589761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2235589761
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.499898247
Short name T987
Test name
Test status
Simulation time 304586559 ps
CPU time 7.23 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 240396 kb
Host smart-8d4b0996-920f-46c2-8d86-83eb8c8e2ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499898247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.499898247
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1936591342
Short name T772
Test name
Test status
Simulation time 61045832 ps
CPU time 2.49 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 233484 kb
Host smart-6e46ef87-af1f-4ced-a678-6d80cb5cd978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936591342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1936591342
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3327728653
Short name T203
Test name
Test status
Simulation time 2875809174 ps
CPU time 5.57 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 225560 kb
Host smart-e99cf9af-89a3-4b1b-973d-9217f7b3281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327728653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3327728653
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1916671248
Short name T616
Test name
Test status
Simulation time 135560461 ps
CPU time 3.58 seconds
Started Jul 11 04:33:50 PM PDT 24
Finished Jul 11 04:34:16 PM PDT 24
Peak memory 219880 kb
Host smart-2c9d407e-c6ea-4964-b5aa-927c0b32cd9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1916671248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1916671248
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1159214579
Short name T965
Test name
Test status
Simulation time 7155654063 ps
CPU time 18.55 seconds
Started Jul 11 04:33:48 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 217680 kb
Host smart-048d31af-b254-4e96-b551-24dfc007a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159214579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1159214579
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2651550547
Short name T328
Test name
Test status
Simulation time 1120025393 ps
CPU time 7.35 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 217328 kb
Host smart-9d2fcb09-bd23-4fbc-b302-8bceb6a4b2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651550547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2651550547
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4061030393
Short name T489
Test name
Test status
Simulation time 16306832 ps
CPU time 0.73 seconds
Started Jul 11 04:35:11 PM PDT 24
Finished Jul 11 04:35:14 PM PDT 24
Peak memory 205308 kb
Host smart-79c9d015-a173-4509-b744-69ff6fd02a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061030393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4061030393
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1041736773
Short name T316
Test name
Test status
Simulation time 18348809 ps
CPU time 0.71 seconds
Started Jul 11 04:35:33 PM PDT 24
Finished Jul 11 04:35:34 PM PDT 24
Peak memory 206768 kb
Host smart-d6de6d61-8c12-4665-941d-a2378eefd267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041736773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1041736773
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.86690899
Short name T389
Test name
Test status
Simulation time 985487198 ps
CPU time 4.28 seconds
Started Jul 11 04:33:54 PM PDT 24
Finished Jul 11 04:34:23 PM PDT 24
Peak memory 233600 kb
Host smart-f58eb167-8fd3-428c-8110-8465cee992e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86690899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.86690899
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1798382330
Short name T577
Test name
Test status
Simulation time 12616287 ps
CPU time 0.75 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 206332 kb
Host smart-0a2e76cb-e87e-4fcb-a929-29601fe76872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798382330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1798382330
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1249451267
Short name T834
Test name
Test status
Simulation time 44971762 ps
CPU time 2.38 seconds
Started Jul 11 04:33:54 PM PDT 24
Finished Jul 11 04:34:21 PM PDT 24
Peak memory 225720 kb
Host smart-54295dbe-1880-4bf2-92bb-917782c407ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249451267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1249451267
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1790382940
Short name T557
Test name
Test status
Simulation time 18559065 ps
CPU time 0.78 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:34:19 PM PDT 24
Peak memory 207804 kb
Host smart-340feb18-5612-495f-b2ec-4087a0eed0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790382940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1790382940
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.509334840
Short name T208
Test name
Test status
Simulation time 11108119693 ps
CPU time 63.61 seconds
Started Jul 11 04:35:30 PM PDT 24
Finished Jul 11 04:36:35 PM PDT 24
Peak memory 251228 kb
Host smart-e7d5fbf4-4488-4d47-862e-63249d052f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509334840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.509334840
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3623133509
Short name T933
Test name
Test status
Simulation time 106987396853 ps
CPU time 222.36 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:38:01 PM PDT 24
Peak memory 256144 kb
Host smart-b06dd506-2d15-416e-84b0-d78b0223de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623133509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3623133509
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.911979114
Short name T435
Test name
Test status
Simulation time 9687837265 ps
CPU time 16.9 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:37 PM PDT 24
Peak memory 219000 kb
Host smart-353bfdd8-4da7-42af-afe6-d77dbab2db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911979114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.911979114
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.241267590
Short name T417
Test name
Test status
Simulation time 222971753 ps
CPU time 4.4 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 225520 kb
Host smart-b5ca78b8-7275-4930-8fd6-43392efaf0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241267590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.241267590
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1809353336
Short name T774
Test name
Test status
Simulation time 26882917693 ps
CPU time 185.63 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:37:29 PM PDT 24
Peak memory 258452 kb
Host smart-9e3dd5cb-366a-4a0d-a898-1fa12c39ecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809353336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1809353336
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2218876165
Short name T550
Test name
Test status
Simulation time 16158967415 ps
CPU time 15.16 seconds
Started Jul 11 04:33:54 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 233812 kb
Host smart-ac106d6b-1a8c-4529-afb3-b117cdb1dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218876165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2218876165
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.945124643
Short name T189
Test name
Test status
Simulation time 16396035386 ps
CPU time 59.23 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:35:28 PM PDT 24
Peak memory 236944 kb
Host smart-4a4af8a9-27b1-4f19-a117-64f1d728ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945124643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.945124643
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1855447222
Short name T674
Test name
Test status
Simulation time 15819898908 ps
CPU time 25.89 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:34:49 PM PDT 24
Peak memory 252728 kb
Host smart-a826b16a-13a7-4469-87bf-06cf62adef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855447222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1855447222
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.832707015
Short name T534
Test name
Test status
Simulation time 3162727635 ps
CPU time 6.41 seconds
Started Jul 11 04:34:20 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 233816 kb
Host smart-60780819-2416-4a8a-bea9-858e8c53b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832707015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.832707015
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.348510489
Short name T850
Test name
Test status
Simulation time 8605119386 ps
CPU time 16.29 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 223456 kb
Host smart-3bbcb55f-a911-4e83-985c-69f8b95582d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=348510489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.348510489
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3866471985
Short name T580
Test name
Test status
Simulation time 182480448 ps
CPU time 0.88 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 206736 kb
Host smart-06663e55-7525-4f10-b4f9-f12a9d1a5e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866471985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3866471985
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1786801141
Short name T519
Test name
Test status
Simulation time 66037934784 ps
CPU time 41.3 seconds
Started Jul 11 04:34:20 PM PDT 24
Finished Jul 11 04:35:23 PM PDT 24
Peak memory 217388 kb
Host smart-31061a1c-cc7f-400d-94a4-9530524eba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786801141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1786801141
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1094822023
Short name T509
Test name
Test status
Simulation time 7342608449 ps
CPU time 9.46 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 217412 kb
Host smart-42bed078-801c-4d6e-8ed9-1adcb5e23bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094822023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1094822023
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.938799037
Short name T1004
Test name
Test status
Simulation time 27658012 ps
CPU time 1.69 seconds
Started Jul 11 04:34:21 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 217352 kb
Host smart-fbc2c5cc-a5d8-4f30-89e8-051786ba43d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938799037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.938799037
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3802349688
Short name T593
Test name
Test status
Simulation time 129331182 ps
CPU time 0.87 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:34:28 PM PDT 24
Peak memory 207948 kb
Host smart-b640e463-2b92-4937-8f43-984d25983d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802349688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3802349688
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.691224733
Short name T530
Test name
Test status
Simulation time 2150797795 ps
CPU time 13.1 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:34:41 PM PDT 24
Peak memory 233872 kb
Host smart-85c4fa56-4a2f-4312-a320-8bb8c4b53507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691224733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.691224733
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3107209721
Short name T356
Test name
Test status
Simulation time 39352597 ps
CPU time 0.75 seconds
Started Jul 11 04:34:21 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 205768 kb
Host smart-d994e8e1-a671-427a-9925-ba793040e458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107209721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3107209721
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3655057870
Short name T269
Test name
Test status
Simulation time 147277213 ps
CPU time 2.58 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:24 PM PDT 24
Peak memory 233764 kb
Host smart-f391158f-e01d-40ad-99e3-75e5d051c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655057870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3655057870
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3974417770
Short name T925
Test name
Test status
Simulation time 16196490 ps
CPU time 0.75 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:25 PM PDT 24
Peak memory 207688 kb
Host smart-614a9082-26bb-4417-b9e9-c17823cd0388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974417770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3974417770
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2292699614
Short name T592
Test name
Test status
Simulation time 45907713699 ps
CPU time 179.73 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:37:24 PM PDT 24
Peak memory 251868 kb
Host smart-b3baa781-5c2c-47ff-b3a1-f5df52afd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292699614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2292699614
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3547711274
Short name T294
Test name
Test status
Simulation time 29121022173 ps
CPU time 38.84 seconds
Started Jul 11 04:34:02 PM PDT 24
Finished Jul 11 04:35:04 PM PDT 24
Peak memory 218540 kb
Host smart-a07c7198-4fad-4bec-9059-3cf00f6ce8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547711274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3547711274
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1480176888
Short name T745
Test name
Test status
Simulation time 23270579008 ps
CPU time 120.25 seconds
Started Jul 11 04:34:21 PM PDT 24
Finished Jul 11 04:36:42 PM PDT 24
Peak memory 254988 kb
Host smart-40066892-c3f9-41c3-a503-2008ff7a1474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480176888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1480176888
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2579229136
Short name T748
Test name
Test status
Simulation time 15421193363 ps
CPU time 36.63 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:34:59 PM PDT 24
Peak memory 233760 kb
Host smart-2fd0e045-95f8-484a-8cbe-6275cad06653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579229136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2579229136
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4032793944
Short name T759
Test name
Test status
Simulation time 38658352 ps
CPU time 0.75 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:25 PM PDT 24
Peak memory 216792 kb
Host smart-3e8e354c-96f8-45e3-818b-0e5a423c2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032793944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4032793944
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3731343348
Short name T641
Test name
Test status
Simulation time 1695689208 ps
CPU time 16.4 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:50 PM PDT 24
Peak memory 233684 kb
Host smart-b80a02da-9b39-45ff-a739-cfebc218ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731343348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3731343348
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2756820813
Short name T990
Test name
Test status
Simulation time 122027361 ps
CPU time 2.34 seconds
Started Jul 11 04:33:57 PM PDT 24
Finished Jul 11 04:34:24 PM PDT 24
Peak memory 225148 kb
Host smart-3ea7d87d-dcb4-4b47-9ff9-f80a8873f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756820813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2756820813
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4238295008
Short name T490
Test name
Test status
Simulation time 7310189346 ps
CPU time 11.81 seconds
Started Jul 11 04:33:56 PM PDT 24
Finished Jul 11 04:34:32 PM PDT 24
Peak memory 225548 kb
Host smart-020516ab-4da5-44b0-aa86-e92c6cb74c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238295008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4238295008
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1090971392
Short name T556
Test name
Test status
Simulation time 10395499645 ps
CPU time 12.95 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 225668 kb
Host smart-1cf3e918-a08e-4bfd-991c-811fb7c8ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090971392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1090971392
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1781971458
Short name T350
Test name
Test status
Simulation time 1587800580 ps
CPU time 5.35 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:35 PM PDT 24
Peak memory 221188 kb
Host smart-0532405b-3100-4085-879a-562c51405224
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781971458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1781971458
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.259840017
Short name T222
Test name
Test status
Simulation time 216814124292 ps
CPU time 989.5 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 266816 kb
Host smart-70a792bb-31cd-469f-806f-d07cd8295bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259840017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.259840017
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2150759401
Short name T706
Test name
Test status
Simulation time 743727338 ps
CPU time 4.37 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:26 PM PDT 24
Peak memory 217328 kb
Host smart-170c03b1-c1c2-4b1b-be6b-541ba0529fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150759401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2150759401
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1589230771
Short name T410
Test name
Test status
Simulation time 13368267318 ps
CPU time 17.48 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 217400 kb
Host smart-b3550772-570d-403f-9e53-fd7a556e719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589230771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1589230771
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3597713653
Short name T377
Test name
Test status
Simulation time 96109630 ps
CPU time 1.68 seconds
Started Jul 11 04:33:55 PM PDT 24
Finished Jul 11 04:34:20 PM PDT 24
Peak memory 217552 kb
Host smart-31ac53da-48a0-4acc-904c-9f6c7450536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597713653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3597713653
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3750559458
Short name T781
Test name
Test status
Simulation time 295847481 ps
CPU time 0.95 seconds
Started Jul 11 04:33:58 PM PDT 24
Finished Jul 11 04:34:23 PM PDT 24
Peak memory 207852 kb
Host smart-71e2b691-c495-4a60-8965-a5ca2abcd5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750559458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3750559458
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.432266259
Short name T86
Test name
Test status
Simulation time 4182690702 ps
CPU time 17.19 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:34:45 PM PDT 24
Peak memory 233800 kb
Host smart-7f0e8fe3-00b8-4f49-b539-d4ceb0323417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432266259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.432266259
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1903625429
Short name T334
Test name
Test status
Simulation time 12559907 ps
CPU time 0.69 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 205692 kb
Host smart-95be308a-2b61-4c09-9daf-561e77d03796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903625429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1903625429
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.486651419
Short name T634
Test name
Test status
Simulation time 3618894502 ps
CPU time 17.54 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:34:51 PM PDT 24
Peak memory 225616 kb
Host smart-cb208075-38b3-4a23-b678-e3949c0cff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486651419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.486651419
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.500457223
Short name T455
Test name
Test status
Simulation time 17339979 ps
CPU time 0.78 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 207352 kb
Host smart-6d053654-672f-4df5-8338-305a81239591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500457223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.500457223
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3220052449
Short name T452
Test name
Test status
Simulation time 137921458136 ps
CPU time 240.8 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:38:33 PM PDT 24
Peak memory 257656 kb
Host smart-cc3a93e5-d366-42fb-8b18-46784c84ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220052449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3220052449
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2252904943
Short name T1002
Test name
Test status
Simulation time 18662266823 ps
CPU time 18.59 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:34:51 PM PDT 24
Peak memory 218560 kb
Host smart-646b854f-0261-41bc-af68-b35cd50a50a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252904943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2252904943
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2615080802
Short name T792
Test name
Test status
Simulation time 80707887598 ps
CPU time 180.83 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:37:30 PM PDT 24
Peak memory 239612 kb
Host smart-b7c570ce-8568-47cd-a2aa-f7c543877fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615080802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2615080802
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.186679212
Short name T144
Test name
Test status
Simulation time 2231270542 ps
CPU time 18.25 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:34:42 PM PDT 24
Peak memory 238568 kb
Host smart-1bb85e8e-a272-47be-8439-34e7649cf93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186679212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.186679212
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3742477339
Short name T182
Test name
Test status
Simulation time 27908932451 ps
CPU time 100.7 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:36:12 PM PDT 24
Peak memory 252536 kb
Host smart-6c2aa09e-9ed7-4fb7-abab-929a9c205da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742477339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3742477339
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3932260402
Short name T495
Test name
Test status
Simulation time 548305535 ps
CPU time 4.94 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 233732 kb
Host smart-a98e96eb-be62-4aec-8899-dddb734259d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932260402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3932260402
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3117646888
Short name T644
Test name
Test status
Simulation time 1425299742 ps
CPU time 15.19 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 225556 kb
Host smart-dddbbfd3-7bda-471b-91c1-b29c26a0a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117646888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3117646888
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.217113182
Short name T94
Test name
Test status
Simulation time 1449539410 ps
CPU time 4.4 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 225480 kb
Host smart-a886ca48-9fce-4cc8-bc1d-88469160d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217113182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.217113182
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3988542683
Short name T448
Test name
Test status
Simulation time 242655429 ps
CPU time 1.97 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 224036 kb
Host smart-de0ca615-d680-4935-a4b5-ec4d3e8b8cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988542683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3988542683
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.901066188
Short name T69
Test name
Test status
Simulation time 1033827814 ps
CPU time 4.17 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 221612 kb
Host smart-25c46cae-84c7-448e-9bf0-9ccb103761e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=901066188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.901066188
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2746947952
Short name T808
Test name
Test status
Simulation time 6803586774 ps
CPU time 35.15 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:35:07 PM PDT 24
Peak memory 242220 kb
Host smart-1be3955a-6620-4af1-a364-aabadb23ed1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746947952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2746947952
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1400735373
Short name T49
Test name
Test status
Simulation time 6247558923 ps
CPU time 34.96 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:35:04 PM PDT 24
Peak memory 217416 kb
Host smart-1ea05c06-d7d1-4024-b759-d044652bcccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400735373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1400735373
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.834476887
Short name T429
Test name
Test status
Simulation time 2065639202 ps
CPU time 6.69 seconds
Started Jul 11 04:33:59 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 217248 kb
Host smart-b87e364c-1ea7-4ef4-b782-cbbef8ffc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834476887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.834476887
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2787141687
Short name T395
Test name
Test status
Simulation time 35751957 ps
CPU time 0.88 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 207636 kb
Host smart-930e8492-e3d2-4cc2-a35c-5b034f112122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787141687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2787141687
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1432885182
Short name T85
Test name
Test status
Simulation time 72449613 ps
CPU time 0.94 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 206952 kb
Host smart-7c9f67ea-0ecb-4a41-ada8-b476df04ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432885182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1432885182
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1306197357
Short name T811
Test name
Test status
Simulation time 436353258 ps
CPU time 3.16 seconds
Started Jul 11 04:34:00 PM PDT 24
Finished Jul 11 04:34:28 PM PDT 24
Peak memory 233608 kb
Host smart-25a3a8e4-acf1-4722-8d4f-8e0c4d37fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306197357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1306197357
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1294011005
Short name T370
Test name
Test status
Simulation time 12095923 ps
CPU time 0.71 seconds
Started Jul 11 04:34:10 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 206692 kb
Host smart-ad6a8fb6-8bc6-46b1-9e2e-3bc8e4913451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294011005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1294011005
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4265566902
Short name T89
Test name
Test status
Simulation time 125810330 ps
CPU time 2.62 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:32 PM PDT 24
Peak memory 225512 kb
Host smart-4ac4e272-ce92-413e-bcdb-199977c5caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265566902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4265566902
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1365084269
Short name T418
Test name
Test status
Simulation time 15469393 ps
CPU time 0.82 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:30 PM PDT 24
Peak memory 207448 kb
Host smart-43fb9643-294f-4e36-bd3a-5c8a4db59d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365084269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1365084269
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4132368725
Short name T502
Test name
Test status
Simulation time 8399178644 ps
CPU time 84.5 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:35:58 PM PDT 24
Peak memory 258164 kb
Host smart-fd903cb9-1492-4de2-b761-678d8029a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132368725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4132368725
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1064146124
Short name T1012
Test name
Test status
Simulation time 22814610614 ps
CPU time 39.72 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:35:12 PM PDT 24
Peak memory 242032 kb
Host smart-796ce5bc-cb9f-44ff-a7d3-e98885e5dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064146124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1064146124
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1726124539
Short name T251
Test name
Test status
Simulation time 177291006580 ps
CPU time 381.58 seconds
Started Jul 11 04:34:11 PM PDT 24
Finished Jul 11 04:40:57 PM PDT 24
Peak memory 250388 kb
Host smart-cb511eba-5b42-4f38-bde0-a6ae5a3e3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726124539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1726124539
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.734158842
Short name T513
Test name
Test status
Simulation time 57301825 ps
CPU time 3.08 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:34:35 PM PDT 24
Peak memory 233704 kb
Host smart-e707a1f1-a757-437b-9068-7423bacad882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734158842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.734158842
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2197564863
Short name T231
Test name
Test status
Simulation time 34104117013 ps
CPU time 274.21 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:39:07 PM PDT 24
Peak memory 240568 kb
Host smart-28951dc9-d005-40bb-852a-6a0e1b0a7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197564863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2197564863
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.108245072
Short name T252
Test name
Test status
Simulation time 298084677 ps
CPU time 3.32 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:34:31 PM PDT 24
Peak memory 233728 kb
Host smart-60a1c401-c94b-4e9e-83f8-1c8040a6c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108245072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.108245072
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1743700485
Short name T647
Test name
Test status
Simulation time 15245080232 ps
CPU time 42.55 seconds
Started Jul 11 04:34:03 PM PDT 24
Finished Jul 11 04:35:10 PM PDT 24
Peak memory 225508 kb
Host smart-6da1baa9-6887-4c1a-a918-c1e8fd11e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743700485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1743700485
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3063406966
Short name T789
Test name
Test status
Simulation time 448887064 ps
CPU time 7.34 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 241892 kb
Host smart-6f9fddec-1ab2-4bae-8813-4d66a4d10c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063406966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3063406966
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4225536168
Short name T623
Test name
Test status
Simulation time 2562150118 ps
CPU time 9.51 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:34:38 PM PDT 24
Peak memory 225600 kb
Host smart-63bf9243-84a8-41f2-8164-9e2f38605588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225536168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4225536168
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2753965897
Short name T672
Test name
Test status
Simulation time 2720447699 ps
CPU time 14.03 seconds
Started Jul 11 04:34:09 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 222676 kb
Host smart-180ba979-95de-45dc-a0af-907f7c4770df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2753965897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2753965897
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1686784475
Short name T1007
Test name
Test status
Simulation time 309803716987 ps
CPU time 704.17 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:46:16 PM PDT 24
Peak memory 274940 kb
Host smart-78e33ac8-c325-499b-9e02-cd48bb1f884d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686784475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1686784475
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2556817875
Short name T289
Test name
Test status
Simulation time 7247093961 ps
CPU time 19.39 seconds
Started Jul 11 04:34:09 PM PDT 24
Finished Jul 11 04:34:55 PM PDT 24
Peak memory 221112 kb
Host smart-1ab4b082-1304-4cd8-9214-8dafdbc6f098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556817875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2556817875
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3054547934
Short name T128
Test name
Test status
Simulation time 1817523129 ps
CPU time 7.16 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 217360 kb
Host smart-8593fb63-59f6-4605-b8d4-1047d5a41983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054547934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3054547934
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2201977638
Short name T307
Test name
Test status
Simulation time 95530648 ps
CPU time 1.61 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:31 PM PDT 24
Peak memory 217368 kb
Host smart-6ed06075-cea4-409c-a269-632fa6d92052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201977638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2201977638
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4048560790
Short name T312
Test name
Test status
Simulation time 280276843 ps
CPU time 0.86 seconds
Started Jul 11 04:34:04 PM PDT 24
Finished Jul 11 04:34:29 PM PDT 24
Peak memory 206940 kb
Host smart-03c596bc-266e-40d7-9c95-30afd4eb028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048560790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4048560790
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.859863067
Short name T478
Test name
Test status
Simulation time 1057410320 ps
CPU time 9.29 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:34:43 PM PDT 24
Peak memory 237580 kb
Host smart-401c9513-ec7a-497d-8bce-c6cf93f9d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859863067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.859863067
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.966775424
Short name T825
Test name
Test status
Simulation time 39433062 ps
CPU time 0.7 seconds
Started Jul 11 04:34:12 PM PDT 24
Finished Jul 11 04:34:37 PM PDT 24
Peak memory 206164 kb
Host smart-1e068611-8565-4bb2-8d71-b2603f595946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966775424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.966775424
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2116402708
Short name T791
Test name
Test status
Simulation time 109741381 ps
CPU time 2.48 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:34 PM PDT 24
Peak memory 233720 kb
Host smart-36c8f1f3-e436-4145-96e4-e15269a89161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116402708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2116402708
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2698243857
Short name T313
Test name
Test status
Simulation time 15231180 ps
CPU time 0.77 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:33 PM PDT 24
Peak memory 207364 kb
Host smart-f5506f23-7f98-495d-984f-0743fbedcbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698243857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2698243857
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1379793445
Short name T985
Test name
Test status
Simulation time 23871405405 ps
CPU time 172.89 seconds
Started Jul 11 04:34:13 PM PDT 24
Finished Jul 11 04:37:30 PM PDT 24
Peak memory 250248 kb
Host smart-9807abde-e18d-4438-a4a9-1489aa8d5129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379793445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1379793445
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.800054822
Short name T425
Test name
Test status
Simulation time 26529586630 ps
CPU time 249.85 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:38:48 PM PDT 24
Peak memory 250264 kb
Host smart-9eaa5c2e-34ee-42f9-acb1-f74289397257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800054822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.800054822
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.540880714
Short name T1025
Test name
Test status
Simulation time 3904905597 ps
CPU time 32.89 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:35:11 PM PDT 24
Peak memory 242068 kb
Host smart-12b65528-58da-4ca3-9587-c051597ae387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540880714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.540880714
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2343341163
Short name T720
Test name
Test status
Simulation time 7491038067 ps
CPU time 15.45 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:34:45 PM PDT 24
Peak memory 238860 kb
Host smart-0842b321-f9f3-45c0-87d8-7653caac0096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343341163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2343341163
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2776956760
Short name T584
Test name
Test status
Simulation time 297077433 ps
CPU time 5 seconds
Started Jul 11 04:34:09 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 233640 kb
Host smart-34a59331-fcc0-42c9-af79-073b3731a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776956760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2776956760
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4007807104
Short name T999
Test name
Test status
Simulation time 21651899471 ps
CPU time 83.83 seconds
Started Jul 11 04:34:06 PM PDT 24
Finished Jul 11 04:35:55 PM PDT 24
Peak memory 242048 kb
Host smart-77362548-4bda-4f2b-9ead-0a4e0a09b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007807104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4007807104
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3419448033
Short name T274
Test name
Test status
Simulation time 5177456735 ps
CPU time 6.6 seconds
Started Jul 11 04:34:08 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 233800 kb
Host smart-e48d6d27-4153-4c59-998f-39d4c676bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419448033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3419448033
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2120875676
Short name T382
Test name
Test status
Simulation time 1284034164 ps
CPU time 2.05 seconds
Started Jul 11 04:34:05 PM PDT 24
Finished Jul 11 04:34:31 PM PDT 24
Peak memory 224124 kb
Host smart-979eb179-2f62-4f5f-a8a5-ac8789077aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120875676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2120875676
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3363557180
Short name T949
Test name
Test status
Simulation time 1461252377 ps
CPU time 7.7 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:40 PM PDT 24
Peak memory 222800 kb
Host smart-e542dab8-50a5-4d0f-8be8-e97841988b0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3363557180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3363557180
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.166180837
Short name T59
Test name
Test status
Simulation time 71883725 ps
CPU time 0.92 seconds
Started Jul 11 04:34:15 PM PDT 24
Finished Jul 11 04:34:39 PM PDT 24
Peak memory 208344 kb
Host smart-2015afd5-5bca-47ad-909f-cc79128b380e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166180837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.166180837
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1856153480
Short name T907
Test name
Test status
Simulation time 37308415049 ps
CPU time 30.27 seconds
Started Jul 11 04:34:12 PM PDT 24
Finished Jul 11 04:35:06 PM PDT 24
Peak memory 217424 kb
Host smart-baf0eddb-cb78-4955-9709-7e5e169cf800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856153480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1856153480
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.111522145
Short name T875
Test name
Test status
Simulation time 2815153814 ps
CPU time 8.8 seconds
Started Jul 11 04:34:12 PM PDT 24
Finished Jul 11 04:34:44 PM PDT 24
Peak memory 217380 kb
Host smart-f4b121a3-b22e-4d84-9358-5700e3dd615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111522145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.111522145
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1355322476
Short name T833
Test name
Test status
Simulation time 83781216 ps
CPU time 1.64 seconds
Started Jul 11 04:34:09 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 217288 kb
Host smart-24f948e9-1fc9-4fbe-a348-6422d9e23ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355322476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1355322476
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3353656481
Short name T598
Test name
Test status
Simulation time 45242994 ps
CPU time 0.71 seconds
Started Jul 11 04:34:09 PM PDT 24
Finished Jul 11 04:34:35 PM PDT 24
Peak memory 206944 kb
Host smart-120a2e8d-00d8-49b4-980a-65f638962f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353656481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3353656481
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3886389516
Short name T742
Test name
Test status
Simulation time 118397011 ps
CPU time 3.43 seconds
Started Jul 11 04:34:07 PM PDT 24
Finished Jul 11 04:34:36 PM PDT 24
Peak memory 233976 kb
Host smart-06c6dd5b-1461-494e-bc8b-28f891c100ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886389516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3886389516
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3501985759
Short name T60
Test name
Test status
Simulation time 22845879 ps
CPU time 0.71 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:10 PM PDT 24
Peak memory 206400 kb
Host smart-07b204ab-dfad-4431-8068-6fee27d1420d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501985759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
501985759
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3382728643
Short name T943
Test name
Test status
Simulation time 780263473 ps
CPU time 9.96 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:35 PM PDT 24
Peak memory 225424 kb
Host smart-b3e5ae9a-6596-4159-93d2-82890e2be2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382728643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3382728643
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.995863202
Short name T338
Test name
Test status
Simulation time 20119318 ps
CPU time 0.79 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:13 PM PDT 24
Peak memory 207368 kb
Host smart-e45b3c13-5841-45f4-a8a4-a8d4f1da0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995863202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.995863202
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2472653439
Short name T420
Test name
Test status
Simulation time 38334528991 ps
CPU time 316.09 seconds
Started Jul 11 04:31:53 PM PDT 24
Finished Jul 11 04:37:34 PM PDT 24
Peak memory 261016 kb
Host smart-c1c26309-1a61-4431-a3ba-17aa781c995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472653439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2472653439
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.730515464
Short name T164
Test name
Test status
Simulation time 198641820921 ps
CPU time 266.17 seconds
Started Jul 11 04:32:13 PM PDT 24
Finished Jul 11 04:37:11 PM PDT 24
Peak memory 254960 kb
Host smart-62552433-4f07-4a47-9600-b082d01b1a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730515464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
730515464
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1800523610
Short name T868
Test name
Test status
Simulation time 30785165707 ps
CPU time 29.43 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:55 PM PDT 24
Peak memory 241436 kb
Host smart-4e83a4a2-a540-4585-84fc-97793e8e9000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800523610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1800523610
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1433072968
Short name T785
Test name
Test status
Simulation time 16612545552 ps
CPU time 75.45 seconds
Started Jul 11 04:31:48 PM PDT 24
Finished Jul 11 04:33:28 PM PDT 24
Peak memory 250248 kb
Host smart-d99a6695-cf56-4407-8e1b-5ebcc89ac9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433072968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1433072968
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3482951629
Short name T589
Test name
Test status
Simulation time 505674156 ps
CPU time 6.24 seconds
Started Jul 11 04:31:37 PM PDT 24
Finished Jul 11 04:32:02 PM PDT 24
Peak memory 233644 kb
Host smart-0197d962-90d4-40b9-8688-c5490d8c5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482951629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3482951629
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.318159901
Short name T430
Test name
Test status
Simulation time 1398505708 ps
CPU time 16.6 seconds
Started Jul 11 04:31:53 PM PDT 24
Finished Jul 11 04:32:35 PM PDT 24
Peak memory 234852 kb
Host smart-e61e507b-49e7-4359-bb7b-95fc0e8f7ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318159901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.318159901
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2934070366
Short name T804
Test name
Test status
Simulation time 96169514 ps
CPU time 0.99 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:15 PM PDT 24
Peak memory 218896 kb
Host smart-ef662aea-7b7b-4987-9c12-ae012560e41d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934070366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2934070366
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.428170982
Short name T191
Test name
Test status
Simulation time 171585774 ps
CPU time 4.97 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:54 PM PDT 24
Peak memory 241120 kb
Host smart-e6b89a8c-a818-4cac-acc2-a6bc775b1359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428170982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
428170982
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1082307599
Short name T873
Test name
Test status
Simulation time 913255268 ps
CPU time 4.33 seconds
Started Jul 11 04:31:51 PM PDT 24
Finished Jul 11 04:32:18 PM PDT 24
Peak memory 233684 kb
Host smart-4dde47d5-6eef-43b6-be19-a403c88c04bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082307599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1082307599
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3407273070
Short name T462
Test name
Test status
Simulation time 1744658313 ps
CPU time 18.21 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:33:07 PM PDT 24
Peak memory 221368 kb
Host smart-da144652-4663-408c-aafc-2752a4b0cfde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407273070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3407273070
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.176347122
Short name T53
Test name
Test status
Simulation time 78167214805 ps
CPU time 424.7 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:39:47 PM PDT 24
Peak memory 267676 kb
Host smart-68eefdb0-06c1-4fd0-ae7c-f08353d6d9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176347122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.176347122
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.522129562
Short name T431
Test name
Test status
Simulation time 3191306892 ps
CPU time 13.2 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 217472 kb
Host smart-870de527-ea5d-441b-af6a-9c447e55b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522129562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.522129562
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.180267898
Short name T84
Test name
Test status
Simulation time 2157459610 ps
CPU time 3.8 seconds
Started Jul 11 04:31:36 PM PDT 24
Finished Jul 11 04:31:57 PM PDT 24
Peak memory 217352 kb
Host smart-5102c430-dede-41ca-ad57-34d5f74cbcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180267898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.180267898
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3327659685
Short name T322
Test name
Test status
Simulation time 1081727463 ps
CPU time 3.28 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:16 PM PDT 24
Peak memory 217592 kb
Host smart-2e4cd7c5-a7c3-40c4-a1c3-dcef2f4142a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327659685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3327659685
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.321172444
Short name T71
Test name
Test status
Simulation time 26447557 ps
CPU time 0.76 seconds
Started Jul 11 04:32:16 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 206868 kb
Host smart-a4da858b-6687-4240-80af-e21037453512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321172444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.321172444
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1710941376
Short name T688
Test name
Test status
Simulation time 3882958030 ps
CPU time 13.29 seconds
Started Jul 11 04:31:48 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 233824 kb
Host smart-d9cb49de-c017-4577-805a-289f428a2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710941376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1710941376
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.191843619
Short name T406
Test name
Test status
Simulation time 32455519 ps
CPU time 0.7 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:10 PM PDT 24
Peak memory 206376 kb
Host smart-8f132052-247a-4de9-9266-ab0bdeca37f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191843619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.191843619
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1135286290
Short name T8
Test name
Test status
Simulation time 962749485 ps
CPU time 9.19 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:29 PM PDT 24
Peak memory 225404 kb
Host smart-6cbdca36-9910-469a-bfa8-7871ce7e9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135286290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1135286290
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.129557920
Short name T5
Test name
Test status
Simulation time 25545255 ps
CPU time 0.75 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 207408 kb
Host smart-c35708fe-88cd-4323-8e3d-cb7b72f46ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129557920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.129557920
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1848909221
Short name T700
Test name
Test status
Simulation time 35559460161 ps
CPU time 77.54 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:33:20 PM PDT 24
Peak memory 251920 kb
Host smart-85d658b7-96d4-468a-929d-f9ab8dc7fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848909221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1848909221
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2151076156
Short name T137
Test name
Test status
Simulation time 58085770715 ps
CPU time 302.55 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:37:21 PM PDT 24
Peak memory 255836 kb
Host smart-efc93b99-5115-479f-9858-13b58c479bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151076156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2151076156
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.784977760
Short name T971
Test name
Test status
Simulation time 79363036699 ps
CPU time 179.75 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:35:04 PM PDT 24
Peak memory 258256 kb
Host smart-b09cb3aa-9194-4c85-b181-c64bafb7179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784977760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
784977760
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.678202457
Short name T281
Test name
Test status
Simulation time 6313873552 ps
CPU time 17.03 seconds
Started Jul 11 04:31:54 PM PDT 24
Finished Jul 11 04:32:36 PM PDT 24
Peak memory 241948 kb
Host smart-1b4a2597-cfad-4601-b4ff-094db023d118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678202457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.678202457
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4106129259
Short name T846
Test name
Test status
Simulation time 390342934 ps
CPU time 4.46 seconds
Started Jul 11 04:31:43 PM PDT 24
Finished Jul 11 04:32:08 PM PDT 24
Peak memory 233572 kb
Host smart-6ceec71a-720d-4f0a-9efc-a76852281d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106129259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4106129259
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1684181830
Short name T837
Test name
Test status
Simulation time 4960231093 ps
CPU time 20.97 seconds
Started Jul 11 04:31:45 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 239008 kb
Host smart-7eafd186-f6ed-4e1a-ba08-37e22ec05a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684181830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1684181830
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2540908919
Short name T655
Test name
Test status
Simulation time 289792040 ps
CPU time 1.12 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 217524 kb
Host smart-e4a7e349-2734-4449-8962-428f61b9295b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540908919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2540908919
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2623284100
Short name T796
Test name
Test status
Simulation time 3480305402 ps
CPU time 7.98 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:17 PM PDT 24
Peak memory 233844 kb
Host smart-a2a00858-7569-4e43-bb47-f615535284ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623284100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2623284100
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3070175678
Short name T522
Test name
Test status
Simulation time 67021531854 ps
CPU time 16.12 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:36 PM PDT 24
Peak memory 233732 kb
Host smart-dc5cd37b-fe5c-480e-b82b-5ff0f89e70a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070175678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3070175678
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.238359720
Short name T10
Test name
Test status
Simulation time 24612943293 ps
CPU time 13.32 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 223216 kb
Host smart-204c5c99-3abd-4978-baa2-3236c75c17d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=238359720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.238359720
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2525817490
Short name T1011
Test name
Test status
Simulation time 946790587 ps
CPU time 14.03 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 217220 kb
Host smart-074575ef-b12f-4412-8914-2e987ce6527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525817490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2525817490
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1989004715
Short name T554
Test name
Test status
Simulation time 730908825 ps
CPU time 4.99 seconds
Started Jul 11 04:31:54 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 217244 kb
Host smart-d5545081-6caa-4629-b00c-eedfe4cef43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989004715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1989004715
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2848241008
Short name T908
Test name
Test status
Simulation time 25441949 ps
CPU time 0.95 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 208840 kb
Host smart-ab51be0d-fdf2-4548-a4ea-04b138d3d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848241008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2848241008
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4181513785
Short name T615
Test name
Test status
Simulation time 56982262 ps
CPU time 0.85 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:15 PM PDT 24
Peak memory 206848 kb
Host smart-d82dba6b-aaff-4b02-8917-5623a335c1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181513785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4181513785
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.278968542
Short name T923
Test name
Test status
Simulation time 10188288678 ps
CPU time 3.98 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:32:25 PM PDT 24
Peak memory 233660 kb
Host smart-2628f18c-b1e6-4701-acc9-a995e6dd8536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278968542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.278968542
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3844452187
Short name T839
Test name
Test status
Simulation time 74611570 ps
CPU time 0.72 seconds
Started Jul 11 04:31:50 PM PDT 24
Finished Jul 11 04:32:13 PM PDT 24
Peak memory 205772 kb
Host smart-8a3b9937-539e-457b-b5eb-c39e9555475f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844452187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
844452187
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1939782742
Short name T871
Test name
Test status
Simulation time 245530843 ps
CPU time 2.69 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 225460 kb
Host smart-2b5269de-a98b-4f4c-91fc-f9891f0e22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939782742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1939782742
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1008874371
Short name T669
Test name
Test status
Simulation time 99063958 ps
CPU time 0.71 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 206344 kb
Host smart-b0cc7d0e-5f1e-41e7-89df-1173ed38cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008874371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1008874371
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.356619875
Short name T886
Test name
Test status
Simulation time 35056967629 ps
CPU time 234.89 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:36:16 PM PDT 24
Peak memory 254436 kb
Host smart-2ed14851-c650-41bb-a4c9-862b15a5521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356619875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.356619875
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2933728220
Short name T730
Test name
Test status
Simulation time 3127258055 ps
CPU time 20.73 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:40 PM PDT 24
Peak memory 251892 kb
Host smart-648d2f20-d3b6-4e9d-9cb3-fb2d9f2ae4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933728220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2933728220
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3328106113
Short name T143
Test name
Test status
Simulation time 3732191241 ps
CPU time 44.42 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 251612 kb
Host smart-564fe64a-0437-4cd9-a3e8-e14fcfa9c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328106113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3328106113
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1323808682
Short name T893
Test name
Test status
Simulation time 37153231436 ps
CPU time 147.15 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:34:55 PM PDT 24
Peak memory 250168 kb
Host smart-750d179b-6a1d-4567-827e-aada96746e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323808682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1323808682
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.295128269
Short name T654
Test name
Test status
Simulation time 383924492 ps
CPU time 4.74 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:20 PM PDT 24
Peak memory 225408 kb
Host smart-9f2167f5-4105-4f83-81e0-ab4512bd4429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295128269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.295128269
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3747136849
Short name T185
Test name
Test status
Simulation time 8062854198 ps
CPU time 22.83 seconds
Started Jul 11 04:31:51 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 225516 kb
Host smart-44e2d72b-c599-4f47-8ff7-dad8f352935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747136849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3747136849
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.799915479
Short name T662
Test name
Test status
Simulation time 15181267 ps
CPU time 1.01 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:32:29 PM PDT 24
Peak memory 217520 kb
Host smart-8b070b3a-4b24-4712-a9e8-fba170dbad9a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799915479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.799915479
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3885484843
Short name T421
Test name
Test status
Simulation time 3674138513 ps
CPU time 12.76 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:32:40 PM PDT 24
Peak memory 232964 kb
Host smart-569edf11-e195-469e-a913-5903167976ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885484843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3885484843
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4263213573
Short name T571
Test name
Test status
Simulation time 6003012654 ps
CPU time 11.45 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:32:39 PM PDT 24
Peak memory 233708 kb
Host smart-c9435197-808e-4833-b894-30b01f64c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263213573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4263213573
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3830743337
Short name T795
Test name
Test status
Simulation time 1161531832 ps
CPU time 14.93 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:41 PM PDT 24
Peak memory 220172 kb
Host smart-26ef7eb3-1fe4-4f86-8c1c-276f88ad0424
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830743337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3830743337
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2483002637
Short name T17
Test name
Test status
Simulation time 245183851 ps
CPU time 1.14 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 216764 kb
Host smart-9f669940-512b-42b3-bd23-e72a35f0bb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483002637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2483002637
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2467056597
Short name T961
Test name
Test status
Simulation time 4817990485 ps
CPU time 24.6 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:50 PM PDT 24
Peak memory 217448 kb
Host smart-96ad7eef-8806-4688-83bf-efdaf0673114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467056597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2467056597
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3454271888
Short name T362
Test name
Test status
Simulation time 425923548 ps
CPU time 1.52 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 208828 kb
Host smart-730754fd-4f45-42b0-98e3-60caf4c617af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454271888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3454271888
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2421247760
Short name T317
Test name
Test status
Simulation time 46275468 ps
CPU time 0.86 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:26 PM PDT 24
Peak memory 207616 kb
Host smart-23bfa5db-85b6-462c-9dc1-8ba266932291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421247760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2421247760
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3614651726
Short name T573
Test name
Test status
Simulation time 36026117 ps
CPU time 0.85 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 207840 kb
Host smart-4b284f5e-460a-45a3-86e4-6e31453f0cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614651726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3614651726
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2949769585
Short name T1
Test name
Test status
Simulation time 9336720190 ps
CPU time 11.63 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:12 PM PDT 24
Peak memory 234284 kb
Host smart-c86438ae-0230-4507-9684-99725327e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949769585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2949769585
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.326307933
Short name T769
Test name
Test status
Simulation time 14255843 ps
CPU time 0.69 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:34 PM PDT 24
Peak memory 205780 kb
Host smart-803fa728-03f0-40da-8422-6c1617073d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326307933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.326307933
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.537036401
Short name T648
Test name
Test status
Simulation time 160848651 ps
CPU time 2.43 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:22 PM PDT 24
Peak memory 233624 kb
Host smart-3cd322f3-d8a1-495a-9712-9c7b83ab307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537036401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.537036401
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3698015013
Short name T28
Test name
Test status
Simulation time 18210247 ps
CPU time 0.74 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 206372 kb
Host smart-a56fec72-2ab2-404b-889f-e73326c05a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698015013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3698015013
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1180942024
Short name T187
Test name
Test status
Simulation time 18146637584 ps
CPU time 102.49 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:34:10 PM PDT 24
Peak memory 265032 kb
Host smart-4f41e1d4-fed0-47b3-8eb1-032ed1fe9d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180942024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1180942024
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1041255596
Short name T525
Test name
Test status
Simulation time 4631143511 ps
CPU time 20.62 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 218560 kb
Host smart-56a15bb5-379c-4182-839b-08a2b94d0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041255596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1041255596
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2053156311
Short name T810
Test name
Test status
Simulation time 1473161584 ps
CPU time 20.48 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:52 PM PDT 24
Peak memory 240004 kb
Host smart-976d7d25-476a-4066-8ef6-c8d34d82232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053156311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2053156311
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.270069129
Short name T147
Test name
Test status
Simulation time 438837977 ps
CPU time 6.96 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:32:49 PM PDT 24
Peak memory 225408 kb
Host smart-0b72e7a3-cd48-4f24-9b23-f35e9cb175d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270069129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.270069129
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2816255091
Short name T611
Test name
Test status
Simulation time 13323644635 ps
CPU time 87.33 seconds
Started Jul 11 04:31:53 PM PDT 24
Finished Jul 11 04:33:45 PM PDT 24
Peak memory 254340 kb
Host smart-b0ddd64d-e4b4-4a9c-bab4-c4af2479481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816255091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2816255091
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4067738591
Short name T566
Test name
Test status
Simulation time 171877495 ps
CPU time 5.4 seconds
Started Jul 11 04:32:00 PM PDT 24
Finished Jul 11 04:32:31 PM PDT 24
Peak memory 225464 kb
Host smart-94457fa3-db09-40f9-a5f4-4e12b5b3eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067738591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4067738591
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4130126899
Short name T404
Test name
Test status
Simulation time 12864623304 ps
CPU time 19.05 seconds
Started Jul 11 04:31:42 PM PDT 24
Finished Jul 11 04:32:21 PM PDT 24
Peak memory 241844 kb
Host smart-2e441a5f-7654-4cdc-b67f-73df30f47856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130126899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4130126899
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.640386526
Short name T910
Test name
Test status
Simulation time 20866473 ps
CPU time 1.02 seconds
Started Jul 11 04:31:49 PM PDT 24
Finished Jul 11 04:32:14 PM PDT 24
Peak memory 217524 kb
Host smart-ff52fb65-7320-4a3f-8326-24510fbda12b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640386526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.640386526
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3676298563
Short name T95
Test name
Test status
Simulation time 1339449141 ps
CPU time 14.01 seconds
Started Jul 11 04:31:44 PM PDT 24
Finished Jul 11 04:32:18 PM PDT 24
Peak memory 249956 kb
Host smart-c79da271-36f7-4b63-a363-6139644cf35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676298563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3676298563
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3048346799
Short name T558
Test name
Test status
Simulation time 196330335 ps
CPU time 2.55 seconds
Started Jul 11 04:32:08 PM PDT 24
Finished Jul 11 04:32:42 PM PDT 24
Peak memory 233692 kb
Host smart-f77a0924-e089-4250-aacc-d1c19e178980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048346799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3048346799
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3514725142
Short name T145
Test name
Test status
Simulation time 141102399 ps
CPU time 3.82 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 224044 kb
Host smart-e3f75c7f-c3a9-4613-abee-c6cc6e246272
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514725142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3514725142
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1355931825
Short name T18
Test name
Test status
Simulation time 4771954245 ps
CPU time 42.5 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 234036 kb
Host smart-662e6943-a2c6-4fb7-90a4-c072bea464d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355931825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1355931825
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4280330221
Short name T865
Test name
Test status
Simulation time 3871298101 ps
CPU time 20.1 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 217732 kb
Host smart-b4fcb3e2-8c8a-4e27-a853-85dc05da1814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280330221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4280330221
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2035413949
Short name T349
Test name
Test status
Simulation time 323368834 ps
CPU time 1.82 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 217024 kb
Host smart-45147ca8-a65e-486c-90c4-23a33f2b5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035413949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2035413949
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3363225798
Short name T726
Test name
Test status
Simulation time 82686968 ps
CPU time 1.13 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:32:24 PM PDT 24
Peak memory 208496 kb
Host smart-21a83920-9b3c-402c-9333-9bac2221a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363225798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3363225798
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1636411962
Short name T652
Test name
Test status
Simulation time 52453662 ps
CPU time 0.65 seconds
Started Jul 11 04:31:56 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 206412 kb
Host smart-bc6dc76e-40ce-48d6-9017-3a040a6c77c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636411962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1636411962
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3600243358
Short name T568
Test name
Test status
Simulation time 324363449 ps
CPU time 2.89 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:32:31 PM PDT 24
Peak memory 233656 kb
Host smart-038fa8aa-619e-4c29-81c4-c6c3e161a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600243358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3600243358
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1530077088
Short name T991
Test name
Test status
Simulation time 43713801 ps
CPU time 0.73 seconds
Started Jul 11 04:32:07 PM PDT 24
Finished Jul 11 04:32:37 PM PDT 24
Peak memory 206328 kb
Host smart-150cc88d-15fd-47a2-856d-d11208e8f276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530077088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
530077088
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.570750840
Short name T46
Test name
Test status
Simulation time 1264227577 ps
CPU time 4.15 seconds
Started Jul 11 04:32:02 PM PDT 24
Finished Jul 11 04:32:32 PM PDT 24
Peak memory 233744 kb
Host smart-5749f4bb-e183-4377-bf7c-3955f6ee78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570750840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.570750840
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.44985363
Short name T936
Test name
Test status
Simulation time 32683546 ps
CPU time 0.76 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:32:28 PM PDT 24
Peak memory 206632 kb
Host smart-61cff102-0486-4da3-a494-9e8620c8c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44985363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.44985363
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.288783249
Short name T911
Test name
Test status
Simulation time 29168511554 ps
CPU time 98.88 seconds
Started Jul 11 04:31:58 PM PDT 24
Finished Jul 11 04:34:02 PM PDT 24
Peak memory 242020 kb
Host smart-8ed9ca2f-6eed-44b1-a6f4-a3e7ecbc628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288783249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.288783249
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1817021792
Short name T33
Test name
Test status
Simulation time 54453475248 ps
CPU time 437.56 seconds
Started Jul 11 04:32:06 PM PDT 24
Finished Jul 11 04:39:54 PM PDT 24
Peak memory 267600 kb
Host smart-e2fc8da8-fe87-4b94-9021-3bfa986ab1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817021792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1817021792
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3958523385
Short name T626
Test name
Test status
Simulation time 22612118384 ps
CPU time 87.25 seconds
Started Jul 11 04:31:52 PM PDT 24
Finished Jul 11 04:33:43 PM PDT 24
Peak memory 250528 kb
Host smart-2b4661a1-acf1-41e7-a3d1-483f1e74a15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958523385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3958523385
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3335035182
Short name T658
Test name
Test status
Simulation time 55085881 ps
CPU time 2.93 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:36 PM PDT 24
Peak memory 233568 kb
Host smart-194c5d16-b20e-4010-9512-50651ca68a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335035182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3335035182
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1684618875
Short name T516
Test name
Test status
Simulation time 28649630314 ps
CPU time 105.17 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:34:18 PM PDT 24
Peak memory 250844 kb
Host smart-a8aa1d53-29a7-48c5-8e2a-e77e09e296d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684618875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1684618875
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2017003764
Short name T327
Test name
Test status
Simulation time 313925777 ps
CPU time 4.08 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 225468 kb
Host smart-76bf294d-9560-4388-880a-95e4efa90599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017003764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2017003764
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.719186698
Short name T794
Test name
Test status
Simulation time 467459540 ps
CPU time 9.16 seconds
Started Jul 11 04:32:04 PM PDT 24
Finished Jul 11 04:32:41 PM PDT 24
Peak memory 233644 kb
Host smart-618ca2ca-1b43-412d-80ee-831eee5f8c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719186698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.719186698
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1246718972
Short name T537
Test name
Test status
Simulation time 26001771 ps
CPU time 0.97 seconds
Started Jul 11 04:32:01 PM PDT 24
Finished Jul 11 04:32:29 PM PDT 24
Peak memory 218844 kb
Host smart-3a61eef9-ef46-434a-991e-f34da840dc7e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246718972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1246718972
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.272286829
Short name T918
Test name
Test status
Simulation time 8162896274 ps
CPU time 15.24 seconds
Started Jul 11 04:32:03 PM PDT 24
Finished Jul 11 04:32:47 PM PDT 24
Peak memory 241608 kb
Host smart-2881fdcc-3293-4771-8079-09a5025ae9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272286829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
272286829
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3801696703
Short name T976
Test name
Test status
Simulation time 66877452 ps
CPU time 2.58 seconds
Started Jul 11 04:32:09 PM PDT 24
Finished Jul 11 04:32:42 PM PDT 24
Peak memory 233592 kb
Host smart-5aa07323-f24f-4ea8-b277-d392772b60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801696703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3801696703
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.731250779
Short name T76
Test name
Test status
Simulation time 2344647443 ps
CPU time 11.48 seconds
Started Jul 11 04:31:55 PM PDT 24
Finished Jul 11 04:32:31 PM PDT 24
Peak memory 221028 kb
Host smart-525dc935-3a0a-4e3e-807d-60eef0fa865a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=731250779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.731250779
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1958244454
Short name T624
Test name
Test status
Simulation time 176689393482 ps
CPU time 371.69 seconds
Started Jul 11 04:31:54 PM PDT 24
Finished Jul 11 04:38:30 PM PDT 24
Peak memory 272868 kb
Host smart-d46e4bcd-f7b6-4875-8da0-b84b747832a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958244454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1958244454
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.716436261
Short name T403
Test name
Test status
Simulation time 14238553155 ps
CPU time 31.72 seconds
Started Jul 11 04:31:47 PM PDT 24
Finished Jul 11 04:32:39 PM PDT 24
Peak memory 217356 kb
Host smart-953bbf9f-91f1-4f21-95bb-b3446ad82cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716436261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.716436261
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.878534227
Short name T927
Test name
Test status
Simulation time 1387587301 ps
CPU time 7.18 seconds
Started Jul 11 04:32:05 PM PDT 24
Finished Jul 11 04:32:41 PM PDT 24
Peak memory 217284 kb
Host smart-3a6fc53c-e4de-4f7b-b230-18a9cc3a9fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878534227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.878534227
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3023394164
Short name T345
Test name
Test status
Simulation time 58896394 ps
CPU time 1.43 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:27 PM PDT 24
Peak memory 217252 kb
Host smart-2988e3f8-4db1-4daa-aca2-c4fc02d8ff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023394164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3023394164
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3873898647
Short name T1008
Test name
Test status
Simulation time 90885646 ps
CPU time 0.77 seconds
Started Jul 11 04:31:57 PM PDT 24
Finished Jul 11 04:32:23 PM PDT 24
Peak memory 206852 kb
Host smart-0c77dedc-1a78-4fd8-bd9b-bab4a6587871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873898647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3873898647
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2222908169
Short name T906
Test name
Test status
Simulation time 11680700650 ps
CPU time 12.53 seconds
Started Jul 11 04:31:59 PM PDT 24
Finished Jul 11 04:32:38 PM PDT 24
Peak memory 233864 kb
Host smart-ccd5dfd3-cd2d-4402-bb06-18756efb78d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222908169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2222908169
Directory /workspace/9.spi_device_upload/latest
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