Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3070243	1			T1	1		T2	1		T3	715
all_values[1]	3070243	1			T1	1		T2	1		T3	715
all_values[2]	3070243	1			T1	1		T2	1		T3	715
all_values[3]	3070243	1			T1	1		T2	1		T3	715
all_values[4]	3070243	1			T1	1		T2	1		T3	715
all_values[5]	3070243	1			T1	1		T2	1		T3	715
all_values[6]	3070243	1			T1	1		T2	1		T3	715
all_values[7]	3070243	1			T1	1		T2	1		T3	715

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23409490

1

T1

8

T2

8

T3

5720

auto[1]

1152454

1

T12

49

T14

36

T15

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24531855

1

T1

8

T2

8

T3

5720

auto[1]

30089

1

T10

271

T12

384

T31

266

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2889031	1			T1	1		T2	1		T3	715
all_values[0]	auto[0]	auto[1]	13852	1			T10	103		T12	186		T31	109
all_values[0]	auto[1]	auto[0]	166491	1			T12	3		T14	3		T15	10
all_values[0]	auto[1]	auto[1]	869	1			T12	1		T14	1		T15	5
all_values[1]	auto[0]	auto[0]	2763064	1			T1	1		T2	1		T3	715
all_values[1]	auto[0]	auto[1]	8807	1			T10	103		T12	123		T31	104
all_values[1]	auto[1]	auto[0]	297596	1			T12	4		T14	1		T15	6
all_values[1]	auto[1]	auto[1]	776	1			T12	3		T14	1		T15	5
all_values[2]	auto[0]	auto[0]	2911100	1			T1	1		T2	1		T3	715
all_values[2]	auto[0]	auto[1]	3583	1			T10	65		T12	43		T31	53
all_values[2]	auto[1]	auto[0]	155216	1			T12	3		T14	3		T15	9
all_values[2]	auto[1]	auto[1]	344	1			T12	2		T14	3		T15	2
all_values[3]	auto[0]	auto[0]	3031354	1			T1	1		T2	1		T3	715
all_values[3]	auto[0]	auto[1]	177	1			T15	3		T16	7		T17	2
all_values[3]	auto[1]	auto[0]	38512	1			T12	7		T14	5		T15	8
all_values[3]	auto[1]	auto[1]	200	1			T12	3		T14	1		T15	3
all_values[4]	auto[0]	auto[0]	2901597	1			T1	1		T2	1		T3	715
all_values[4]	auto[0]	auto[1]	189	1			T12	2		T15	3		T16	8
all_values[4]	auto[1]	auto[0]	168245	1			T12	4		T14	6		T15	8
all_values[4]	auto[1]	auto[1]	212	1			T12	5		T14	1		T15	7
all_values[5]	auto[0]	auto[0]	3001595	1			T1	1		T2	1		T3	715
all_values[5]	auto[0]	auto[1]	169	1			T12	4		T14	2		T15	5
all_values[5]	auto[1]	auto[0]	68310	1			T14	1		T15	4		T16	6
all_values[5]	auto[1]	auto[1]	169	1			T12	3		T14	1		T15	1
all_values[6]	auto[0]	auto[0]	2948548	1			T1	1		T2	1		T3	715
all_values[6]	auto[0]	auto[1]	186	1			T12	3		T14	2		T15	5
all_values[6]	auto[1]	auto[0]	121340	1			T12	7		T14	5		T15	4
all_values[6]	auto[1]	auto[1]	169	1			T14	2		T16	7		T17	3
all_values[7]	auto[0]	auto[0]	2936032	1			T1	1		T2	1		T3	715
all_values[7]	auto[0]	auto[1]	206	1			T12	5		T14	5		T15	2
all_values[7]	auto[1]	auto[0]	133824	1			T12	3		T15	7		T16	3
all_values[7]	auto[1]	auto[1]	181	1			T12	1		T14	2		T15	3