Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37349	1			T1	4		T3	8		T5	6
auto[SpiFlashAddrCfg]	8263	1			T1	2		T2	2		T3	4
auto[SpiFlashAddr3b]	9591	1			T1	6		T3	2		T6	2
auto[SpiFlashAddr4b]	8026	1			T1	4		T6	2		T8	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35701

1

T3

14

T5

6

T8

16

auto[1]

27528

1

T1

16

T2

2

T6

6

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32998

1

T1

8

T2

2

T3

14

auto[1]

30231

1

T1

8

T5

6

T6

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42303	1			T1	6		T3	8		T5	6
values[1]	1151	1			T10	1		T12	7		T23	6
values[2]	1523	1			T1	2		T10	6		T12	14
values[3]	1610	1			T8	2		T10	9		T11	2
values[4]	1525	1			T3	2		T10	17		T12	7
values[5]	1617	1			T10	4		T11	2		T12	15
values[6]	1541	1			T3	2		T10	5		T11	2
values[7]	1583	1			T1	2		T3	2		T10	3
values[8]	10376	1			T1	6		T2	2		T6	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32386

1

T1

16

T2

2

T3

14

auto[1]

30843

1

T10

339

T23

217

T41

200

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59749

1

T1

14

T2

2

T3

14

write

3480

1

T1

2

T8

2

T10

21

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20077

1

T1

10

T2

2

T3

6

valids[0x1]

43152

1

T1

6

T3

8

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1696	1			T6	2		T10	10		T12	9
internal_process_ops[0x5a]	1654	1			T8	2		T10	13		T12	7
internal_process_ops[0x05]	22953	1			T3	2		T10	107		T12	29
internal_process_ops[0x35]	1656	1			T1	4		T3	2		T5	6
internal_process_ops[0x15]	1634	1			T10	5		T12	8		T23	8
internal_process_ops[0x03]	1155	1			T8	2		T10	6		T11	2
internal_process_ops[0x0b]	1140	1			T3	2		T8	2		T10	4
internal_process_ops[0x3b]	1082	1			T8	2		T10	2		T12	14
internal_process_ops[0x6b]	1052	1			T1	2		T10	4		T12	7
internal_process_ops[0xbb]	1071	1			T3	2		T10	4		T11	2
internal_process_ops[0xeb]	1102	1			T1	2		T8	6		T10	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61485

1

T1

14

T2

2

T3

14

auto[1]

1744

1

T1

2

T10

9

T12

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60586

1

T1

16

T2

2

T3

14

auto[1]

2643

1

T10

20

T12

9

T23

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10967

1

T3

8

T5

6

T11

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6796

1

T1

4

T6

2

T12

39

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2245

1

T3

4

T11

2

T12

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1925

1

T1

2

T2

2

T12

34

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2518

1

T3

2

T8

10

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2269

1

T1

4

T6

2

T12

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2068

1

T8

4

T11

2

T12

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1909

1

T1

4

T6

2

T12

26

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

130

1

T8

2

T12

3

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T26

2

T40

2

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T46

2

T48

1

T18

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T12

3

T26

2

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

112

1

T12

1

T26

2

T92

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T12

1

T26

2

T40

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

100

1

T31

1

T47

2

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T46

2

T44

1

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T12

2

T26

1

T40

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T12

3

T26

1

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

98

1

T40

1

T46

2

T17

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T1

2

T31

1

T46

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T12

7

T26

3

T48

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

126

1

T12

1

T26

1

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T12

4

T26

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T12

2

T31

1

T46

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10836

1

T10

124

T23

80

T41

51

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7891

1

T10

63

T23

50

T41

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1673

1

T10

15

T23

10

T41

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1559

1

T10

20

T23

9

T41

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1960

1

T10

21

T23

27

T41

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1982

1

T10

28

T23

21

T41

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1661

1

T10

24

T23

5

T41

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1490

1

T10

23

T23

8

T41

14

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

117

1

T41

5

T64

1

T174

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T41

3

T64

1

T96

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

110

1

T10

1

T41

2

T174

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T10

3

T64

1

T174

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T64

1

T96

3

T175

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

94

1

T41

1

T64

1

T174

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

119

1

T23

2

T64

2

T96

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

126

1

T10

3

T41

1

T96

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

141

1

T10

4

T23

1

T41

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T64

2

T174

3

T20

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

109

1

T10

1

T41

2

T64

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T10

2

T41

1

T64

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T10

3

T23

1

T41

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

152

1

T10

1

T64

2

T174

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

121

1

T10

3

T23

3

T41

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T174

1

T79

5

T17

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3818	1			T3	4		T12	56		T26	44
auto[0]	values[0]	valids[0x1]	16952	1			T1	6		T3	4		T5	6
auto[0]	values[1]	valids[0x1]	585	1			T12	7		T26	2		T40	1
auto[0]	values[2]	valids[0x0]	505	1			T1	2		T12	7		T26	8
auto[0]	values[2]	valids[0x1]	290	1			T12	7		T26	3		T46	2
auto[0]	values[3]	valids[0x0]	571	1			T8	2		T12	10		T26	5
auto[0]	values[3]	valids[0x1]	356	1			T11	2		T12	1		T26	4
auto[0]	values[4]	valids[0x0]	602	1			T3	2		T12	7		T26	7
auto[0]	values[4]	valids[0x1]	293	1			T26	3		T29	2		T91	4
auto[0]	values[5]	valids[0x0]	607	1			T11	2		T12	12		T26	4
auto[0]	values[5]	valids[0x1]	301	1			T12	3		T26	2		T40	2
auto[0]	values[6]	valids[0x0]	506	1			T12	3		T26	6		T40	1
auto[0]	values[6]	valids[0x1]	357	1			T3	2		T11	2		T12	4
auto[0]	values[7]	valids[0x0]	598	1			T1	2		T12	5		T26	2
auto[0]	values[7]	valids[0x1]	314	1			T3	2		T12	3		T26	2
auto[0]	values[8]	valids[0x0]	3618	1			T1	6		T2	2		T8	6
auto[0]	values[8]	valids[0x1]	2113	1			T6	2		T8	6		T12	27
auto[1]	values[0]	valids[0x0]	4143	1			T10	47		T23	33		T41	38
auto[1]	values[0]	valids[0x1]	17390	1			T10	185		T23	109		T41	69
auto[1]	values[1]	valids[0x1]	566	1			T10	1		T23	6		T41	7
auto[1]	values[2]	valids[0x0]	401	1			T10	1		T23	5		T41	5
auto[1]	values[2]	valids[0x1]	327	1			T10	5		T23	2		T41	1
auto[1]	values[3]	valids[0x0]	390	1			T10	1		T23	3		T41	5
auto[1]	values[3]	valids[0x1]	293	1			T10	8		T23	1		T41	2
auto[1]	values[4]	valids[0x0]	362	1			T10	12		T23	3		T41	5
auto[1]	values[4]	valids[0x1]	268	1			T10	5		T23	1		T41	8
auto[1]	values[5]	valids[0x0]	435	1			T10	3		T23	3		T41	5
auto[1]	values[5]	valids[0x1]	274	1			T10	1		T23	3		T41	2
auto[1]	values[6]	valids[0x0]	422	1			T10	3		T23	2		T41	8
auto[1]	values[6]	valids[0x1]	256	1			T10	2		T23	4		T41	1
auto[1]	values[7]	valids[0x0]	366	1			T10	1		T23	2		T41	3
auto[1]	values[7]	valids[0x1]	305	1			T10	2		T23	1		T41	2
auto[1]	values[8]	valids[0x0]	2733	1			T10	33		T23	21		T41	18
auto[1]	values[8]	valids[0x1]	1912	1			T10	29		T23	18		T41	21