Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3461826

1

T1

1

T2

1

T3

5117

auto[1]

33100

1

T10

99

T12

20

T23

77

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911528

1

T1

1

T2

1

T3

1

auto[1]

2583398

1

T3

5116

T10

6153

T12

14940

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	687297	1			T1	1		T2	1		T3	5117
auto[524288:1048575]	408706	1			T10	2014		T12	17		T23	523
auto[1048576:1572863]	358947	1			T5	26		T10	20		T12	300
auto[1572864:2097151]	409613	1			T10	2507		T12	1158		T23	6
auto[2097152:2621439]	400382	1			T5	2374		T10	1010		T12	2527
auto[2621440:3145727]	413620	1			T5	837		T10	8		T12	2380
auto[3145728:3670015]	443204	1			T5	2180		T10	264		T12	2653
auto[3670016:4194303]	373157	1			T5	2437		T10	281		T12	2855

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2616356

1

T1

1

T2

1

T3

5117

auto[1]

878570

1

T5

7778

T10

18

T23

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3036962

1

T1

1

T2

1

T3

5117

auto[1]

457964

1

T10

341

T12

24

T23

2599

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	195380	1			T1	1		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	431144	1			T3	5116		T10	129		T12	3118
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	133000	1			T10	17		T12	4		T23	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	223126	1			T10	1964		T12	5		T23	520
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	98503	1			T5	26		T10	6		T12	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	204942	1			T10	4		T12	294		T23	772
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	106389	1			T10	9		T12	5		T23	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	243876	1			T10	2475		T12	1152		T23	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	81061	1			T5	2374		T10	8		T12	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	254299	1			T10	647		T12	2509		T26	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	92762	1			T5	837		T10	4		T12	12
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	235694	1			T10	2		T12	2367		T23	132
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	112993	1			T5	2180		T10	7		T12	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	267625	1			T10	257		T12	2651		T23	900
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	74743	1			T5	2437		T10	7		T12	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	253327	1			T10	263		T12	2826		T23	834
auto[0]	auto[1]	auto[0:524287]	auto[0]	886	1			T10	2		T12	4		T23	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	54547	1			T23	2334		T26	2758		T40	128
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1837	1			T10	1		T12	4		T23	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46714	1			T12	4		T26	325		T174	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	512	1			T10	1		T23	1		T31	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51316	1			T26	770		T64	768		T174	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3149	1			T10	2		T12	1		T23	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51828	1			T10	1		T26	60		T40	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1572	1			T12	2		T26	1		T41	32
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60179	1			T10	332		T41	768		T47	768
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2777	1			T12	1		T40	2		T64	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	78280	1			T26	256		T174	256		T79	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1020	1			T64	5		T96	38		T44	25
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56879	1			T44	256		T17	372		T18	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	617	1			T12	2		T23	2		T41	9
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40849	1			T12	3		T23	256		T31	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	552	1			T10	1		T26	1		T41	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	4002	1			T10	1		T26	18		T31	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	556	1			T10	6		T26	3		T41	9
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3003	1			T10	26		T26	81		T174	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	377	1			T10	4		T26	1		T40	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2919	1			T10	5		T26	8		T40	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	446	1			T10	1		T26	1		T40	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3097	1			T10	17		T40	32		T41	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	373	1			T10	2		T12	3		T26	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2344	1			T10	21		T12	3		T26	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	429	1			T10	2		T23	4		T40	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3251	1			T23	18		T40	27		T31	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	477	1			T23	3		T26	2		T40	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3533	1			T23	40		T26	9		T40	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	408	1			T10	3		T12	5		T23	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2331	1			T10	8		T12	6		T23	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	72	1			T26	3		T47	1		T79	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	714	1			T26	67		T47	22		T79	47
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	103	1			T209	1		T161	2		T185	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	367	1			T161	23		T50	10		T231	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	73	1			T64	9		T175	6		T227	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	305	1			T175	26		T227	29		T209	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	94	1			T10	1		T40	1		T41	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	734	1			T10	1		T40	30		T41	240
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	96	1			T41	4		T96	6		T79	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	458	1			T79	53		T48	8		T22	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	102	1			T96	7		T175	7		T19	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	325	1			T19	41		T22	1		T201	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T17	2		T19	2		T209	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	599	1			T17	10		T19	35		T209	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	91	1			T12	1		T41	2		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	791	1			T12	2		T31	4		T16	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2138573	1			T1	1		T2	1		T3	5117
auto[0]	auto[0]	auto[1]	870291	1			T5	7778		T10	7		T23	4
auto[0]	auto[1]	auto[0]	445385	1			T10	339		T12	21		T23	2599
auto[0]	auto[1]	auto[1]	7577	1			T26	1		T79	1		T48	1
auto[1]	auto[0]	auto[0]	27522	1			T10	87		T12	17		T23	74
auto[1]	auto[0]	auto[1]	576	1			T10	10		T23	3		T26	5
auto[1]	auto[1]	auto[0]	4876	1			T10	1		T12	3		T26	70
auto[1]	auto[1]	auto[1]	126	1			T10	1		T41	3		T96	4