Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3070243	1			T1	1		T2	1		T3	715
all_pins[1]	3070243	1			T1	1		T2	1		T3	715
all_pins[2]	3070243	1			T1	1		T2	1		T3	715
all_pins[3]	3070243	1			T1	1		T2	1		T3	715
all_pins[4]	3070243	1			T1	1		T2	1		T3	715
all_pins[5]	3070243	1			T1	1		T2	1		T3	715
all_pins[6]	3070243	1			T1	1		T2	1		T3	715
all_pins[7]	3070243	1			T1	1		T2	1		T3	715

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24437088	1			T1	8		T2	8		T3	5720
values[0x1]	124856	1			T12	18		T14	12		T15	26
transitions[0x0=>0x1]	123977	1			T12	13		T14	9		T15	17
transitions[0x1=>0x0]	123989	1			T12	13		T14	9		T15	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3069294	1			T1	1		T2	1		T3	715
all_pins[0]	values[0x1]	949	1			T12	1		T14	1		T15	5
all_pins[0]	transitions[0x0=>0x1]	513	1			T12	1		T14	1		T15	2
all_pins[0]	transitions[0x1=>0x0]	403	1			T12	3		T14	1		T15	2
all_pins[1]	values[0x0]	3069404	1			T1	1		T2	1		T3	715
all_pins[1]	values[0x1]	839	1			T12	3		T14	1		T15	5
all_pins[1]	transitions[0x0=>0x1]	654	1			T12	3		T15	4		T16	5
all_pins[1]	transitions[0x1=>0x0]	170	1			T12	2		T14	2		T15	1
all_pins[2]	values[0x0]	3069888	1			T1	1		T2	1		T3	715
all_pins[2]	values[0x1]	355	1			T12	2		T14	3		T15	2
all_pins[2]	transitions[0x0=>0x1]	311	1			T12	2		T14	3		T15	2
all_pins[2]	transitions[0x1=>0x0]	156	1			T12	3		T14	1		T15	3
all_pins[3]	values[0x0]	3070043	1			T1	1		T2	1		T3	715
all_pins[3]	values[0x1]	200	1			T12	3		T14	1		T15	3
all_pins[3]	transitions[0x0=>0x1]	145	1			T12	1		T16	4		T17	2
all_pins[3]	transitions[0x1=>0x0]	157	1			T12	3		T15	4		T16	4
all_pins[4]	values[0x0]	3070031	1			T1	1		T2	1		T3	715
all_pins[4]	values[0x1]	212	1			T12	5		T14	1		T15	7
all_pins[4]	transitions[0x0=>0x1]	176	1			T12	3		T14	1		T15	6
all_pins[4]	transitions[0x1=>0x0]	999	1			T12	1		T14	1		T16	5
all_pins[5]	values[0x0]	3069208	1			T1	1		T2	1		T3	715
all_pins[5]	values[0x1]	1035	1			T12	3		T14	1		T15	1
all_pins[5]	transitions[0x0=>0x1]	1002	1			T12	3		T14	1		T15	1
all_pins[5]	transitions[0x1=>0x0]	121052	1			T14	2		T16	6		T17	3
all_pins[6]	values[0x0]	2949158	1			T1	1		T2	1		T3	715
all_pins[6]	values[0x1]	121085	1			T14	2		T16	7		T17	3
all_pins[6]	transitions[0x0=>0x1]	121046	1			T14	2		T16	4		T17	3
all_pins[6]	transitions[0x1=>0x0]	142	1			T12	1		T14	2		T15	3
all_pins[7]	values[0x0]	3070062	1			T1	1		T2	1		T3	715
all_pins[7]	values[0x1]	181	1			T12	1		T14	2		T15	3
all_pins[7]	transitions[0x0=>0x1]	130	1			T14	1		T15	2		T16	4
all_pins[7]	transitions[0x1=>0x0]	910	1			T15	4		T16	5		T17	5