Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18686

1

T3

14

T5

6

T8

16

auto[1]

13700

1

T1

16

T2

2

T6

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4247	1			T8	16		T12	20		T26	96
values[1]	3774	1			T6	6		T12	20		T26	30
values[2]	3944	1			T1	16		T3	14		T5	6
values[3]	4037	1			T12	40		T26	62		T239	14
values[4]	4359	1			T12	66		T26	25		T31	20
values[5]	4038	1			T12	20		T26	113		T92	16
values[6]	4216	1			T12	46		T91	10		T40	28
values[7]	3771	1			T2	2		T12	48		T26	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4093	1			T8	16		T12	20		T26	84
values[1]	4198	1			T2	2		T40	20		T97	8
values[2]	3409	1			T12	20		T26	116		T40	76
values[3]	4521	1			T12	48		T26	20		T27	4
values[4]	4043	1			T5	6		T12	25		T26	64
values[5]	4334	1			T1	16		T6	6		T12	64
values[6]	3998	1			T3	14		T12	40		T26	119
values[7]	3790	1			T11	8		T12	83		T26	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	302	1			T8	16		T46	64		T20	12
auto[0]	values[0]	values[1]	473	1			T40	11		T46	10		T48	13
auto[0]	values[0]	values[2]	265	1			T26	67		T226	11		T54	14
auto[0]	values[0]	values[3]	387	1			T27	4		T18	14		T19	65
auto[0]	values[0]	values[4]	196	1			T40	9		T47	9		T19	12
auto[0]	values[0]	values[5]	348	1			T63	76		T18	42		T162	12
auto[0]	values[0]	values[6]	423	1			T12	12		T31	11		T46	60
auto[0]	values[0]	values[7]	150	1			T208	14		T35	9		T240	10
auto[0]	values[1]	values[0]	201	1			T26	11		T44	8		T48	12
auto[0]	values[1]	values[1]	120	1			T44	13		T225	14		T162	15
auto[0]	values[1]	values[2]	214	1			T20	13		T172	12		T241	10
auto[0]	values[1]	values[3]	415	1			T242	6		T116	4		T44	19
auto[0]	values[1]	values[4]	389	1			T62	150		T197	23		T19	20
auto[0]	values[1]	values[5]	258	1			T47	10		T20	14		T198	12
auto[0]	values[1]	values[6]	363	1			T12	7		T48	12		T18	12
auto[0]	values[1]	values[7]	106	1			T31	13		T243	10		T198	8
auto[0]	values[2]	values[0]	523	1			T244	2		T161	10		T196	13
auto[0]	values[2]	values[1]	265	1			T46	36		T44	13		T221	22
auto[0]	values[2]	values[2]	222	1			T46	6		T169	6		T161	60
auto[0]	values[2]	values[3]	308	1			T12	11		T26	9		T46	23
auto[0]	values[2]	values[4]	228	1			T5	6		T224	16		T20	14
auto[0]	values[2]	values[5]	259	1			T40	15		T46	97		T201	21
auto[0]	values[2]	values[6]	240	1			T3	14		T26	13		T245	6
auto[0]	values[2]	values[7]	238	1			T11	8		T12	12		T47	16
auto[0]	values[3]	values[0]	414	1			T246	14		T170	14		T35	10
auto[0]	values[3]	values[1]	408	1			T236	14		T19	17		T215	11
auto[0]	values[3]	values[2]	189	1			T12	8		T26	12		T195	13
auto[0]	values[3]	values[3]	276	1			T44	11		T168	14		T225	11
auto[0]	values[3]	values[4]	297	1			T239	14		T47	13		T18	15
auto[0]	values[3]	values[5]	280	1			T26	38		T223	53		T227	13
auto[0]	values[3]	values[6]	192	1			T47	13		T19	36		T205	11
auto[0]	values[3]	values[7]	270	1			T12	11		T227	10		T215	12
auto[0]	values[4]	values[0]	273	1			T12	15		T26	15		T19	11
auto[0]	values[4]	values[1]	489	1			T48	83		T172	89		T215	12
auto[0]	values[4]	values[2]	211	1			T31	14		T19	14		T161	10
auto[0]	values[4]	values[3]	366	1			T18	33		T162	16		T234	9
auto[0]	values[4]	values[4]	373	1			T12	13		T44	12		T72	12
auto[0]	values[4]	values[5]	480	1			T12	10		T247	87		T35	14
auto[0]	values[4]	values[6]	215	1			T44	11		T172	28		T225	11
auto[0]	values[4]	values[7]	302	1			T19	8		T227	12		T170	7
auto[0]	values[5]	values[0]	326	1			T26	20		T19	34		T227	12
auto[0]	values[5]	values[1]	358	1			T197	10		T227	24		T206	16
auto[0]	values[5]	values[2]	190	1			T31	27		T17	13		T195	18
auto[0]	values[5]	values[3]	284	1			T46	9		T72	17		T198	10
auto[0]	values[5]	values[4]	265	1			T26	11		T222	4		T17	17
auto[0]	values[5]	values[5]	317	1			T46	8		T17	13		T248	10
auto[0]	values[5]	values[6]	166	1			T44	14		T249	4		T250	9
auto[0]	values[5]	values[7]	259	1			T12	14		T26	7		T92	16
auto[0]	values[6]	values[0]	298	1			T19	24		T227	12		T170	11
auto[0]	values[6]	values[1]	203	1			T19	18		T186	11		T193	7
auto[0]	values[6]	values[2]	214	1			T18	11		T251	8		T198	8
auto[0]	values[6]	values[3]	142	1			T215	14		T234	8		T193	11
auto[0]	values[6]	values[4]	301	1			T44	9		T229	12		T199	48
auto[0]	values[6]	values[5]	232	1			T12	17		T91	10		T18	12
auto[0]	values[6]	values[6]	505	1			T31	15		T172	65		T198	14
auto[0]	values[6]	values[7]	593	1			T12	19		T40	11		T252	6
auto[0]	values[7]	values[0]	197	1			T19	11		T198	11		T195	11
auto[0]	values[7]	values[1]	227	1			T97	8		T47	14		T170	14
auto[0]	values[7]	values[2]	289	1			T40	69		T227	13		T172	20
auto[0]	values[7]	values[3]	352	1			T12	9		T227	16		T198	12
auto[0]	values[7]	values[4]	163	1			T253	12		T227	65		T198	9
auto[0]	values[7]	values[5]	347	1			T12	13		T40	8		T17	8
auto[0]	values[7]	values[6]	267	1			T26	19		T17	10		T215	84
auto[0]	values[7]	values[7]	263	1			T19	9		T254	10		T198	11
auto[1]	values[0]	values[0]	86	1			T46	4		T20	8		T170	5
auto[1]	values[0]	values[1]	252	1			T40	9		T46	10		T48	7
auto[1]	values[0]	values[2]	235	1			T26	29		T226	9		T54	8
auto[1]	values[0]	values[3]	231	1			T18	6		T19	4		T170	5
auto[1]	values[0]	values[4]	432	1			T40	14		T47	28		T19	12
auto[1]	values[0]	values[5]	171	1			T18	7		T162	8		T54	17
auto[1]	values[0]	values[6]	187	1			T12	8		T31	33		T46	7
auto[1]	values[0]	values[7]	109	1			T255	12		T35	11		T50	8
auto[1]	values[1]	values[0]	157	1			T26	19		T44	12		T220	22
auto[1]	values[1]	values[1]	157	1			T44	7		T225	6		T162	18
auto[1]	values[1]	values[2]	226	1			T20	7		T172	129		T229	9
auto[1]	values[1]	values[3]	217	1			T44	21		T215	6		T213	8
auto[1]	values[1]	values[4]	274	1			T197	10		T19	9		T229	70
auto[1]	values[1]	values[5]	124	1			T6	6		T47	10		T20	6
auto[1]	values[1]	values[6]	440	1			T12	13		T48	45		T18	8
auto[1]	values[1]	values[7]	113	1			T31	14		T198	12		T54	15
auto[1]	values[2]	values[0]	137	1			T161	19		T196	7		T256	9
auto[1]	values[2]	values[1]	150	1			T46	7		T44	7		T192	9
auto[1]	values[2]	values[2]	358	1			T46	114		T161	11		T35	7
auto[1]	values[2]	values[3]	260	1			T12	9		T26	11		T46	90
auto[1]	values[2]	values[4]	118	1			T29	2		T20	6		T210	22
auto[1]	values[2]	values[5]	247	1			T1	16		T40	39		T46	13
auto[1]	values[2]	values[6]	222	1			T26	80		T172	9		T186	12
auto[1]	values[2]	values[7]	169	1			T12	8		T47	8		T161	7
auto[1]	values[3]	values[0]	143	1			T170	6		T35	10		T54	8
auto[1]	values[3]	values[1]	340	1			T19	11		T215	9		T257	5
auto[1]	values[3]	values[2]	171	1			T12	12		T26	8		T195	11
auto[1]	values[3]	values[3]	310	1			T44	9		T225	9		T201	9
auto[1]	values[3]	values[4]	290	1			T47	7		T18	5		T19	9
auto[1]	values[3]	values[5]	96	1			T26	4		T227	7		T20	10
auto[1]	values[3]	values[6]	173	1			T47	8		T19	13		T205	9
auto[1]	values[3]	values[7]	188	1			T12	9		T227	28		T215	12
auto[1]	values[4]	values[0]	239	1			T12	5		T26	10		T19	9
auto[1]	values[4]	values[1]	115	1			T48	13		T172	6		T215	8
auto[1]	values[4]	values[2]	175	1			T31	6		T194	24		T19	6
auto[1]	values[4]	values[3]	153	1			T18	10		T162	7		T234	11
auto[1]	values[4]	values[4]	291	1			T12	12		T44	8		T72	11
auto[1]	values[4]	values[5]	269	1			T12	11		T35	11		T50	8
auto[1]	values[4]	values[6]	201	1			T44	9		T172	11		T225	9
auto[1]	values[4]	values[7]	207	1			T19	12		T227	8		T170	13
auto[1]	values[5]	values[0]	283	1			T26	9		T19	19		T227	8
auto[1]	values[5]	values[1]	181	1			T197	10		T227	47		T258	10
auto[1]	values[5]	values[2]	184	1			T31	23		T17	7		T195	6
auto[1]	values[5]	values[3]	279	1			T46	76		T45	24		T72	3
auto[1]	values[5]	values[4]	232	1			T26	53		T17	3		T20	9
auto[1]	values[5]	values[5]	281	1			T46	12		T17	12		T172	12
auto[1]	values[5]	values[6]	101	1			T44	6		T250	11		T259	5
auto[1]	values[5]	values[7]	332	1			T12	6		T26	13		T40	10
auto[1]	values[6]	values[0]	331	1			T19	8		T227	12		T170	9
auto[1]	values[6]	values[1]	267	1			T19	9		T186	9		T193	13
auto[1]	values[6]	values[2]	144	1			T18	9		T198	12		T225	4
auto[1]	values[6]	values[3]	192	1			T215	6		T234	18		T193	81
auto[1]	values[6]	values[4]	110	1			T44	11		T229	8		T199	9
auto[1]	values[6]	values[5]	178	1			T12	6		T18	10		T19	10
auto[1]	values[6]	values[6]	208	1			T31	5		T172	8		T198	6
auto[1]	values[6]	values[7]	298	1			T12	4		T40	17		T20	5
auto[1]	values[7]	values[0]	183	1			T19	67		T198	9		T195	10
auto[1]	values[7]	values[1]	193	1			T2	2		T47	37		T170	6
auto[1]	values[7]	values[2]	122	1			T40	7		T227	7		T234	15
auto[1]	values[7]	values[3]	349	1			T12	19		T227	50		T198	8
auto[1]	values[7]	values[4]	84	1			T227	10		T198	11		T260	10
auto[1]	values[7]	values[5]	447	1			T12	7		T40	17		T17	15
auto[1]	values[7]	values[6]	95	1			T26	7		T17	14		T215	6
auto[1]	values[7]	values[7]	193	1			T19	24		T198	9		T234	11